12/21/98 -1 Seminar Productieautomatisering 2000+Gerrit Muller Specification and design of a complex...

12/21/98 -1

Seminar Productieautomatisering 2000+ Gerrit Muller

Specification and design of a complex system:The ASML waferstepper

Gerrit Muller

7-1-1999

Delft

Seminar Productieautomatisering 2000+

12/21/98 -2


The Market

PC’snon PCcomputing

consumerelectronics

communications otherapplications

IC’s memory othersemiconductors

equipment

32% 16% 17% 18% 17%

semiconductor salesby end-use rmarket

source: Dataquest, ING Barings research www.asml.com

ASMLsales 1997: 1.8 Gflnet income: 0.3 Gfl

steppers

GDP

1997 2002

33.4 T$ 39.4 T$

electronicsales

semiconductorsales

902.4G$ 1284.2G$

151.7G$ 330.6G$

Equipmentsales

22.3G$ 42.8G$

Steppers 3.6G$ 7.3G$

17% 26%

15%

16%

13%

17%

3% 3%

12/21/98 -3


What is a waferstepper?

Lightsource

Mask (Reticle)

Lens

Wafer

Die

12/21/98 -4


Step & Scan technology

Slit

reticle

wafer

Lens

Scanningfieldsize

Steppingfieldsize

250 mm/s

Lens

12/21/98 -5


Main specifications

Imaging Overlay Productivity

linewidth: 180 nm (1999)

critical dimension control

AA (single machine) 40 nmBC (matched) 60 nm

96 Wafers per hour

For comparison: Wafer diameter 200 mmDie size ca.: 20*20 mm2

12/21/98 -6


Products

Steppers 5500

Scanners

300 mm,high throughput

Non opto

i-line

248nm

248nm

i-line193nm

12/21/98 -7


Product roadmap

/250C i-line stepper

/300C DUV stepper

/500 DUV scanner

/400 i-line scanner

/900 193 nm scanner

/700 DUV scanner

S700 DUV scanner T700 DUV scanner

T1100 193 nm scanner

5500 stepper body

5500 scanner body

Atlas 300 mm body

Ath

ena/

TIS

Qu

adru

pol

e

2 k

Hz

lase

r

S400 I-line scanner T400 I-line scanner

/300D

12/21/98 -8


Mechanical Design

• dynamic performance• stage technology• servo technology

• cooperation with Philips CFT, NatLab

• design rule: 10 nm-> 1 nm -> subnanometer

12/21/98 -9


Example dynamic performance

6 degrees of freedom:• x, y, Rz• z, Rx, Ry• v = 250 mm/s• a = 10 m/s2

• control frequency: 4 kHz (250 sec)• position measerument by interferometers

manycables

12/21/98 -10


Optics design

• Projection design• Illumination• Light source (lasers)• Intensity, abberations, distortion, stray light, uniformity • cooperation with Zeiss, Cymer

• 365 nm -> 248 nm -> 193 nm (-> 157 nm?)• extensive modelling and simulation

12/21/98 -11


Example projection design

ca 12 lens elements

• temperature and pressure controlled• anti reflection coatings• 193 nm CaF

1 m.

12/21/98 -12


Control architecture

• Functions implemented in software:• Calibration, Preparation, Expose, Batch control

• Electronics infrastructure

• Integration

12/21/98 -13


Modular subsystems

illuminator light source

reticle stage

lens

wafer stage

base frame

reticlehandling

waferhandling

contaminationandtemperaturecontrol

electronicscabinets

UIconsole

measurement

12/21/98 -14


System engineering

mechanics optics control measurement contamination &temperature

imaging

overlay

productivity

12/21/98 -15


Overlay budget

ProcessOverlay80 nm

Reticle15 nm

MatchedMachine60 nm

Processdependencysensor5 nm

SingleMachine30 nm

LensMatching25 nm

MatchingAccuracy5 nm

Stageoverlay12 nm

Globalalignmentaccuracy6 nm

Stage gridaccuracy5 nm

Metrologystability6 nm

Positionaccuracy7 nm

alignmentrepro5 nm

Interferometerstability1 nm

Framestability2.5 nm

trackingerror phi75 nrad

trackingerror X, Y2.5 nm

Off axispos measaccuracy4 nm

Stage Al.pos. meas.accuracy4 nm

Systemadjustmentaccuracy2 nm

Off axisSensorrepro3 nm

Blue alignsensorrepro3 nm

trackingerror WS2 nm

trackingerror RS1 nm

12/21/98 -16


Development phases

sps

plancost, effort,time

prs

eps

eds

integrationplan

tps

1 2 3 40

feasibility definition system design integration field monitoring

tpd

alfa test TAR

prototype

tps

subsystem spec subsystemdesign

engineering verification

sds

beta test TAR

business impact

12/21/98 -17


SPS contents checklist

performance requirements• imaging• overlay• throughput

overviewdoc tree, structure

functional requirements draft• functional model (extern) draft

product lifecycleoption structure draft

machine requirements• design constraints, f.i. robustness• safety• reliability• COG, COO• interoperability

operations requirements draft• serviceability• manufacturability

option structure

environment requirements• wafer, reticles• power, gases, water, etc.• weight size•transport

functional requirements• functional model (extern)• factory integration• user interface

operations requirements• serviceability• manufacturability

1 2 30

feasibility definition system design subsystem spec engineeringsubsystemdesign

12/21/98 -18


SDS contents checklist

decomposition in subsystems draft

performance budgets draft

functional model (design) draft

overview

control architecture

costprice budget draft

consumable budget draft

diagnostic analysis

safety design

accessabilityset up sequencetolerance budgetcycle time budget

mechanical layout budgets draft

SW architecture draft

Electrical architecture

handling interfacespower, gas, water, etc budgets draft

doc tree, structure draft doc tree, structureoverview draft

decomposition in subsystems

performance budgets

functional model (design) concept functional model (design)

function allocation draft function allocation concept function allocation

control architecture draft

SW architecture

mechanical layout budgetspower, gas, water, etc budgets

safety analysis

reliability/uptime budget draft reliability/uptime budget

costprice budgetconsumable budget

1 2 30

feasibility definition system design subsystem spec engineeringsubsystemdesign

diagnostic design

interoperability design

transport design

12/21/98 -19


Definitions

PRS Product Requirement Specification What should the product be Marketing

SPS System Performance Specification What will the product be SESDS System Design Specification How will it be made SETPS Test Performance Specification What and how will it be tested SETAR Test Acceptance Report Testresult SE

EPS Element Performance Specification What D&EEDS Element Design Specification How D&ETPS Test Performance Specification What and how will it be tested D&ETAR Test Acceptance Report Testresult D&EEPS, EDS, TPS are recursively applied from subsystem level to monodisciplinary module level

12/21/98 -20


Concurrent engineering, Integration

subsystem1 design

subsystem2 design

Subsystem n design

dynamical performance

imaging

overlay

metrology

levelling

Integrationprototypes

Finalintegration

Concurrentengineering

• • • • •

12/21/98 -21


Moore’s law (or challenge?)

97 98 99 00 01 02 03 04 05 06

1994roadmap

1997roadmap

1998revision

1999proposal

leadingedgecustomers

250 180 130

250 180 150 130

250 180 150 125

250 180 130 90

250 180 130 100

SIA

linewidth in nm.

12/21/98 -22


97 98 99 00 01 02 03 04 05 06

1994roadmap

250 180 130

SIA

leadingedgecustomers

250 180 130 100

Rule of thumb: Process overlay = linewidth / 3

overlay

overlay

80overlay

60 45

80 60 45 35

12/21/98 -23


Overlay budget

ProcessOverlay80 nm

Reticle15 nm

MatchedMachine60 nm

Processdependencysensor5 nm

SingleMachine30 nm

LensMatching25 nm

MatchingAccuracy5 nm

Stageoverlay12 nm

Globalalignmentaccuracy6 nm

Stage gridaccuracy5 nm

Metrologystability6 nm

Positionaccuracy7 nm

alignmentrepro5 nm

Interferometerstability1 nm

Framestability2.5 nm

trackingerror phi75 nrad

trackingerror X, Y2.5 nm

Off axispos measaccuracy4 nm

Stage Al.pos. meas.accuracy4 nm

Systemadjustmentaccuracy2 nm

Off axisSensorrepro3 nm

Blue alignsensorrepro3 nm

trackingerror WS2 nm

trackingerror RS1 nm

2003:35 nm

Dramaticincrease ofcomplexity!

12/21/98 -24


Summary ASML developement strategy

• Concurrent engineering• short development cycle time

• Networking• market• technology base• flexibility

• System engineering• modularity• short integration

• Family concept• upgradeability• follow SIA roadmap• reuse, risk reduction over generations

12/21/98 -25


Stellingen

• Multi disciplanary design process and skills required

• Most unforeseens show up during integration:– force integration start as early as possible– integration is always underestimated

• Manage the design and integration by a few key parameters,– however watch out for sub - optimization

Date post:	31-Mar-2015
Category:	Documents
Upload:	nico-raven
View:	232 times
Download:	2 times

12/21/98 -1 Seminar Productieautomatisering 2000+Gerrit Muller Specification and design of a complex...

Documents