VHDL VHDL Structural ModelingDigital Logic

OutlineStructural VHDLUse of hierarchyComponent instantiation statementsConcurrent statementsTest Benches

A general VHDL designentity entity-name is [port ( In_1, In_2, In_3 : in bit; out_1, out_2 : out bit; inout_1, inout_2 : inout bit);] end [entity] [entity-name];architecture arch-name of entity-name is [declaration]begin architecture bodyend [architecture] [arch-name];

entity

architecture

entity-name

In_1

In_2

In_3

input

component

Out_1

inout

Out_2

process

output

concurrent assignment

Inout_1

Inout_name

arch-name

Component and Signal DeclarationsDECLARATION of architecture contains:component declarationsignal declarationExample of component declarationcomponent AND2_OP port (A, B : in bit; Z : out bit);end component;Example of signal declarationsignal list-of-signal-names : type-name [ := initial-value] ;ex) signal sig_a, sig_b : bit ;

Concurrent Assignmententity fulladder_df is port ( A, B, Cin : in bit; Sum, Cout : out bit);end fulladder_df;

architecture data_flow of fulladder_df isbegin Sum

Processentity fulladder_bh is port ( A, B, Cin : in bit; Sum, Cout : out bit);end fulladder_bh;

architecture behavioral of fulladder_bh isbegin process (A , B, Cin) begin if ( A = 0 and B = 0 and Cin = 0) then Sum

Component Instantiation StatementsThe statement part of an architecture body of a structural VHDL description contains component instantiation statementsFORMATlabel : component_name port map (positional association of ports);label : component_name port map (named association of ports);EXAMPLESA1 : AND2_OP port map (A_IN, B_IN, INT1);A2 : AND2_OP port map (A => A_IN, C => C_IN, Z => INT2);

Componententity fulladder_st is port ( A, B, Cin : in bit; Sum, Cout : out bit);end fulladder_st;

architecture structral of fulladder_st is

componenet XOR3_OP port ( IN_A, IN_B, IN_C : in bit; OUT_Z : out bit ); end component;

componenet AOI3_OP port ( IN_A, IN_B, IN_C : in bit; OUT_Z : out bit ); end component;begin XOR : XOR3_OP port map (A, B, Cin, Sum); AOI : AOI3_OP port map (A, B, Cin, Cout);end structral;

A

B

Cin

XOR

Sum

fulladder_st

AOI

Cout

Hirarchical StructureCan combine 4 fulladder_xx functions (defined earlier) to form another 4-bit fulladder function component fulladder_st port (A, B, Cin : in bit; Sum, Cout : out bit); end component;

signal sig_c0, sig_c1, sig_c2 : bit;

begin FA0 : fulladder_df port map (A(0), B(0), Cin, Sum(0), sig_c0); FA1 : fulladder_bh port map (A(0), B(0), sig_c0, Sum(0), sig_c1); FA2 : fulladder_st port map (A(0), B(0), sig_c1, Sum(0), sig_c2); FA3 : fulladder_bh port map (A(0), B(0), sig_c2, Sum(0), Cout);end hirarchical;entity fulladder_4bit is port (A, B : in bit_vetcor (3 downto 0); Cin : in bit; Sum : out bit_vetcor (3 downto 0); Cout : out bit);end fulladder_4bit ;

architecture hirarchical of fulladder_4bit is

component fulladder_df port (A, B, Cin : in bit; Sum, Cout : out bit); end component;

component fulladder_bh port (A, B, Cin : in bit; Sum, Cout : out bit); end component;

FA0

FA1

FA2

FA3

B(3)

A(3)

B(2)

A(2)

B(1)

A(1)

B(0)

A(0)

Cin

Cout

Sum(3)

Sum(2)

Sum(1)

Sum(0)

sig_c0

sig_c1

sig_c2

fulladder_4bit

Example of a four-bit registerentity reg4 is port ( en, clk : in bit; d : in bit_vector (3 downto 0); q : out bit_vector (3 downto 0));end reg4;Let us look at a 4-bit register built out of 4 D latches

reg4

d(3)

d(2)

d(1)

d(0)

en

clk

q(3)

q(2)

q(1)

q(0)

Behavioral Description of Registerarchitecture behavior of reg4 isbegin process variable stored_d : bit_vector (3 downto 0); begin if (en = 1 and clk = 1) then stored_d(3) := d(3); stored_d(2) := d(2); stored_d(1) := d(1); stored_d(0) := d(0); endif; q(3)

Structral Composition of Register entity d_latch is port (d, clk : in bit; q : out bit);end d_latch;

architecture arch_dff of d_latch isbegin process (clk) begin if (clk = 1) then q

Structural Description of Registerarchitecture struct of reg4 is

component d_latch port (d, clk : in bit; q : out bit); end component;

component and2_op port (x, y : in bit; z : out bit); end component;

signal int_clk : bit;

begin DFF3 : d_latch port map(d(3), int_clk, q(3)); DFF2 : d_latch port map(d(2), int_clk, q(2)); DFF1 : d_latch port map(d(1), int_clk, q(1)); DFF0 : d_latch port map(d(0), int_clk, q(0)); AND : and2_op port map(en, clk, int_clk);end struct;

DFF3

d(3)

d(1)

d(2)

d(0)

en

clk

q(3)

q(2)

q(1)

q(0)

DFF2

DFF1

DFF0

reg4

int_clk

AND

Mixed ModelsModels need not be purely structural or behavioralOften it is useful to specify a model with some parts composed of interconnected component instances and other parts using processesUse signals as a way to join component instances and processesA signal can be associated with a port of a component instance and can be assigned to or read in a process

Example of Mixed Modeling : Multiplier

clk

product

entity

architecture

multiplier

reset

multiplicand

multiplier

mixed

arith_unit

multiplier_sr

process

partial_product

result

full_product

arith_control

mult_bit

mult_load

result_en

Example of Mixed Modeling : Multiplierentity multiplier is port ( clk, reset : in bit; multiplicand, multiplier : in integer; product : out integer);end multiplier;

architecture mixed of multiplier is

signal partial_product : integer; signal full_product : integer; signal arith_control, result_en, mult_bit, mult_load : bit;

compononent shift_adder port ( addend, augend : in integer; arith_control : in bit; sum : out interger); end component; compononent shift_adder port ( addend, augend : in integer; arith_control : in bit; sum : out interger); end component; compononent shift_adder port ( addend, augend : in integer; arith_control : in bit; sum : out interger); end component;begin arith_unit : shift_adder port map ( addend => multiplicand, augend =>full_product, sum => partial_product, add_control => arith_control); result : reg port map (d => partial_product, q => full_product, en => result_en, reset => reset); multiplier_sr : shift_reg port map (d => multiplier, q => mult_bit, load => mult_load, clk => clk); product

Concurrent Signal Assignmententity XOR2_OP is port (A, B : in bit; Z : out bit);end XOR2_OP;

architecture AND_OR of XOR2_OP isbegin Z

Concurrent Signal Assignmententity XOR2_OP is port (A, B : in bit; Z : out bit);end XOR2_OP;

architecture AND_OR of XOR2_OP is signal INT1, INT2 : bit;begin -- different order, same effect INT1

Concurrent and Sequential StatementsVHDL provide both concurrent and sequential signal assignmentsExampleSIG_A

Data Flow Modeling of Combinational LogicConsider a parity function of 8 inputs

entity EVEN_PARITY is port ( BVEC : in bit_vector(7 downto 0); PARITY: out bit);end EVEN_PARITY;

architecture DATA_FLOW of EVEN_PARITY isbegin PARITY

Alternative Logic Implementations of PARITYTREE CONFIGURATIONarchitecture TREE of EVEN_PARITY is signal INT1, INT2, INT3, INT4, INT5, INT6 : bit;begin INT1

Alternative Logic Implementations of PARITYCASCADE CONFIGURATIONarchitecture CASCADE of EVEN_PARITY is signal INT1, INT2, INT3, INT4, INT5, INT6 : bit;begin INT1

Alternates Architecture BodiesThree different VHDL descriptions of the even parity generator were shownThey have the same interface but three different implementationUse the same entity description but different architecture bodiesarchitecture DATA_FLOW of EVEN_PARITY is ...architecture TREE of EVEN_PARITY is ...architecture CASCADE of EVEN_PARITY is ...

Test BenchesOne needs to test the VHDL model through simulationWe often test a VHDL model using an enclosing model called a test benchA test bench consists of an architecture body containing an instance of the component to be testedIt also consists of processes that generate sequences of values on signals connected to the component instance

Example Test Benchentity test_bench isend test_bench;

architecture test_reg4 of test_bench is

signal sig_d, sig_q : bit_vector (3 downto 0); signal sig_en, sig_clk : bit;

begin

tb_reg4 : reg4 port map (sig_en, sig_clk, sig_d, sig_q); process begin d

SummaryStructural VHDLUse of hierarchyComponent instantiation statementsConcurrent statementsTest Benches