13.Clock Stand07

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VLSI System Design NCKUEE-KJLEE

Clock Strategy

Clocked Systems

Latch and Flip-flops System timing

Clock skew

High speed latchdesign

Phase locked loop Dynamic logic

Multiple phase clock

Clock distribution

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Clocked Systems

Most VLSI systems are a combination of

pipelines and

f ini t e state machines(FSM)

Finite state machine

Pipelined systems

Logic...

LogicD Q

CLK CLK

D QInput outputD Q

CLK or CLKS

Comb.Logic

Q D

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Single-phase clock timing

waveformsTc: clock cycle time (period)

Ts: setup time -- the time beforethe clock edge during whichthe data input (D) has to be

stable

Th: hold time -- the time after theclock edge during which thedata input (D) has to remainstable

Tq: clock-to-Q delay -- The delayfrom the clock edge to the Q

output

Clock

Cycle Time (Tc)

Setup Time (Ts)

Hold Time (Th)

data

Clock-to-Q Delay (Tq)

Q

CLK

D Q

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Latches and flip-flops

(a) Negative Latch (Level sensitive)

(b) Positive Latch (Level sensitive)

clk

D

Q

clk

D

Q

CLK

0

1

s

D

Q

CLK

0

1s

DQ

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Latches and flip-flops

(c) Positive edge-triggered register(single-phase clock)

(d) Pass transistor/inverter implementation

clk

D

QM

QCLK

0

1 s

D

CLK

0

1s

QQM

master slave

clk=0

clk=1

master slave

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System timing

RegisterA

CombinationalLogicTd

RegisterBclock

Tq Ts

(A) Positive-edge triggered

Tq Td Ts

Tc

Tc >Tq + Td + Ts

(B) Alternatively, one may use latches as storage elements to save area.

LatchA

CombinationalLogic

Td

LatchB

CombinationalLogic

Tdclock

Tq Ts

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(C)

LatchA

CombinationalLogicTda

LatchBclock

Tq Ts Latchc

CombinationalLogicTdb

A B

Tc1 Tco

Tqa Tda Tsb Tqb Tdb Tsc

Tc1>Tqa+Tda+Tsb Tco>Tqb+Tdb+Tsc

If Tc=Tc1+Tco and Tc1=Tco, Tqa=Tqb,

Tsb=Tsc

=> The limit is Tc = Tda + Tdb + 2(Tq+Ts)

System timing (cont)

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Racing due to clock skew

1. If Tc2 > Tc1 + tq1 + td2

M2 may sample a w rong

dat a (current data)

Transparency problem

2. If Tc1 + tq1 + td2 >Tc (cycle time)

M2 cannot sample t heprevious data

REG1-bitd q

Logic

REG1-bitd q

delaydelayTc

1Tc

2

M1

M2

Td2

1 0

clk

Tc1

Tc2

Td2 Old Data New Data

clk

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Single-phase clock using D-FF

C2 C1

C1 C2L1 L2

C1 = C2 or C2 = C1

C2 C1 C1 C2

C1C2

Wrong datain L2

Correctdata

C1

C2

1) C2=C1

2) C1=C2

Wrongonly if

FSM --> "feedback" orPipeline --> "feedthrough"

Comb.Logic

L1 L2Comb

CLK

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To eliminate (reduce) time skew

(clock skew)1.Balanced delay clock driver 2.Use buffers where necessary

3.Very careful simulation(HSPICE)

4.Very small rise and fall time onthe clock-- large buffer for large

load5.Multiple clocking strategies

clk-in clk

clk

clk-in clk

clk

usually slightly smaller than the inverter

clkclk

clkclk

Large Load

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Some Implementations of clockedlatches

Use a weak trickle inverter

small inverter

(low-gain, smallerW or large L)

-ck

ck

D Q

Transmission-gate latch

D

Q

D

Q

clk

clk

clk

clk

eliminate a metalconnection

smaller area

compared with a tri-state buffer

D

c lk

c lk

c lk

c lk

bufferedinput

or

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Typical symbolic layouts forlatches

D

Qclk

clk

clk

clk

-clk

clkclk

-clk

D Q

-clk

clkclk

-clk

D Q

VDD

V

SS

QD

clk -clk

(a)

VDD

VSS

QD

clk -clk

VDD

VSS

QD

clk -clk

(b) (c)

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logic gate based latches

Q

clk

D

Q

-Q

D

clk

(a) Level sensitive

Q

-Q

D

clk

(b) Edge triggered

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Asynchronously settable andresettable F/Fs

-clk

clkclk

-clk

-clk

clk

clk

-clk

-reset

D

Q

-clk

clkclk

-clk

-clk

clk

clk

-clk

-reset

D

Q

-set

(a)

(b)

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Dynamic single clock latches

The feedback inverter and transmission gate are eliminated.

The latched value is stored on the capacitance of the input to

the inverter (mainly gate capacitance) Clock-to-Q (Tq) is very small need to be very careful to

prevent transparency problem.

Internal inversion of the clock is often necessary.

Dynamic nodes should be always refreshed or clamped to aknown state when in stand-by or low-power mode.

clk

-clk

D -Q

clk

-clk

D

(b)(a)

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clk

D

-clk

clk

-clk

D Q

-clk

clk

clk

-clk

D

-clk

clk

Q

(d)master-slave F/F(c)Tristate inverter (e)

Dynamic single clock latches (cont)

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Refreshing for Dynamic latches

Dynamic storage nodes areusually a gate capacitance.

Assume the leakagecurrent= 1 nA

and the storage

capacitance = 0.02PF

Even if the storage of thecorrect state is unimportant,the leakage may cause thestorage node to assume a levelthat causes the inverter todraw significant current.

large current

si

VC 100

10

51002.0

9

12 ==

must refresh every 100 s

5V -> 2.5V

Ph l k d l (PLL) l k

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Phase locked loop (PLL) clocktechniques

(1) To synchronize internal and external clocks.

(2) To synchronize data transfers between chips.

(3) To operate the internal clock at a higher rate.

output pad

dclk

clock

clockpad

clockroute

dclk

+dpad

clock

dclk

data out

(a) Without PLL

output pad

dclk

clock

clockpad

clockroute

dclk

+dpad

clock

dclk

data out

PLLchip

(a) With PLL

(1)

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(2) (3)

clockPLL

clockPLL

system clock

bus

g speetristate bus

To ensure the output of chipsare synchronized with eachother.

output pad

dclk

clock

clock

pad

clockroute

dclk

+dpad

clock

dclk

PLLchip

/ 4

Clock rate

clock

d clockclk

at d

4clk

4

PLL techniques

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Block diagram of a PLL circuit

PhaseDetector Chargepump Filter VCO

U

D

Ffb

referenceclock(Fin)

n*Fin

Phase detector: detect the difference between Ffb and Fin.

If Ffb > Fin =>D pulseIf Ffb > Fin =>U pulse

Charge pump: charge or Discharge a capacitor according to D and U.

Filter: filter the capacitor output (smoother).VCO: Change the oscillation frequency depending on the control voltage.(Voltage Control Oscillator)

n

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Phase Detector

If F1 falls before F2

=> UP=1

If F2 falls before F1

=> DN=1

UP

DN

16/8

16/8

16/8

16/8

16/8

16/8

16/8

16/8

16/8

16/8

16/8

16/8

F1

F2

16/8

16/8

F1

F2

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Charge Pump

CAP charges when CHGUP=1discharge when CHGDN=1

N2

N1

N3 N4

P12/5

/5

10/2

40/2

40/2

P-REF

N-REF

P-SWITCHSW0

SW1

P-SWITCH SW0

SW1

P-REF

N-REF

CHGUP

CHGDN

CAP

P1

40/2

N540/2

SW0

SW1

10/210/2

8/1

16/1

IN

Bias circuit

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Filter

in

2/6

2400/6

4/6

2400/6

out

outin

controlvoltage

32/1

16/1

16/1

32/1

32/1

16/1

16/1

32/1

16/1

16/1

32/116xFsc

13stages

32/1

VCO

VCO

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Metastability Problem

If the setup or hold time is notsatisfied, I.e., D changes at theactivation edge of the clock, thenthe output Q will have a state

depending on the timing relationbetween D and CLK

QQD

clk

clkdelay=2.2ns

Q

-Q

delay=2.3ns

Q

-Q

metastablepoint

delay=2.4ns

Q

-Q

metastablepoint

NoProblem

Long delay

Outputerror

clock

2ns

delay

4ns data

Metastable state in a pair of

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Metastable state in a pair ofinverters

To Solve the metastabilityproblem:

Set up t ime is short er thanthe clock- to-Q delays in asynchronizat ion syst em.

For asynchronous input :need a special circuit

called synchronizer.

BAInv1

Inv2

metastablepoint

0V 2.5V 5V

VA

VB Inv1

Inv2

Single phase N P CMOS dynamic

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Single-phase N-P CMOS dynamiclogic

Combine N-P sect ion of domino logic w it h clocked CMOS(C2MOS) latch as t he output stage.

clk -clk

clk

-clk

n-logicblock

p-logicblock

C2MOS latch

From n or buffered p-logic

n-p CMOS clk logic stage

to -clk section

to n-logic blocksto p-logicblocks

to n-logicblocks

to p-logicblocks

Inputs from

-clk stages

a

clk -clk

clk

-clk

n-logicblock

p-logicblock

C2MOSlatch

n-p CMOS -clk logic stage

to -clksection

b

evaluationPrecharge

(c)

-clklogic

clklogic

-clklogic

Prechargeevaluation

evaluationPrecharge

clk -clk0 11 0

Design rules for N-P CMOS

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Design rules for N-P CMOSdynamic logic

Two problems to be solved

1.Each sect ion must beint ernally race free.

2.When dif ferent sect ion arecascaded t o from pipelinedsystem, clock skew shouldnot cause a problem.

R1: During precharge, logic-blocks must be sw it chedoff.

R2: During evaluat ion,int ernal input s can makeonly one t ransit ion.

When a st at ic logic is used ina N-P CMOS dynam ic logic, itshould be placed aft er

dynamic logic (I .e., oneshould keep t he st atic logicup to t he C2MOS lat ch.

Reason: stat ic logic af t er

creat es a glit ch at it s output .

clkclk

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R3: There exists in each logic block

at least one dynamic gat et hat is separat ed fromt he previous C2MOSoutput stage by an even numberof invent ions.

or

R4: The total number of inversionsbet w een t w o consecut ive

C2MOS stage is even.

Reason:

C2

MOS

C2

MOS

or Domino The same evaluationphase in a section

1 1

clk clk

0 0

clk clk

or

clk

-clk

C2MOS latch

(clk section)

clk

-clk

even number ofinversions

at least onedynamic stage

C2MOS latch

output stage

(-clk section)

OR

even umber of inversions

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Two phase clocking

D Q

phi2

-phi2

phi1

-phi1

DFF1

(a)

C

2C

1

phi1

=1

phi2

=0

C2C1

phi1

=0

phi2=1

phi1

phi2

(b)

(d)C

2C1

phi

1

=1

phi2=0

phi1

phi

2

logic

logic

phi1

phi2

small dealy overlap

skewedclokcs

(c)

overlap

slow risetime

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Two phase clock generation

1. Globally distribute two clockswith or without theircomplements.

3. A single global clock and locallygenerated two-phase clocks

Two-phase clock generator

clk

Delay for non-overlapperiod

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Two phase registers

-phi1

D Q

phi1

-phi2

phi2

DEF1

-phi1

phi

1

D n1

Q-phi

2

phi

2

DEF2

-phi1

phi1

D n2

Q

-phi2

phi2

DEF3Both of these dynamic registers

have to drive a local storage gate.

D Q

phi1 phi2

DEF1A

high level =VDD

-Vtn

(a)

Q

phi1 phi2DEF1B

p leakers

(b)D

Q

clk

(c)

D

T h l i

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Two phase logic

1. Static logic with two phaseregisters

2. Dynamic logic

Logic Logic

-phi1

phi1

-phi2

phi2

phi1

n-logicphi

1n-logic

-phi1

phi1

-phi2

phi2

from phi2

stageto phi

1stage

phi1

precharge phi1

logic

latch phi2

data

evaluate phi1logic

precharge phi

1

logic

latch phi2data

phi2

evaluate phi2

logic

evaluate phi2

logicprecharge phi

2

logic

latch phi1

data

F Ph l k

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Four-Phase clock

11

12

2

324

Four-Phase logic clocking method

nonoverlapping

clk1

clk2clk

3

clk4

D

clk1

clk12

clk3

clk3clk1

clk34

Q

clk1

clk2

clk3

clk4

(b)

D

clk1

clk2

clk3

clk3

clk1

clk4 Q

inv1 inv2

n1

(a)

clk1

SlaveLatch

Logic MasterLatch

Logic

clk2 clk3 clk4

Cl k di t ib ti

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Clock distribution

1. A single large buffer

2. A distributed-clock-treeapproach

n-bit datapath

n-bit datapath

n-bit datapath

n-bit datapath

n-bit datapath

n-bit datapath

n-bit datapath

n-bit datapath

n-bit datapath

n-bit datapath

n-bit datapath

n-bit datapath

clock

delays have to matchbetween stages

T d i l k t t

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Trends in clock strategy

For first-time designer, use static logic, single-phasestatic registers.

For standard cell and gate-array design, single-phasemay be the only choice.

Two phase clocking make timing design of RAMs, ROMs

and PLAs easier. In modern process and circuits, cycle time is the main

concern => single phased

Processes are extremely dense => single phase

Date post:	04-Apr-2018
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13.Clock Stand07

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