13.ECE 301 - Sequential Logic Modules II

7/27/2019 13.ECE 301 - Sequential Logic Modules II

1/25

VITU N I V E R S I T Y

ECE 301 - VLSI System Design(Fall 2011)

Verilog HDL -

Prof.S.Sivanantham

VIT UniversityVellore, Tamilnadu. India

E-mail: [email protected]


2/25

After completing this lecture, you will be able to:

Describe how to model counters (ripple/synchronouscounters and modulo r counters)

Describe how to model timing generators

ECE301 VLSI System Design FALL 2011 S.Sivanantham


3/25

Counter is a device that counts the input events such as input pu ses or c oc pu ses.Types of counters:

SynchronousAs nchronous ri le counters:

Binary counter (up/down counters)Synchronous counters:

Binary counter (up/down counters)BCD counter (up/down counters)


Gray counters (up/down counters)


4/25

J

CK

Q J

CK

Q J

CK

Q

clk

Q' K Q' K Q' K 1 2 3

clk

qout [0]

qout [1]



5/25

-

module ripple_counter(clk, qout);input clk;output reg [2:0] qout;wire c0, c1;// the body of the 3-bit ripple counter

assign c0 = qout[0], c1 = qout[1]; qout[0]


6/25

// a 3-bit ripple counter with enable controlmodule ripple_counter_enable(clk, enable, reset_n, qout);input clk, enable, reset_n;output reg [2:0] qout;wire c0, c1;

-assign c0 = qout[0], c1 = qout[1];always @(posedge clk or negedge reset_n)

if (!reset_n) qout[0]


7/25

---

// an N-bit ripple counter using generate blocksmo u e r pp e_coun er_genera e c , rese _n, qou ;

parameter N = 4; // define the size of counter input clk, reset_n;output reg [N-1:0] qout;// the body of the N-bit ripple counter genvar i;

generate for (i = 0; i < N; i = i + 1) begin: ripple_counter always @(negedge clk or negedge reset_n)

if (!reset_n) qout[0]


8/25

// an n-bit binary counter with synchronous reset and enable control.

_ , , , ,

parameter N = 4;input clk, enable, reset;output reg [N-1:0] qout;output cout; carry output

// the body of the N-bit binary counter alwa s osed e clk if (reset) qout


9/25

--- // an N-bit binary up/down counter with synchronous reset and enable control.module binary_up_down_counter_reset(clk, enable, reset, upcnt, qout, cout, bout); parameter N = 4;input clk, enable, reset, upcnt;output reg [N-1:0] qout;

,// the body of N-bit up/down binary counter always @(posedge clk)

if (reset) qout


10/25

--- // an N-bit up/down binary counter with synchronous reset and enable control.

_ _ _ , , , , , ,

Parameter N = 4;// Enable up count (eup) and enable down count (edn)// cannot be set to one simultaneously.input c , reset, eup, e n;output reg [N-1:0] qout;

output cout, bout;// the bod of the N-bit binar counter always @(posedge clk)

if (reset) qout


11/25

---

// an exam le to illustratin the cascade of two u /down counters.module up_dn_bin_counter_cascaded(clk, reset,eup, edn, qout, cout, bout); parameter N = 4;input clk, reset, eup, edn;ou pu - : qou ;output cout, bout;

// declare internal nets for cascading both counterswire cout1, bout1;

// The body of the cascaded up/down counter _ _ _ _ _ , , , , , ,

up_dn_bin_counter #(4) up_dn_cnt2 (clk, reset,cout1, bout1, qout[7:4], cout, bout);endmodule



12/25

// the bod of modulo r binar counter with s nchronous reset and enable control.module modulo_r_counter(clk, enable, reset, qout, cout); parameter N = 4; parameter R= 10; // BCD counter

npu c , ena e, rese ;output reg [N-1:0] qout;output cout; // carry output// the body of modulo r binary counter.assign cout = (qout == R - 1);always @(posedge clk)

if (reset) qout


13/25

In this lecture, we focus on the following three circuits:

PR (pseudo random)-sequence generator Ring counter o nson coun er

f Combinational Circuit

D

CK

Q D

CK

Q D

CK

Q D

CK

Q

Qn -1 Q n -2 Q1 Q0 D

n -1 z

Q' Q' Q' Q'

clk

01n-2n-1


The general paradigm of sequence generator


14/25

n f ( x) n f ( x) n f ( x)1, 2, 3, 4, 6,7, 15, 22, 60 1+ x+ x

n

1+ x2+ xn5, 11, 21, 29

1+ x+ x2+ x7+ xn2426 1+ x+ x2+ x6+ xn

1+ x+ x2+ x23+ xn302 22 n

1+ x+ x5+ x6+ xn4344, 50 1+ x+ x26+x 27+ xn

1+ x+ x3+ x4+ xn4520 21 n, , , ,

28, 31, 41, 521+ x3+ xn

1+ x4+ xn923, 47 1+ x5+ xn

333435

1+ x13+ xn

1+ x+ x14+ x15+ xn

1+ x2+ xn

484951, 53

1+ x9+ xn

1+ x+ x15+ x16+ xn

1+ x+ x27+ x28+ xn

181+ x2+ x3+ x4+ xn

1213

1+ x+ x4+ x6+ xn

1+ x+ x3+ 4+ xn

81+ x7+ xn 36

373839

1+ x11+ xn

1+ x2+ x10+ x12+ xn

1+ x+ x5+ x6+ xn

1+ x4+ xn

545556,5957

1+ x24+ xn

1+ x+ x21+ x22+ xn

1+ x7+ xn

1+ x+ x36+ x37+ xn

nn

i 2

14, 16 1+ x3+ x4+ x5+ xn

1+ x+ x2+ x5+ xn19, 2740 1+ x2+ x19+ x21+ xn

42 1+ x+ x22+ x23+ xn58 1+ x19+ xn


ni

i ===

K210

0


15/25

CK Q'

CK Q'

CK Q'

CK Q' 01n-2 a n -2a n -1a n a 1 a 0n-1

(a) Standard format

D

CK

Q D

CK

Q D

CK

Q D

CK

Q

(b) Modular format

Q' Q' Q' Q' n-1 n-2 1 0a 2a 1a 0 a n -1 a n

clk



16/25

-An example of 4-bit pr-sequence generator:

primitive polynomial: 1 + x + x4

qout [3] qout [2] qout [1] qout [0]

d [3] D Q D Q D Q D Q

d [2] d [1] d [0]

clk

Q' clear

start

Q' clear

Q' clear

Q' preset

Using start to set the initial to 1000, the circuit will start from state4b1000 after reset signal is applied.



17/25

-// an N-bit pr_sequence generator module --- in standard formmo u e pr_sequence_genera e c , qou ;

parameter N = 4; // define the default size parameter [N:0] tap = 5'b10011;input clk; = 4b0100 for simulation only. Without

output reg [N-1:0] qout = 4b0100;wire d;

e n a va ue, s mu a ors cannocalculate qout and hence we could notobserve the qout values.

-assign d = ^(tap[N-1:0] & qout[N-1:0]);always @(posedge clk)

qout


18/25

-// an N-bit pr_sequence generator module --- in standard formmodule pr_sequence_generate (clk, start, qout); parameter N = 4; e ine t e e au t size

parameter [N:0] tap = 5'b10011;input clk, start;out ut re N-1:0 outwire d;// pseudo-random sequence generator body

assign d = ^(tap[N-1:0] & qout[N-1:0]);a ways pose ge c or pose ge s ar

if (start) qout


19/25

qout [3]qout [2]qout [1]qout [0]

D

CK

Q

Q' clear

D

CK

Q

Q' preset

D

CK

Q

Q' clear

D

CK

Q

Q' clear

// a ring counter with initial value

clk start

_ , , parameter N = 4;input clk, start;output reg [0:N-1] qout;

// the body of ring counter always @(posedge clk or posedge start)if (start) qout


20/25

qout [3]qout [2]qout [1]qout [0]

D

CK

Q

Q' clear

D

CK

Q

Q' clear

D

CK

Q

Q' clear

D

CK

Q

Q' clear

// Johnson counter with initial value

clk start

_ , , parameter N = 4; // define the default sizeinput clk, start;output reg [0:N-1] qout;

// the body of Johnson counter always @(posedge clk or posedge start)if (start) qout


21/25

A timing generator is a device that generates timingsrequ re or spec c app cat on.Multiphase clock signals:

Binary counter with decoder

Di ital monostable circuits:Retriggerable Nonretriggerable



22/25

clk

T 0

T

T 2

3

T 4

5

T 6


T 7


23/25

T 0 T 1 T 2 T 3 T 4 T 5 T 6 T 7

a Rin counter a roach

CK D

clk 0 1 2 3 4 5 6 7

// a ring counter with initial value serve as a timing generator _ _ _ parameter n = 4; // define the counter sizeinput clk, reset;output reg [0:n-1] qout;

e o y o r ng coun er always @(posedge clk or posedge reset)if (reset) qout


24/25

Binary counter with decoder approach

T 7 T 6 T 5 T 4 T 3 T 2 T 1 T 0

7 6 5 4 3 2 1 0

3-to-8 decoder

A2 A1 A0

CP CK Q2 Q1 Q0Binary counter

SynplifyPro with n = 4 and m =2.(Program is listed on the next page.)

decode+

R

[3:0]EQ[3:0][1:0] D[1:0]

[1:0][1:0] [1:0]Q[1:0][1:0] D[1:0] qout[3:0][3:0]

enable

clk


qout[3:0]cn_ou _ :

bcnt_out[1:0]reset


25/25

// a binary counter with decoder serve as a timing generator mo u e nary_coun er_ m ng_genera or c , rese , ena e, qou ;

parameter N = 8; // define the number of phases parameter M = 3; // define the bit number of binary counter input clk, reset, enable;output reg [N-1:0] qout;reg [M-1:0] bcnt_out;

// the body of binary counter if (reset) bcnt_out

Date post:	02-Apr-2018
Category:	Documents
Upload:	enzuek
View:	222 times
Download:	0 times

13.ECE 301 - Sequential Logic Modules II

Documents