148 IEEE TRANSACTIONS ON ADVANCED PACKAGING...

148 IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 30, NO. 1, FEBRUARY 2007

Flip-Chip-Assembled Air-Suspended InductorsPatrick J. Bell, Student Member, IEEE, Nils D. Hoivik, Member, IEEE, R. A. Saravanan,

Negar Ehsan, Student Member, IEEE, Victor M. Bright, Member, IEEE, and Zoya Popović, Fellow, IEEE

Abstract—This paper discusses high-performance planar sus-pended inductors for hybrid integration with microwave circuits.The inductors are fabricated using a silicon surface microma-chining foundry process and assembled using flip-chip bonding.The silicon substrate is removed, leaving a metal inductor sus-pended 60 m above the microwave substrate, thus reducing theparasitic capacitance and loss. Various rectangular, octagonal, andcircular inductor geometries with one to five windings are designedwith inductance values between 0.65 and 16 nH to demonstrate theflexibility of this technique. Measured self-resonant frequenciesare between 5 and 34.8 GHz, with quality factors from 45 to100. Equivalent circuits extracted from measurement for eachinductor type show good agreement with measured impedanceand full-wave simulations over frequency. The dc current handlinglimit is 200 mA.

Index Terms—Bias-tee, hybrid circuit, micromachined, qualityfactor, radio frequency (RF) choke, self-resonant frequency.

I. INTRODUCTION

CURRENT technology limitations in quality factor, cur-rent handling, and inductance often prohibit the use oflumped inductors in microwave hybrid-circuit applicationsat frequencies above C-band. However, monolithic inductorsare commonly used in applications up to K-band. The goalof this paper is to bridge the gap between surface-mount andmonolithic inductor performance. The inductors presented hereare micromachined on an inexpensive host substrate usinglithographic techniques and then transferred to a high-qualitymicrowave substrate via a low-temperature flip-chip assemblyprocess. The result is a lumped inductor hybrid circuit, Fig. 1,with performance characteristics comparable to those of mono-lithic inductors.

Substrate effects are the dominant limitation of planar induc-tors on both high-resistivity substrates like GaAs and low-resis-tivity CMOS-grade silicon. Resistive losses degrade the qualityfactor. High substrate permittivity increases the parasitic capac-itance, which reduces the self-resonant frequency. These issueshave been addressed in the past by fabricating the inductor on

Manuscript received December 19, 2005; revised April 13, 2006. This workwas supported in part by the Defense Advanced Research Projects Agency(DARPA) Intelligent RF Front End (IRFFE) under Contract N00014-02-1-0501with Dr. E. Martinez and Dr. D. Healy, and in part by a National ScienceFoundation (NSF) under ITR collaborative Grant ECS-0218744.

P. J. Bell, N. Ehsan, V. M. Bright, and Z. Popović are with the University ofColorado at Boulder, Boulder, CO 80309 USA (e-mail: [email protected]; [email protected]; [email protected]).

N. D. Hoivik was with the University of Colorado at Boulder. He is nowwith the IBM T. J. Watson Research Center, Yorktown Heights, NY 10598 USA(e-mail: [email protected]).

R. A. Saravanan was with the University of Colorado at Boulder. He is nowwith the United States Air Force Academy, USAFA, CO 80840 USA.

Digital Object Identifier 10.1109/TADVP.2006.890227

Fig. 1. Sketch of a micromachined inductor after completion of the release andflip-chip assembly in a CPW 50- test line. The inductor is suspended 60 �mabove the microwave substrate on gold posts (100� 100 �m).

low-K dielectrics, such as polyimide [1] or benzocyclobutene(BCB) [2]. With these methods, resonant frequencies between12 and 14 GHz for inductances around 2 nH and quality factorsbetween 30 and 50 have been demonstrated [1]. Another op-tion is to bulk etch the substrate surrounding the inductor, sus-pending the inductor structure in air. First demonstrated on sil-icon in [3], substrate removal increased the resonant frequencyfrom 800 MHz to 3 GHz. Similarly on bulk-etched GaAs [4],substrate removal increased the resonant frequency of a 5-nHinductor from 10 to 17 GHz with an increase in quality factorfrom 11.5 to 18.9. A third method utilizes microelectromechan-ical system (MEMS) fabrication techniques to create air-sus-pended inductors without bulk substrate etching. Stacked planarmicrostructures may be built using either photoresist [5], [6] orpolyimide [7] as sacrificial layers. The surface micromachiningapproach in [5] demonstrates a 2.7-nH inductor with a self-res-onant frequency of 15 GHz and a -factor of 40.

In this paper, a tethered assembly mechanism is integratedwith a micromachined inductor such that no surface or bulketching is required on the microwave substrate. The inductancevalues range from 0.65–16 nH, with self-resonant frequenciesfrom 5–35 GHz and quality factors from 45–100. Standard in-ductor shapes, shown in Fig. 2, are used to demonstrate the flex-ibility of this assembly technique. The inductor labels in Fig. 2are used throughout this paper in reference to each particular in-ductor type.

In [8], the inductor type shown in Fig. 2(a) was demonstratedas a high-impedance radio frequency (RF) choke in a miniatur-ized bias-tee. The impedance of these inductors remains highwell beyond the self-resonant frequency, extending the band-width of a bias-tee network. Below the resonant frequency, theinductors can be used as high-quality lumped elements. An ex-ample is a miniaturized Wilkinson divider at 1.72 GHz [9] witha footprint of 0.96 cm .

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BELL et al.: FLIP-CHIP-ASSEMBLED AIR-SUSPENDED INDUCTORS 149

Fig. 2. Photographs of the flip-chip assembled suspended inductors. This assembly technique was tested for several geometries, including (a) a 5.5-turn rectangularand (b) an open-center 3.5-turn rectangular, (c) a five-turn tapered rectangular, (d), (e), and (f) four- two- and one-turn octagonal, and (g) and (h) four- and two-turncircular inductors. The labels in this figure will be used throughout this paper in reference to a specific geometry. The coplanar waveguide lines have 90-�m signalline and 30-�m slot widths for 50 on an alumina substrate (� = 9:8). (a) Rect5, (b) Rect3, (c) Taper5, (d) Oct4, (e) Oct2, (f) Oct1, (g) Circ4, and (h) Circ2.

II. INDUCTOR DESIGN

Design of flip-chip micromachined inductors begins with se-lection of silicon surface micromachining process layers, whichmust provide adequate structural support and low conductorloss. After selection of the metalization layers, the geometry ofthe planar coil is chosen for desired values of inductance and res-onant frequency. Equations based on geometric considerationsaccurately predict the inductance; however, full-wave simula-tions are required to determine the self-resonant frequency.

A. Mechanical and Processing Considerations

Early experimentation by the authors with 2- m-thick solidgold suspended inductors was unsuccessful [10]. The highlymalleable gold structure does not provide adequate structuralsupport since the diameter-to-thickness aspect ratio is large foruseful inductor values (about 100:1). This problem is addressedusing a multilayer structure of polysilicon and trapped silicondioxide to provide additional stiffness. The worst case saggingat the extreme edges is less than a single turn thickness (2 m)due to internal stress, simulated using finite-element analysis(Coventorware). The advantage of a multilayer structure comesat the cost of a coefficient of thermal expansion (CTE) mis-match. A detailed thermal analysis of released gold/polysiliconstructures is given in [11]. Tests from 25 C to 120 C show littlevariation in the electrical properties of the inductors presentedin this paper.

A polysilicon surface micromachining multiuser MEMSprocess (PolyMUMPs) foundry service is commercially avail-able through the MEMSCAP Corporation. This process hasthree available polysilicon deposition layers with intermediatephosphosilicate glass (PSG) layers and a thin gold metal layer[12]. The inductors presented here use 2.0 m of polysilicon(POLY1), 0.75 m of PSG oxide (OXIDE2), 1.5 m of polysil-icon (POLY2), and 0.5 m of gold (METAL). PolyMUMPs isintended to be a self-contained MEMS process; however, thelow resistivity of the silicon wafer is unsuitable for microwavecircuits and components, and the gold metalization is thinnerthan the skin depth. These issues are addressed by masklesselectroplating and removal of the silicon substrate, performedin-house. 2 m of additional gold (ELECTRO) is plated to theinductor, resulting in a total gold thickness of 2.5 m. Substrateremoval is accomplished by designing the entire inductorstructure above the first PSG oxide layer (OXIDE1). A timedhydrofluoric acid (49% HF) prerelease step then dissolves thesacrificial PSG oxide and suspends the inductor in air. The crosssection of the edge of one inductor turn is shown in Fig. 3.

Fig. 3. Cross section of the edge of one turn in the inductor coil showing thePolyMUMPs micromachining layers [12], which are inverted after flip-chipbonding. The vertical dimension is to scale. The turn width w is much largerthan the total thickness (24–40 �m).

B. Electrical Considerations

The inductance of a planar coil is dependent on the totalnumber of turns , turn width , turn spacing , outer diameter

, inner diameter , and the geometry of the spiral. Initial es-timates of the inductance approximated the sides of the inductorspiral as current sheets, as in [13]. Tapered geometries have beenfound in [14] to increase the quality factor of the inductor, anda nonoptimized tapered design is included [Fig. 2(c)].

The series resistance of the inductor is estimated from, where is the total length

of the inductor, is the turn width (24 or 40 m), and isthe sheet resistance of the gold layer. Since only an estimationof the series resistance is required, proximity effects are notconsidered. The metal thickness is finite, so skin depth isscaled accordingly [15]. Also, the conductivity of the polysil-icon is much lower than that of the gold layer (5.00 10 S/m forPOLY1, 3.33 10 S/m for POLY2, and 3.33 10 S/m for the goldMETAL layer). The flip-chip assembly process provides a directgold-to-gold connection; therefore, the substantially larger par-allel sheet resistances of the polysilicon layers above the goldlayer have a negligible contribution to the overall dc resistanceof the inductor. Electroplating the gold layer to a total thicknessof 2.5 m insures at least one skin depth down to 1 GHz.

A summary of the series inductance ( calc) and series re-sistance ( calc) estimates, with resonant frequencies fromfull-wave simulations (Agilent Momentum) is given with mea-sured results in Table I in Section III.

C. Hybrid Assembly Considerations

One of the primary goals of this paper is to bring the advan-tages of compact, planar inductors to hybrid circuits. Hybrid in-tegration in this case involves transfer of the inductor from thesilicon wafer to the circuit, and elimination of the lossy [12]



TABLE IEXTRACTED EQUIVALENT CIRCUIT PARAMETERS AND MEASURED PERFORMANCE

Fig. 4. (a) Layout of the assembly tethers surrounding a bond pad and (b) anenlarged top and cross-sectional view of a single tether. The notch is located ata predetermined breaking point. Locking structures in the bond pad made usingthe polysilicon POLY0 layer guide and hold the inductor in alignment duringthe bonding process.

silicon wafer. The transfer of the inductor onto the circuit sub-strate requires two steps: thermo-compression flip-chip bondingand final release from the silicon wafer.

In earlier inductor assemblies, the thermo-compressionbonding to gold bumps on an alumina (Al O ) substrate oc-curred first, followed by a timed 49% hydrofluoric acid (HF)etch of the sacrificial PSG layer. While HF does not attackalumina, not all microwave substrates and components are HFresistant. Providing greater versatility requires a prerelease as-sembly mechanism to be integrated with the inductor, allowingthe HF release to occur before the thermo-compression bond tothe microwave substrate.

To facilitate a “prerelease” of the inductor before bonding, theinductor structure is anchored through the sacrificial PSG to thesilicon wafer by tethers around the bond pads [16], illustratedin Fig. 4. With these polysilicon tether structures, the timed HFrelease occurs first, leaving the inductor suspended in air whileanchored through the tethers to the silicon wafer. The receivingmicrowave substrate has pedestals (gold bumps) that align withthe two bond pads on the inductor. The pressure applied to thepad during bonding causes the tethers to break at the designednotches in the polysilicon, indicated in Fig. 4, which free theinductor from the host silicon. The final structure is a metalspiral suspended 60 m in air above the microwave substrate.

Fig. 5 shows a conceptual schematic of the complete transferprocess. In addition, a locking mechanism in the bond pad usingthe POLY0 layer of the PolyMUMPs process guides and holdsthe inductor in place during the bonding process. These lockingstructures are shown in Figs. 4 and 5(c).

This hybrid assembly has been demonstrated on both aluminaand Rogers TMM6 substrates [8], [9], shown in Fig. 6, and iscompatible with any flat substrate. No sacrificial material is re-quired on the circuit substrate, and this method can integrateinductors with existing microwave circuitry.

III. MEASURED PERFORMANCE

Three copies of the eight inductor types were characterizedto verify basic repeatability. -parameters were measured ona 50-GHz Agilent 8510C network analyzer and a CascadeSummit 9000 probe station with 250- m-pitch air coplanar(ACP) ground-signal-ground (GSG) probes. A thru-reflect-line(TRL) calibration was performed with reference planes at theedge of the inductor, Fig. 7.

Depending on the intended application, different parametersare relevant. Inductors in matching circuits and filters operatebelow the resonant frequency, and so resonance and qualityfactor are critical parameters. RF chokes for bias lines require ahigh impedance, in which case the inductor can operate beyondthe resonance frequency. This section summarizes measuredresults in terms of phase, quality factor, and input impedance.

A. Test Circuit

All inductors are measured in a finite-ground 50- coplanarwaveguide (CPW) test circuit, shown in Fig. 7. A slot widthof 30 m on a 635- m-thick alumina substrate prevents higherorder modes from developing in the line, verified using both full-wave simulations and experiments. Using a TRL calibration, themaximum attenuation in the line is measured at dB/mmat 45 GHz. The test circuits are spaced on the alumina wafersuch that coupling between the structures is below dB.

Each geometry is simulated using full-wave electromagneticanalysis (Agilent Momentum). Simulated resonant frequenciesare included in Table I. A few simplifications greatly decreasethe simulation time: 1) the alumina substrate is thick comparedto the slot width, therefore, the substrate is modeled as infinite;2) the finite ground planes extend far enough to cause little devi-ation in impedance from the case of the ideal CPW with infiniteground planes, therefore, the ground is modeled as infinite and



Fig. 5. Cross-sectional illustration of the prerelease and flip-chip transferprocess of the tethered inductor. (a) The sacrificial oxide layer of the host waferwith micromachined inductor features is etched, leaving the inductor structureanchored to the host substrate by the tethers. (b) The inductor–host substratecombination is then flipped and aligned with the gold bumps on the receivingsubstrate. (c) Thermo-compression bonding joins the inductor bond-pads tothe gold bumps and simultaneously breaks the tethers at designed points. Theinset in (c) shows an interlocking structure to hold the inductor in place duringthe bonding process. (d) After flip-chip transfer, the resulting structure is areleased device. This conceptual drawing is not to scale. (a) A micromachinedinductor on the silicon wafer before the pre-release etching of the sacrificialoxide. (b) A pre-released device flipped and aligned with the bond pads on thereceiving substrate. The inductor is anchored to the silicon wafer by the tetherssurrounding the bond pads. (c) Thermo-compression bonding breaks the tetherstructures to completely release the inductor. (d) A released inductor suspendedin air above the microwave substrate.

only the slot is meshed; 3) the backshort in the ground planehas little effect on the circuit; therefore, it is ignored. A sim-ulation of the exact finite-ground/finite-substrate structure wascompared to the simplified model and validates convergence ofthese assumptions from 1–50 GHz.

B. Equivalent Circuit Model

Using the measured -parameters, an equivalent circuitmodel [17], shown in Fig. 8, is fit to the experimental data usingthe optimization routines in Agilent ADS. A gradient methodis used to fit the model to the magnitude and phase of theimpedance of the experimental data from 1 GHz to the self-res-onant frequency. , and are the series inductance,

Fig. 6. Inductors from this work hybridly integrated with surface-mount ca-pacitors and resistor in a miniature bias tee on alumina [8] and a miniaturelow-loss Wilkinson power divider on Rogers TMM6 [9]. The scale and induc-tors are indicated. The 1.72-GHz 3-dB divider has a 0.96-cm footprint, withS = �20 dB, S = S = �26 dB, and insertion loss of 0.2 and 0.8 dBat ports 2 and 3, respectively. (a) Bias Tee. (b) Wilkinson Divider.

Fig. 7. All inductors are characterized on a finite-ground CPW test circuit, withdimensions 2a = 90 �m, 2b = 150 �m, and 2c = 1350 �m. The distance ofthe CPW launch from the probe pads to the reference plane is 500 �m, the open-circuit end-gap distance is 2b, and the width of the backshort is 300 �m. TheCPW dimensions, backshort, and launch remain constant for all tested inductortypes. The inner D and outer D diameters of the inductor, turn width w andspacing s between turns, and the diameter of the ground slot around the inductor(D ) vary with inductor type. The ground slot diameter is D + 200 �m forall inductor types.

Fig. 8. Pi-equivalent circuit model of the inductor, where L ; C and R arethe series inductance, capacitance, and resistance. The substrate effects are in-cluded in C and R . This model is accurate up to the resonant frequency.

capacitance, and resistance. The shunt capacitance andresistance are due to substrate losses. Typically, the shuntresistance for insulating substrates is assumed to be infinite [1],[4]; however, without this component, the equivalent modeldoes not converge to the measured -factor. For best accuracyin the model, cannot be assumed to be infinite. Table Ishows typical component values for all inductor types, where

is in the range of 10–50 k . The values labeled “model”in Table I are the extracted values from the experimental data.

calc is the predicted inductance calc is the estimatedresistance from Section II.B.

C. Self-Resonant Frequency

The self-resonant frequency is most visible in the phase of theinput impedance of the inductor with a short circuit termi-



Fig. 9. Measured (symbol) and modeled (solid line) phase of the eight induc-tors from Fig. 2. The self-resonant frequency occurs where the phase crosseszero. The legend shows the order of the self-resonance frequency from left toright. A summary of the measured resonant frequencies is included in Table I.

nation at port 2 of Fig. 8. The resonance occurs when the phasechanges abruptly from 90 to -90 .

Fig. 9 shows the phase of each of the eight inductor types.The solid lines represent the equivalent circuit models, with thesymbols at the measured data points showing the close agree-ment of the models. The measured resonant frequency is alsoincluded in Table I and compared with the resonance frequencyobtained with full-wave simulation.

D. Input Impedance

The magnitude of is critical to RF chokes in bias lines.Fig. 10 shows the magnitude of for the eight types of induc-tors. The maximum impedance for each of the inductors occursat the resonant frequency, which is where the impedance crossesthe real axis of the Smith chart. Beyond this resonance, althoughon the capacitive side of the Smith chart, the impedance remainshigh. For added clarity, the measured data is cut after the firstminimum of (around 20 ), beyond which the inductor al-ternates between series and parallel resonances and would bequite difficult to use in an RF choke design. In the case of theRect5 inductor, which is demonstrated in a miniaturized bias-teein [8], the impedance is above 100 from 1 to 15 GHz. Thishigh impedance range corresponds to the operating range of thebias-tee, where losses between the RF ports are minimized.

E. Quality Factor

Quality factor is calculated from the -parameters by, where is the input impedance with

a short circuit termination at port 2 of Fig. 8. Figs. 11 and 12show the measured -factor (symbols) and the -factor of theequivalent circuit model (solid line). The maximum -factor( meas) and the frequency at which this value occurs (meas) are included in Table I for each inductor type.

Fig. 10. Measured (symbol) and modeled (solid line) input impedances for alltypes of inductors. The maximum impedance occurs at the resonant frequency.The legend shows the order of the impedance peak from left to right. For clarity,only the impedances up to the first minimum are shown.

Fig. 11. Measured (symbol) and modeled (solid line) quality factors of the sixlower-resonant frequency inductors. Exact values of peak Q-factor and the fre-quency of maximum Q from the model (f ) are included in Table I.

The -parameter method of calculating quality factor isvery sensitive, most evident in Fig. 12 for high values of athigh frequencies. Similar behavior is noticed in [4] and [18]. Adifferent measurement and extraction method will be needed ashigher frequency inductors become more available. The modelsfor Circ2 and Oct1 are fit to the data at lower frequencies(1–8 GHz) and at the self-resonant frequency, resulting inconservative peak- values compared to the data.

The trends in Figs. 11 and 12 suggest three methods of qualityfactor improvement. First, the quality factor at frequencies up



Fig. 12. Measured (symbol) and modeled (solid line) quality factors for theCirc2 and Oct1 inductors. At high frequencies the S-parameter method of de-termining Q-factor is extremely sensitive and limited by the instrumentation.The models are a best-fit to the data.

to 5 GHz may be enhanced by thicker metalization. Second, re-ducing the potential for conductor and induced eddy current lossin the inner turns by eliminating them in the open core Rect3and Oct2 inductors improved the quality factor significantly, al-though these configurations do not achieve the maximum in-ductance for the area occupied by the inductor. Additionally, ta-pering the turn widths to balance the effects of conductor lossesin the longer outer turns and the eddy current losses for the innerturns in the presence of stronger magnetic fields dramaticallyenhances the quality factor, verifying the results of [14]. Essen-tially, these inductors exhibit the same traits as their monolithicplanar spiral counterparts.

IV. DISCUSSION

This paper presents design, assembly, modeling, and mea-surements of high- inductors with measured resonant frequen-cies through Ka-band. An important additional parameter is cur-rent handling, particularly for applications in bias lines. Heatingat high currents warps the inductor structure due to CTE mis-match in the stacked structure long before it reaches a cata-strophic meltdown. Warpage is considered the mode of failure,since the high heat will change the metal properties and theplastic deformation permanently changes the inductance. Sincethese tests are destructive, only the 5.5-turn rectangular inductorhas been tested. It has the highest series resistance of all theinductors in this work. Visual warpage occurred around 120 mA,with catastrophic meltdown around 300 mA for the three Rect5inductors tested. This indicates that the maximum current han-dling capacity is approximately 2 mA/ m of cross-sectionalarea, less than gold alone (silicon–gold alloys melt at a lowertemperature than pure gold). Inductors with larger cross-sec-tional areas (such as the octagonal type) support approximately

200 mA before the onset of warpage. A thicker metal layerwould also increase the current handling proportionally.

Susceptibility to shock and vibrations are also concerns withsuspended inductors. Using the four-turn octagonal inductoras an example, finite-element simulations show the first threemodes of mechanical resonance occurring between 9.2 and10.8 kHz. Similar mechanical resonant frequencies for sus-pended inductors are reported in [18]. The multilayer structurein this work increases the stiffness of the inductor when com-pared to all-metal inductors. Simulations indicate a maximumdeformation at the outer edges of the inductor of 0.04 m ( 1%of the inductor coil thickness) for acceleration of 100 G.

In summary, the inductors demonstrated in this work haveinductance values ranging from 0.65–16 nH, with self-resonantfrequencies from 5–35 GHz, and quality factors ranging from45–100. The high impedance of the inductors even beyond theresonant frequency makes these inductors particularly usefulas high-impedance RF chokes in bias-tees. Below resonance,the low-loss and high- properties of these flip-chip assembledinductors make them suitable for lumped-element circuits andimpedance matching in the 1–5 GHz frequency range, wheredistributed matching circuits are quite large and surface-mountinductors are not readily available. This flip-chip assemblymethod can be used to create lumped-element inductors onhybrid circuits with frequency and quality-factor characteristicscomparable to their monolithic counterparts.

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Patrick J. Bell (S’99) received the B.S. degree inelectrical engineering from the University of Virginia(UVA), Charlottesville, in 2001, and the M.S. andPh.D. degrees from the University of Colorado atBoulder in 2003 and 2006, respectively.

He was a Student Intern at GaAsTEK, Roanoke,VA, from 1997 to 1999, a Student Researcher in theFar Infrared Receiver Laboratory, UVA, in 2000, anda Graduate Intern at the Massachusetts Institute ofTechnology (MIT) Lincoln Laboratory, Cambridge,in 2003. He was the Sandia National Laboratories

Excellence in Engineering Fellow at the University of Colorado from 2004 to2006. His research interests include high-efficiency microwave power ampli-fiers, RF-MEMS, and low-loss reconfigurable microwave networks.

Nils D. Hoivik (S’99–M’04) received the B.S. de-gree in mechanical engineering from the College ofEngineering, Oslo, Norway, in 1997, with a focus onmechatronics and control systems, and the Ph.D. de-gree from the University of Colorado at Boulder in2002 specializing in flip-chip-assembled RF-MEMSdevices.

He is currently a Researcher at the IBM T. J.Watson Research Center, Yorktown Heights, NY,working on RF-MEMS devices fabricated usinginterconnect technology. His research interests

include the design, fabrication, packaging, modeling, and testing of MEMSdevices for RF applications such as variable high-Q capacitors, integrated RFswitches, resonators, and thin-film dielectric materials.

R. A. Saravanan, photograph and biography not available at the time ofpublication.

Negar Ehsan (S’05) was born in Tehran, Iran, in Jan-uary 1982. She received the B.S. and M.S. degrees inelectrical and computer engineering and a minor inapplied mathematics from the University of Coloradoat Boulder in 2006. She is currently working towardthe Ph.D. degree in electrical engineering at the Uni-versity of Colorado at Boulder.

Her research interests include thick frequency-se-lective surfaces and impedance tuning networks.

Ms. Eshan was the recipient of the 2006 Distin-guished Senior Award from the Department of Elec-

trical Engineering, University of Colorado.

Victor M. Bright (M’92) received the B.S. degreein electrical engineering from the University ofColorado at Denver in 1986, and the M.S. and Ph.D.degrees from the Georgia Institute of Technology,Atlanta, in 1989 and 1992, respectively.

He is the Associate Dean for Research and aProfessor of Mechanical Engineering, College ofEngineering and Applied Science, University ofColorado at Boulder. Prior to joining the Universityof Colorado, he was a Professor in the Departmentof Electrical and Computer Engineering, Air Force

Institute of Technology, Wright-Patterson Air Force Base, OH (June 1992–De-cember 1997). During 2004, he was a Visiting Professor at the Swiss FederalInstitute of Technology (ETH-Zurich), Switzerland. His research activitiesinclude micro- and nano-electromechanical systems, silicon micromachining,microsensors/microactuators, optoelectronics, optical, magnetic and RFmicrosystems, atomic-layer deposited materials, ceramic MEMS, MEMS reli-ability, and MEMS packaging. His teaching activities include manufacturingof MEMS, sensor/actuator design, and microsystem integration and packaging.He is an author of over 70 archived journal articles in the fields of MEMS,NEMS, and microsystems.

Dr. Bright has served on the Executive Committee of the ASME MEMS Di-vision, on the Technical Program Committee of the IEEE MEMS 2000 through2006 conferences, and as the General Co-Chair for the IEEE MEMS 2005. Healso served on the Technical Program Committee for the Transducers’03 andIEEE/LEOS Optical MEMS from 2003 to 2005. He has taught a Short Courseon MEMS Packaging at Transducers’03 and Transducers’05.

Zoya Popović (S’86–M’90–SM’99–F’02) receivedthe Dipl.Ing. degree from the University of Bel-grade, Serbia, Yugoslavia, in 1985, and the Ph.D.degree from the California Institute of Technology,Pasadena, in 1990.

Since 1990, she has been with the Universityof Colorado at Boulder, where she is currently theHudson Moore, Jr., Chaired Professor of Electricaland Computer Engineering. She has developed fiveundergraduate and graduate electromagnetics andmicrowave laboratory courses. Her research interests

include microwave and millimeter-wave quasi-optical circuits, high-efficiencycircuits, low-phase noise circuits, smart and multibeam antenna arrays, intel-ligent RF front ends, RF optical techniques, batteryless sensor powering andmillimeter-wave imaging.

Dr. Popovic is the recipient of the 1993 and 2005 Microwave Prizes pre-sented by the IEEE Microwave Theory and Techniques Society (IEEE MTT-S)for the best journal papers. She also received the 1996 URSI Issac Koga GoldMedal, the 1993 NSF Presidential Faculty Fellow Award, the 2000 HumboldtResearch Award from the German Alexander von Humboldt Stiftung, andthe 2001 Hewlett-Packard(HP)/American Society for Engineering Education(ASEE) Terman Medal for combined teaching and research excellence.


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148 IEEE TRANSACTIONS ON ADVANCED PACKAGING...

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