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FUTURE OF DIGITAL
CH13
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From China: 2.5petaflops/s
World Fastest supercomputer World Upcoming fastest supercomputer
Blue Gene /Q-Mira from IBM 10petaflops/s
IBM Exascale Super computer
Project 2020
THE RACE FOR SUPERCOMPUTING POWER
INTEL CMOS Integrated Silicon
Nanophotonics Computer Chip
Project 2010
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THE NEXT BIGGEST SUPERCOMPUTER POTENTIAL BREAKTHROUGH
Quantum Computer
In theory, quantum computers would be able to process infinite computations across
multiple "dimensions".
The quantum computer took a step closer to reality in January 2011 when Oxford
University physicists unveiled a successful test of a quantum chip.
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ITRS Roadmap
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FREQUENCY
Lead Microprocessors frequency used to double every 2 years
P6
Pentium ® proc486 386
286 8086 8085
8080
8008
4004 0.1
1
10
100
1000
10000
1970 1980 1990 2000 2010
Year
F r e q u e n c y
( M h z )
Doubles every
2 years
P4
Courtesy, Intel
Core i7 (3.3GHz)
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CHIP POWER OF INTEL PROCESSORS
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POWER DISSIPATION
Lead Microprocessors power continues to increase
P6 Pentium ® proc
486
386
286 8086
8085 8080
8008 4004
0.1
1
10
100
1971 1974 1978 1985 1992 2000
Year
P o w e r ( W a t t s )
Courtesy, Intel
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POWER: MAJOR PROBLEM
5KW18KW
1.5KW
500W
4004 8008
8080 8085
8086 286
386 486
Pentium® proc
0.1
1
10
100
1000
10000
100000
1971 1974 1978 1985 1992 2000 2004 2008
Year
P o w e r ( W a t t s ) Core i7
(130W)
Power delivery and dissipation will be prohibitive
To maintain Moore’s Law
Courtesy, Intel
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Active and Passive Components of
CMOS Power
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DELAY VS. VT/VDD
Need to minimize VT with respect to VDD
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TEM OF THIN GATE OXIDE
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TUNNELING THROUGH SiO2
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Dealing with Short Channel Effects in bulk MOSFET
1.Increasing body doping concentration2.Using halo implant
High doping density results in:
• Lower carrier mobility;• high tunneling effect which increases off-state currents;
• Larger depletion capacitors leading to high sub-threshold swing which
increases off-state currents;
• Larger parasitic capacitance, Cgd, Cds.
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Limit of Bulk CMOS Scaling
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BULK CMOS SCALING LIMIT
To reduce short channel effects, we need to reduce Xdep (channel depletion
layer thickness), X j ( Junction depletion width), tox (oxide layer thickness
under gate). Defining a figure of merit
For bulk MOSFET gate length
Lbulk >
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AFTER SCALING PROCESS REACHES LIMITS ...
• New ideas, technologies, and concepts will be required for continued
performance improvements.
• Examples of new ideas, technologies, and concepts:
•Silicon on insulator (S0I) technology
•Depleted MOSFETS and FinFETS
•SiGe and SiC technology
•3D integration
•Optical interconnects
•Nanowire transistors
2010 2015 2020
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SOI CMOS
anneal
SIMOX PROCESS
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Dealing with Short Channel Effects in
FULLY DEPLETED SILICON ON INSULATOR (FD-SOI)
Use ultra-thin film (tsi is small) as the conducting body, depletion layer is
confined in the film.( Xdep
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