150MHz AD Converter

7/29/2019 150MHz AD Converter

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UNIVERSITY OF CALIFORNIA

Los Angeles

An 8-Bit 150-MHz CMOS A/D Converter

A dissertation submitted in partial satisfaction of the

requirements for the degree Doctor of Philosophy

in Electrical Engineering

by

Yun-Ti Wang

1999


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Dedication

To my parents and Jing for their love and support.


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Table of Contents

Chapter 1 Introduction .............................................................................. 1

1.1 Motivation ............................................................................................... 1

1.2 Thesis Organization ................................................................................ 3

Chapter 2 ADC Applications and Architectures ..................................... 4

2.1 Applications ............................................................................................ 4

2.1.1 Digital Oscilloscopes ..................................................................... 4

2.1.2 Gigabit Ethernet ............................................................................. 5

2.1.3 RGB-to-LCD Display Conversion ................................................. 6

2.2 Architecture Review ............................................................................... 7

2.2.1 Flash Architecture .......................................................................... 7

2.2.2 Two-Step Architecture ................................................................. 10

2.2.3 Pipelined Architecture ................................................................. 12

2.2.4 Interleaved Architecture ............................................................... 14

2.2.5 Interpolating Architecture ............................................................ 16

Chapter 3 Proposed ADC Architecture ................................................. 18

3.1 Sliding Interpolation ............................................................................. 19

3.2 Embedded Pipelining ............................................................................ 27

3.3 Addition of Interleaving ........................................................................ 29


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3.4 Clock Edge Reassignment .................................................................... 32

3.5 Reinterpolation ...................................................................................... 36

3.6 Effect of Nonlinearity in Sliding Interpolation ..................................... 40

Chapter 4 Circuit Design and Layout Considerations ......................... 42

4.1 Introduction ........................................................................................... 42

4.2 Front-End Sample-and-Hold Circuit ..................................................... 42

4.3 Differential Amplifiers .......................................................................... 46

4.4 Comparator ........................................................................................... 49

4.5 Clock Edge Reassignment .................................................................... 53

4.6 Control and Decode Circuit .................................................................. 55

4.7 ROM and Output Stage ......................................................................... 57

4.8 Clock Generator .................................................................................... 58

4.9 One Slice of First-Stage Signal Path ..................................................... 60

4.10 Floor Plan And Layout Considerations ................................................. 63

Chapter 5 Experimental Results ............................................................. 71

5.1 Introduction ........................................................................................... 71

5.2 Design of Chip-on-Board Assembly ..................................................... 72

5.3 Test Setup .............................................................................................. 78

5.4 Experimental Results ............................................................................ 79


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Chapter 6 Conclusion and Future Work ............................................... 84

Bibliography ................................................................................................. 87


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List of Figures

Figure 2.1 Digital oscilloscope. ...................................................................... 5

Figure 2.2 ADC application in Gigabit Ethernet. ........................................... 6

Figure 2.3 ADC application in RGB-to-LCD display conversion. ................. 7

Figure 2.4 Block diagram of an N-bit flash ADC. .......................................... 8

Figure 2.5 Transfer curves of an N-bit flash ADC. ......................................... 9

Figure 2.6 Mapping scheme of a 4-bit two-step ADC. ................................. 10

Figure 2.7 Block diagram of an N-bit, two-step ADC. ................................. 11

Figure 2.8 Block diagram of a pipelined ADC. ............................................ 13

Figure 2.9 Block diagram of an interleaved ADC. ....................................... 15

Figure 2.10 A 2x active interpolating ADC. ................................................. 16

Figure 3.1 Traditional active 2x interpolation architecture. ......................... 20

Figure 3.2 Sliding interpolation architecture. ............................................... 21

Figure 3.3 Flow diagram of multi-stage sliding interpolation. ..................... 22

Figure 3.4 Sliding interpolation architecture. ............................................... 23

Figure 3.5 Block diagram of multi-stage sliding interpolation. .................... 24

Figure 3.6 Detailed block diagram of multi-stage sliding interpolation. ...... 25

Figure 3.7 Sliding mechanism ...................................................................... 26

Figure 3.8 Pipelined sliding interpolation ADC architecture. ...................... 28

Figure 3.9 Addition of interleaving scheme. ................................................ 30

Figure 3.10 Complete ADC architecure with replica SHA. ......................... 31
http://chapter2.pdf/http://chapter2.pdf/


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Figure 3.11 (a) Timing mismatch in interleaved architecture, (b) generation

ofCK1 and CK2 by a frequency divider. ................................. 33

Figure 3.12 Basic concept of the clock edge reassignment. ......................... 35

Figure 3.13 Detailed operation of clock edge reassignment. ........................ 36

Figure 3.14 Reinterpolation (a) implementation, (b) error plot. ................... 38

Figure 3.15 INL reduction by reinterpolation observed in Monte Carlo

simulations. ............................................................................... 39

Figure 3.16 Nonlinearity-induced error in 2x interpolation. ......................... 41

Figure 4.1 Dual-channel interleaved SHA. ................................................... 43

Figure 4.2 Timing diagram for SHA. ............................................................ 44

Figure 4.3 A triple-channel interleaved SHA with a replica. ....................... 45

Figure 4.4 Preamplifier. ................................................................................ 47

Figure 4.5 Reinterpolating and interpolating amplifiers. .............................. 48

Figure 4.6 Comparator used in the first stage (CMP_A). ............................. 50

Figure 4.7 Comparator used in stages 2 to 5 (CMP_B). ............................... 52

Figure 4.8 Clock edge reassignment circuit for a dual-channel system. ...... 53

Figure 4.9 Operational diagram of a dual-channel CERA system. ............... 54

Figure 4.10 Block diagram of NAND_FF with comparator. ........................ 55

Figure 4.11 Details of NAND_FF ................................................................ 56

Figure 4.12 ROM and output stage. .............................................................. 57

Figure 4.13 Clock generator. ........................................................................ 59


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Figure 4.14 High-speed differential D latch. ................................................ 60

Figure 4.15 Realization of a slice of the signal path in the first stage. ......... 61

Figure 4.16 Simulated output of the 8-bit ADC. .......................................... 62

Figure 4.17 Layout floor plan. ...................................................................... 64

Figure 4.18 Detailed circuit arrangement in the first stage. .......................... 66

Figure 4.19 Sliding/multiplexing mechanism of the lower bank. ................. 67

Figure 4.20 Sliding/multiplexing mechanism of the upper bank. ................. 68

Figure 4.21 Die photo. .................................................................................. 69

Figure 5.1 Chip-on-board assembly. ............................................................. 72

Figure 5.2 Zoom-in of the central cavity area. .............................................. 73

Figure 5.3 Actual size of chip-on-board assembly. ...................................... 74

Figure 5.4 Mother board and daughter board. .............................................. 75

Figure 5.5 A combination of different kinds of boards. ............................... 77

Figure 5.6 Test setup. .................................................................................... 78

Figure 5.7 DNL and INL at fin = 1.8 MHz and fsample = 150 MHz. ............. 80

Figure 5.8 FFT at fin = 1.76 MHz. ................................................................ 81

Figure 5.9 SNDR and SFDR at fsample = 150 MHz. ..................................... 82


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List of Tables

Table 1: Measurement Summary .................................................................. 83


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ACKNOWLEDGMENTS

First, I would like to express my sincere thankfulness to Professor Behzad

Razavi for his guidance and support throughout my Ph.D study. He is my role

model. I am also grateful to Professors William J. Kaiser, Frank M. Chang, and

James S. Gibson for serving on my Ph.D. committee.

Next, I would like to thank Jafar Savoj and Tai-Cheng Lee for the helpful

technical discussions with them and also Alireza Razzaghi for his proofreading of

my dissertation.

I am very grateful and feel very lucky that my wonderful parents are open-

minded, patient, and very supportive throughout this long graduate study process. I

am also thankful for the support from other members in our family.

Last but not the least, I would like to express my deepest gratitude to Guo Jing,

my dear better half, who has generously and consistently provided me the crucial

emotional support and love that I needed the most to complete this challenging

process. With the mutual understanding, caring, encouragement, and support

between us, I believe we can make more contributions to this world in the future.


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ABSTRACT OF THE DISSERTATION

An 8-Bit 150-MHz CMOS A/D Converter

by

Yun-Ti Wang

Doctor of Philosophy in Electrical Engineering

University of California, Los Angeles, 1999Professor Behzad Razavi, Chair

High-speed analog-to-digital converters (ADCs) with resolutions of 8 bits

find wide application in instrumentation and communication systems. For example,

portable digital oscilloscopes use 8-bit ADCs with sampling rates above one

hundred megahertz. Also, the Gigabit Ethernet standard with CAT-5 copper cable

requires four 125-MHz ADCs having a resolution of 7 to 8 bits to perform the front-

end analog-to-digital data conversion.

This dissertation presents an 8-bit, 5-stage interleaved and pipelined ADC

that performs analog processing only by means of open-loop circuits such as

differential pairs and source followers, thereby achieving a high conversion rate.

The concept of sliding interpolation is proposed to obviate the need for a large

number of comparators or interstage digital-to-analog converters and residue


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amplifiers. The pipelining incorporates distributed sampling between the stages so

as to relax the linearity-speed trade-offs in the sample-and-hold functions. This

work also introduces a clock edge reassignment technique that suppresses timing

mismatch issues in interleaved systems. Moreover, in order to reduce the integral

nonlinearity error (INL) with negligible speed or power penalty, a reinterpolation

method is proposed.

Fabricated in a 0.6-m CMOS technology, the ADC achieves a DNL of 0.62

LSB, INL of 1.24 LSB, SFDR of 50 dB, and SNDR of 43.7 dB at 150 MHz

sampling rate with low input frequencies. When input frequency is at 70 MHz,

SNDR of 40 dB is attained. The converter draws 395 mW from a 3.3-V supply and

occupies an area of 1.2 x 1.5 mm2.


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Chapter 1

Introduction

1.1 Motivation

Analog-to-digital (A/D) conversion and digital-to-analog (D/A) conversion are

critical interfaces in mixed-signal processing systems. With the continuous advance of

semiconductor technology and scaling of devices, digital circuits have achieved both

high speed and low power dissipation. This trend has several impacts on mixed-signal

integrated circuits (ICs). First, increasingly more operations are performed by digital

circuits rather than by their analog counterparts. Second, the speed of the A/D and D/A

interfaces must scale with the speed of the digital circuits in order to fully utilize the

advantages of advanced technologies. Third, cost and performance make it desirable to

achieve the high levels of integration on a single chip for mixed-signal processing

systems.


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The above observations lead to several important design implications for analog

circuits. First, front-end analog signal processing and data conversion (including anti-

aliasing filters) still remain as important niches where analog solutions provide

advantages over digital approaches. A/D converters (ADCs) and D/A converters

(DACs) will continue to play an indispensable and significant role in mixed-signal

processing systems. Second, in video and communications applications, the transfer

rate of the data between the analog and digital domains continues to increase, creating

new challenges in the design of data converters. Third, when a data converter is

implemented on a chip along with a great deal of digital circuitry, it experiences a

substantial substrate and supply noise. Thus, the noise immunity of data converters

becomes an extremely important issue in mixed-signal processing systems. Fourth, the

power consumption of data converters is a critical parameter in many of todays

applications, impacting the cost of packaging as well as the battery lifetime in portable

products.

In general, A/D conversion requires higher power consumption and circuit

complexity than D/A conversion to achieve a given resolution and speed. Therefore,

ADCs often appear as the bottleneck in high-performance mixed-signal systems. This

observation underscores the importance of research and development to improve A/D

conversion algorithms and circuits for future applications [8]-[37].

The goal of this research is to develop new A/D conversion architectures and

circuit techniques that lead to high speed and moderate power consumption in CMOS


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technology, with the objective of achieving a conversion rate well above 100 MHz at a

resolution of 8 bits. Such A/D converters find wide application in digital sampling

oscilloscopes, Gigabit Ethernet over CAT-5 twisted pair cables, RGB-to-LCD data

conversion, and imaging systems with a large number of pixels.

The concepts introduced in this research have been realized in the design of an

8-bit, 150-MHz A/D converter fabricated in a 0.6-m CMOS technology. The

prototype achieved a signal-to-(noise+distortion) ratio (SNDR) of 43 dB at full

sampling rate while consuming 395 mW from a 3.3-V supply.

1.2 Thesis Organization

This dissertation presents both a theoretical study and experimental verification

of the novel architecture and circuit techniques developed during the course of this

research.

Chapter 2 reviews applications of ADCs and conventional ADC architectures.

Chapter 3 introduces the ADC architecture, presenting techniques such as sliding

interpolation, embedded pipelining and interleaving, clock edge reassignment, and

reinterpolation. Chapter 4 describes the design of each building block and various

trade-offs at the circuit level and the architecture level. Some critical layout issues are

also addressed. Chapter 5 presents the test procedure and the experimental results

obtained for the prototype and Chapter 6 provides a summary and recommendations for

future work.


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Chapter 2

ADC Applications and Architectures

In this Chapter, we first describe general potential applications of A/D converters

with sampling rates above 100 MHz and resolutions of about 8 bits. These include digital

oscilloscopes, Gigabit Ethernet receivers, and LCD displays.

Next, we review a number of ADC architectures suited to high-speed operation

and study their speed-resolution-power trade-offs [9]-[21]. Of interest to us are flash,

two-step, pipelined, interleaved, interpolating architectures.

2.1 Applications

2.1.1 Digital Oscilloscopes

Digital oscilloscopes employ high speed ADCs to quantize the probed analog


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signal. For portable digital oscilloscopes, low power consumption and cost are critical.

As shown in Fig. 2.1, an 8-bit A/D converter digitizes input signal, a core DSP processes

the result, and an 8-bit DAC converts the signal back to an analog waveform, which is

then applied to the display.

Figure 2.1 Digital oscilloscope.

2.1.2 Gigabit Ethernet

Gigabit Ethernet over CAT-5 twisted-pair wires requires four 8-bit, 125-MHz

ADCs at the receiver end. The principal challenge in the design of these converters is

power consumption. Shown in Fig. 2.2, the ADCs must provide sufficient dynamic range

so as to accommodate a large echo and signal level variation due to the attenuation

through the cable.

8-bitDSP

ADC

8-bit

DAC

Display


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Figure 2.2 ADC application in Gigabit Ethernet.

2.1.3 RGB-to-LCD Display Conversion

Computer CRT displays typically incorporate three 8-bit RAMDACs to display

the analog RGB images on a CRT monitor. With the advent of flat-panel LCD displays,

it is necessary to convert the analog RGB signals to the form required for LCD displays.

This is accomplished as shown in Fig. 2.3.

High-end LCD displays require an ADC conversion rate of 150 MHz. The power

dissipation is also critical because three such ADCs are integrated on one chip.

8-bitADC

CAT-5

125 MHz

EqualizerDemodulator

Echo Canceller


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Figure 2.3 ADC application in RGB-to-LCD display conversion.

2.2 Architecture Review

2.2.1 Flash Architecture

Figure 2.4 shows the block diagram of an N-bit flash ADC. The analog input

signal is simultaneously compared with threshold voltages of the ADC by an array of 2N

1 comparators, thereby producing a thermometer code. The result is subsequently

converted to a binary output by an encoder. The threshold levels are usually generated by

a ladder consisting of a string of matched resistors.

8-bitDSP

ADC

8-bitDSP

DACLCD

Display

RGB

Display

8-bit

ADC

8-bit

DAC

8-bit

ADC

8-bit

DAC

150 MHz


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Figure 2.4 Block diagram of an N-bit flash ADC.

The operation of a flash ADC can be viewed from another perspective that leads

to techniques such as interpolation. Illustrated in Fig. 2.5 are the differential outputs of

each preamplifier in the ADC as the analog input varies from VMIN to VMAX. We note

that each output crosses zero when the input of the preamplifier crosses its respective

reference voltage. Hence, the ADC operation can be viewed as a collection of these zero

crossings.

= VR[2N1]

VR[2N2]

VR[2]

= VR[1]

Thermometer

Encoder

--> N2N1

0

1 Output

N

+

2N2

1

2

3

VinVref

Comparators

+

+

+

+

+

VMAX

VMIN

2N

1


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Figure 2.5 Transfer curves of an N-bit flash ADC.

The principal advantage of the flash architecture is its high throughput rate. The

conversion of each sample takes only one single clock period. However, many issues

limit the utility of this approach for resolutions above 6 bits. The exponential growth of

the input capacitance, power dissipation, and area are critical drawbacks. Furthermore,

the offset of the comparators, the feedthrough of the analog input to the resistor ladder

[2], the slew-dependent comparator delay [4][7], and the problem of bubbles in the

thermometer code [2][4] degrade the static and dynamic performance substantially.

= VR[2N1]VR[2

N2]

VR

[2]= VR[1]

VMAX

VMIN

VMINVin

VMAX

0

2N1 Zero-crossings


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2.2.2 Two-Step Architecture

In order to avoid the exponential growth encountered in flash ADCs, the

quantization of the signal can be performed in two or more steps. The basic principle of

the two-step architecture can be illustrated by the mapping scheme of a 4-bit ADC as

shown in Fig. 2.6. In the two-step topology, the input range is first divided into four equal

segments, and a coarse quantizer is used to determine in which segment the analog input

lies, thus producing the most significant bits (MSBs). Next, each segment is subdivided

into four segments, and a fine quantizer detects the least significant bits (LSBs).

Figure 2.6 Mapping scheme of a 4-bit two-step ADC.

A more detailed description of the operation is depicted in Fig. 2.7 , where the

block diagram of an N-bit, two-step ADC and the conversion flow are illustrated. The

circuit consists of a sample-and-hold amplifier (SHA), two flash quantizers, D/A

overflow

11

10

01

00

11

10

01

00

MSB LSB overflow

Coarse FineQuantizer Quantizer


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converter, and a subtractor.

Figure 2.7 Block diagram of an N-bit, two-step ADC.

11

10

01

00

11

10

01

00

MSB LSB

Coarse Fine

Analog

Digital

1011

Residue

SubtractorQuantizer Quantizer

input

Output

Coarse

N1-bit

ADCDAC

N1-bit

S/H

N-bit Digital Output Buffer

N1 MSBs N2 LSBs

N-bit Digital Output

Analog Input

(a)

Residue

Vin

Vres

Fine

N2-bit

ADC

(b)

Vin

V1

Dout

DoutVres


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The conversion proceeds as follows: an analog input signal with magnitude ofVin

is sampled by the SHA and subsequently mapped onto the level V1 by the coarse

quantizer, resulting in the two MSBs, e.g., 10 in this case. Next, an analog residue, Vres

,

is produced by the subtractor and digitized by the fine quantizer, thereby generating the

two LSBs.

The primary advantage of the two-step topology is that it requires less hardware

and power than a flash architecture. However, this savings is obtained at the cost of longer

processing time, leading to a substantial reduction of the throughput rate.

2.2.3 Pipelined Architecture

From the above discussion, it is clear that the use of multiple stages can alleviate

the exponential growth present in flash topologies. The two-step architecture exemplifies

this benefit to a certain degree, but the low throughput rate limits the use of this approach.

Pipelining enables potentially faster conversion while avoiding the exponential

growth of power and hardware.

Figure 2.8 illustrates the block diagram of a pipelined ADC. The analog input is

applied to the first stage in the chain, and N1 bits are detected. The analog residue is also

generated and applied to the next stage. The same procedure repeats up to the end of the

chain. This concept is similar to the idea of an assembly line because the interstage

sampling allows all of the stages to operate concurrently.

A common approach to pipelining is based on a precision multiply-by-two stage


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[7] that merges most of the interstage operations into a compact circuit. Usually used with

0.5 bits of overlap, this technique provides a modular implementation.

Figure 2.8 Block diagram of a pipelined ADC.

The pipelined architecture offers a number of advantages. First, the throughput

rate is determined by the speed of only one stage in the pipeline. Second, interstage

residue amplification relaxes the precision required of subsequent stages. Third, the

power and hardware of pipelined converters grow almost linearly with the number of bits.

Also, overlap and digital correction [2] can be used to allow large offsets in the

comparators.

The primary drawback of the conventional pipelined topology is the need for high

Stage 1 Stage j Stage m

Nj-bit

ADC DAC

Nj-bit

S/H

Nj bits

2Nj

N1 bits Nm bitsNj bits

Analog

Input


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precision in the interstage SHAs, DACs, and subtractors, especially at the front end. The

precision typically mandates the use of op amps, imposing severe trade-offs among

speed, voltage swing, gain, and power dissipation. As device dimensions, supply

voltages, and the intrinsic gain (gmro) of MOSFETs continue to scale down, the design

of op amps becomes increasingly more difficult.

2.2.4 Interleaved Architecture

In the pipelined topology, the conversion rate is still limited by the settling time

and accuracy requirements of the interstage operations. Interleaving can be used to

further improve the throughput rate.

The basic principle behind interleaving is illustrated in Fig. 2.9. The architecture

employs Midentical sub-ADCs, each incorporating a SHA that tracks for T1 seconds and

holds for (M1)T1 seconds. Thus, each sub-ADC is allotted (M1)T1 seconds for one

conversion.

The use of multiple parallel channels, however, introduces serious difficulties due

to mismatches [14]. Tones at fck/Mand fixed-pattern noise are generally caused by offset

mismatches and sideband modulation aroundfck/Mis introduced due to gain mismatches.

The dynamic performance is severely affected by the timing mismatch among the

channels [5][6].


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Figure 2.9 Block diagram of an interleaved ADC.

Vin

Nbits

Sub-ADC1

DigitalOutput

CK1

@ Mx fck

SHA1

Nbits

Sub-ADC2

CK2

SHA2

Nbits

Sub-ADCM

CKM

SHAM

CKM

CK2

CK1

t

T1 (M1)T1


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2.2.5 Interpolating Architecture

As mentioned in Section 2.2.1, one of the critical disadvantages of the flash

topology is the large input capacitance. This problem can be alleviated by applying

interpolation as shown in Fig. 2.10. The idea is that ifVin crosses (VR2 + VR1)/2, then Vo2

crosses zero, increasing the resolution by a factor of two. In essence, interpolation adds

zero crossings to the set of input/output characteristics of a flash stage.

Figure 2.10 A 2x active interpolating ADC.

Interpolation lends itself to implementation submicron technologies because the

amplifiers used in Fig. 2.10 need not have an accurate gain, high linearity, or large output

swings. Also, it can reduce the differential nonlinearity (DNL) resulting from the offset

of the preamplifiers [30]. However, the simple scheme shown in Fig. 2.10 still requires

21 + 1 22 + 1 2N+ 1

Vin

VR1

VR2 Vo3

Vo1

Vo2

PreamplifiersInterpolating

Amplifiers

20 + 1


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high power and substantial hardware because of the 2x growth in each interpolation step.

Furthermore, the offset voltages of the amplifiers lead to uncorrected integral

nonlinearity (INL).


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Chapter 3

Proposed ADC Architecture

In this Chapter, we describe the architecture of the proposed A/D converter. We

introduce the concept of sliding interpolation as a means of avoiding the exponential

growth of power and area, extending the idea to multiple stages. Next, we incorporate

a distributed sampling scheme between the stages so as to realize pipelining without op

amps. To further improve the conversion rate, dual-channel interleaving is employed in

all of the interpolative stages, while triple-channel interleaving is used in the front-end

sample-and-hold circuit. In order to minimize dynamic performance degradation due to

the timing mismatch among the channels in an interleaving system, a new technique,

namely clock edge reassignment is proposed. The concept of reinterpolation is also

introduced to reduce the INL by roughly 30%. Finally, the effects of the gain and offset

mismatches among different channels are studied in a generic interleaved architecture


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with interpolation.

3.1 Sliding Interpolation

Interpolation can generally be viewed as analog-to-digital conversion in terms

of zero-crossing points rather than direct amplitude quantization. The basic operation

can be described as follows. A group of preamplifiers first generate the difference

between the analog input signal and each tap voltage of a reference ladder. According

to their polarities, the outputs of these preamplifiers can be divided into two groups:

positive and negative, with a distinctive boundary between them. This phenomenon is

similar to what happens inside a thermometer and can be used later to recover the actual

amplitude information of the original analog input signal. These preamplifier outputs

can then be fed into the next-level bank of interpolating amplifiers, whose outputs retain

the thermometer code property. With the aid of these interpolating amplifiers, this code

contains more divisions and hence a higher resolution. As long as the zero-crossing

boundary is unique and the code exhibits sufficient linearity, the original analog signal

can be recovered.

Before introducing the concept of sliding interpolation, let us first briefly review

the traditional active interpolation. As an example, a simple active 2x interpolation

circuit is shown in Fig. 3.1. While this scheme reduces the number of the input

preamplifiers and hence the input capacitance, it still requires a large number of

differential pairs and comparators. However, we recognize that for a given input level,

the outputs of only a few preamplifiers in the first stage are of interest. Thus, the


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subsequent stages need not interpolate the outputs ofall of the preamplifiers. We then

surmise that a compact interpolating stage can slide up and down if the analog input

value is roughly known. Shown in Fig. 3.2, the idea is to use a sub-ADC to determine

which preamplifier outputs must be interpolated and route these outputs to the

interpolating differential pairs through a differential multiplexer (MUX). The rest of the

preamplifier outputs are discarded.

Figure 3.1 Traditional active 2x interpolation architecture.

While, in principle, multiplexing and interpolating between only two outputs is

sufficient, in this design we process four preamplifier outputs to allowmargin for offsets

of the comparators in the sub-ADC. When this concept is repeatedly applied to the

following stages, a multi-stage sliding interpolation system can be formed.

2 21 + 1 22 + 1 2N + 1

Vin

VR1

VR2Vo3

Vo1

Vo2

PreamplifiersInterpolating

Amplifiers


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Figure 3.2 Sliding interpolation architecture.

Through the sliding interpolation, the power and hardware grow only linearly,

rather than exponentially. These features make sliding interpolation a promising

architecture for high-speed ADCs.

The principle of multi-stage sliding interpolation is illustrated in Fig. 3.3. The

first stage has 16 preamplifiers to generate 16 zero crossings. If the analog input lies

between VR,j and VR,j+1, then a 4-bit coarse ADC and a 16-to-4 MUX route the outputs

of the preamplifiers sensing VR,j1,..., VR,j+2 to the next interpolating stage.

MUX

Sub-ADC

Vin

VR1

VR2

Vo3

Vo1

Vo2


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Figure 3.3 Flow diagram of multi-stage sliding interpolation.

Since only 2x-interpolation is used, each stage, excluding the first one,

generates a total of seven outputs. Also a sub-ADC is used to detect two more bits in

each stage. The overall resolution is increased by one bit because the second bit is used

for subsequent digital error correction.

Detection of zero crossings can be implemented by a simple differential

amplifier. Therefore, all of the decision levels in Fig. 3.3 can be replaced by amplifiers

as shown in Fig. 3.4.

Vmax

Vmin

Vin

Stage 1 Stage 2 Stage 3 Stage 4

MUX(16 --> 4)

MUX(7 --> 4)

MUX(7 --> 4)

VR,j1

VR,j+2


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Figure 3.4 Sliding interpolation architecture.

If the gain of every amplifier in each stage is about two, the input dynamic range

of the sub-ADCs remains nearly the same through the chain. All of the sub-ADCs can

therefore be realized in the same form, allowing a modular design.

Vmax

Vmin

Vin

Stage 1 Stage 2

MUX(16 --> 4)

MUX(7 --> 4)

MUX(7 --> 4)

Stage 3 Stage 4


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Figure 3.5 Block diagram of multi-stage sliding interpolation.

The implementation of the sliding interpolation is shown in Fig. 3.5. The front-

end SHA samples and holds the analog input signal. In stage 1, the preamplifiers

generate 16 zero crossings, while the sub-ADC determines the four MSBs. In the

second and the following stages, each MUX is commanded by the sub-ADC in the

previous stage to select and route four amplified outputs to the interpolative amplifiers.

Stages 2 through 5 are identical, simplifying the design and layout.

Sub-ADC

MUX

Sub-ADC

Sub-ADC

MUXPre-AMP

Sub-ADC

MUXInterpolative

AMP

Stage 2 Stage 3 Stage 4Vin

SHAInterpolative

AMP

Interpolative

AMP

Stage 1

Vmax

Vmin

Vin

(a)

(b)


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Further details of the sliding interpolation are shown in Fig. 3.6. The first stage

incorporates 16 preamplifiers while each of the following interpolative stages requires

seven amplifiers. By virtue of this technique, the total number of differential pairs

reduces from roughly 500 to 50. The five sub-ADCs require a total of 28 comparators.

Figure 3.6 Detailed block diagram of multi-stage sliding interpolation.

Sub-ADC

16Preamps

Stage 2 Stage 3 Stage 4

Vin

SHA

MUX

2x-Interpolation

416

Sub-ADC

MUX

2x-Interpolation

47

Sub-ADC

MUX

2x-Interpolation

47

Sub-ADC

4 bits 2 bits 2 bits2 bits

(16 --> 4)(7 --> 4) (7 --> 4)

Stage 1


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26

Figure 3.7 Sliding mechanism

-0.1 -0.08 -0.06 -0.04 -0.02 0 0.02 0.04 0.06 0.08 0.1-1

-0.5

0

0.5

1

Input (V)

Sliding Interpolation (5 Stages)

A: Stage 1

Output(V)

-0.1 -0.08 -0.06 -0.04 -0.02 0 0.02 0.04 0.06 0.08 0.1-1

-0.5

0

0.5

1

B: Stage 2

-0.1 -0.08 -0.06 -0.04 -0.02 0 0.02 0.04 0.06 0.08 0.1-1

-0.5

0

0.5

1

C: Stage 3

-0.1 -0.08 -0.06 -0.04 -0.02 0 0.02 0.04 0.06 0.08 0.1-1

-0.5

0

0.5

1

D: Stage 4

-0.1 -0.08 -0.06 -0.04 -0.02 0 0.02 0.04 0.06 0.08 0.1-1

-0.5

0

0.5

1

E: Stage 5

Input (V)

Output(V)


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Figure 3.7 plots the amplifier outputs in each stage as sliding interpolation is

activated. The outputs of the first stage exhibit zero-crossing points that are separated

by 50 mV. After sliding interpolation with redundancy, zero crossings with 25-mV

spacing are generated, etc.

Sliding interpolation provides a number of benefits. First, as described before it

lends itself well to the multi-stage pipelining with no D/A converters or subtractors.

Second, it requires no precision gain in any of the building blocks, allowing the use of

simple differential pairs in the entire signal path. Third, it can include reinterpolation to

improve the precision.

Although, the hardware size and the associated power consumption in the

sliding interpolation structure are substantially less than those in the traditional

interpolation method, the throughput rate is severely limited by the multi-stage

operation. For each held analog input sample, the overall A/D conversion is not

complete unless the digital data is generated by all of the sub-ADCs, an operation that

can easily take several tens of nanoseconds. For a higher conversion rate, a pipelining

scheme is needed.

3.2 Embedded Pipelining

As mentioned before, pipelining can improve the throughput rate. The question

is where and how it should be applied. As shown in Fig. 3.6, each interpolative stage

contains only two analog blocks, a MUX and an amplifier bank. Thus, pipelining can

be applied at only one of two points: at the input or output of the MUX.


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Figure 3.8 Pipelined sliding interpolation ADC architecture.

As shown in Fig. 3.8, the interface between the multiplexer and the amplifier

bank is the best choice. This is so for two reasons. First, the multiplex switches can also

function as the sample-and-hold switches, significantly reducing the delay between the

two stages because only one switch appears in the signal path between two consecutive

stages. Second, the interconnection wires between the multiplexers and the

interpolative amplifiers exhibit a significant amount of parasitic capacitance, which can

Sub-ADC

16Preamps

MUX

2x-Interpolation

416

Sub-ADC

4-bit 2-bit

(16 --> 4)

Distributed

Sampling &

Digital Error Correction

Vin

SHA

Stage 1 Stage 2

Tostages 3 to 5


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now be utilized as the sample-and-hold capacitors. This type of distributed sample-and-

hold system is similar to that reported in [19]. Partitioning the conversion into several

equal-length time slots, the pipelining significantly improves the throughput rate.

Note that each stage in the pipeline operates in the sample mode for half of the

clock period and in the hold mode for the other half. On the other hand, the sub_ADC

in each stage operates only during the hold mode, raising the possibility of adding

interleaving to further increase the throughput rate.

3.3 Addition of InterleavingBesides the reasons mentioned in the previous section, the addition of

interleaving is also desirable because, even though the maximum path length between

consecutive samplers in the pipeline corresponds to roughly two differential pairs, the

settling requirements still limit the conversion speed. As shown in Fig. 3.9, the

converter employs two identical interleaved channels to increase the speed. The

multiplexers (MUXs), distributed sample-and-holds, and 2x-interpolation amplifiers

are duplicated for the even and the odd channels whereas the front-end buffer, the

preamplifiers, and all of the sub-ADCs are shared between the two channels. The timing

is such that when one stage in the odd channel is in the sampling mode, the

corresponding stage in the even channel is in the hold/amplification mode and vice

versa.


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Figure 3.9 Addition of interleaving scheme.

When the SHA in the odd channel is sampling the analog input, the SHA in the

even channel is holding and passing the previous analog sample to the preamplifiers

through the buffer. The sub-ADC in stage 1 then generates the four-bit digital code and

commands the MUX in the even channel of stage 2 to redirect the selected preamplifier

outputs to the interpolation amplifiers.

Even though the addition of interleaving increases the speed by almost a factor

of two, the first sub-ADC still creates three difficulties. First, due to the finite

impedance seen at the preamplifier outputs, the kickback noise generated by the sub-

SHA(even)

Sub-ADC

SHA(odd)

Vin

Stage 2Stage 1

(odd)

(even)

Sub-ADC

OFF

OFF

(odd)

(even)

DistributedS/H & 2x

Interpolation

MUX

Stage 3

Digital Output

DistributedS/H & 2x

Interpolation

MUX

DistributedS/H & 2x

Interpolation

MUX

DistributedS/H & 2x

Interpolation

MUX

ON

ON

Buffer

Preamps


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ADC considerably disturbs the analog signals at the inputs of the MUX thereby

requiring a long settling time after the sub-ADC is strobed. Second, the sub-ADC

cannot begin its conversion until the front-end SHA, the buffer, and the preamplifier

outpus are settled. Since the buffer drives a relatively large capacitance, the settling in

this path is quite slow. Third, since the sub-ADC appears in the critical path, that is, the

preamplifier outputs must remain idle until the sub-ADC makes a decision, the

throughput rate is severely limited.

Figure 3.10 Complete ADC architecure with replica SHA.

SHA

(even)

Sub-ADC

SHA(odd)

Vin

Stage 2Stage 1

(odd)

(even)

Sub-ADC

OFF

OFFReplica

(odd)

(even)

Distributed

S/H & 2xInterpolation

M

UX

Stage 3

Digital Error Correction

Digital Output

Distributed

S/H & 2xInterpolation

M

UX

DistributedS/H & 2x

Interpolation

MUX

DistributedS/H & 2x

Interpolation

MUX

ON

ON

SHA(even)

SHA(odd)

Buffer

Buffer

Preamps


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Figure 3.10 illustrates a modification that alleviates all of the above issues. A

replica front-end SHA is added and its output directly drives the first sub-ADC.

Scaled down in device sizes and current levels by a factor of two with respect to the

main SHA, the replica prohibits the large kickback noise of the sub-ADC from

corrupting the output of the preamplifiers. Also, the replica signal experiences a shorter

delay than that in the main path because of the much smaller load capacitance seen by

the replica buffer. Thus, the sub-ADC can be strobed much earlier than before.

The use of interleaving raises concern with respect to mismatches between the

offsets, gains, and timings of the two channels. The first two issues will be discussed in

Section 3.6. The problem of the timing mismatch and the proposed solution are

described in the next section.

3.4 Clock Edge Reassignment

Before proposing a solution for the timing mismatch problem in interleaved

systems, we revisit the problem itself to understand its nature. As shown in Fig. 3.11(a),

two interleaved channels, SHA1 and SHA2, require two corresponding clocks, CK1 and

CK2, which are generated by two different clock generators. In the ideal case, the

sampling edge ofCK1 is placed precisely midway between the sampling edges ofCK2

such that SHA1 and SHA2 sample the analog signal at evenly-spaced points in time.


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Figure 3.11 (a)Timing mismatch in interleaved architecture, (b)generation ofCK1 and

CK2 by a frequency divider.

This is usually accomplished by a frequency divider [Fig. 3.11(b)], producing

CK1 and CK2 with a nominal duty cycle of 50% even if the duty cycle ofCKin deviates

from 50%. In reality, however, the devices in the clock generators ofFig. 3.11(a) or the

frequency divider ofFig. 3.11(b) suffer from substantial mismatches, especially at high

Ta Tb

2T = Ta + Tb

CK1

SHA1Clock

CK2

CK1

CK1a

Generator 1

CK2

SHA2Clock

CK2a

Generator 2

CKinCK1CK2

2

(a)

(b)


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34

speeds, introducing large timing errors between CK1 and CK2. Since an 8-bit ADC

sampling a 75-MHz signal cannot tolerate timing mismatches greater than roughly

12 ps, frequency division does not provide the accuracy required in this design.

The problem of timing mismatch can be considerably relaxed if a single clock

drives both SHAs. Since the duty cycle of the clock may deviate from 50%, only one of

the edges must be used for the sampling command in both circuits. Figure 3.12

illustrates how this is accomplished by clock edge reassignment. Two switches, S1

and S2, and two predictive control signals, Vodd and Veven, are added to the system. A

master clock, CKmaster, with a frequency twice the sampling rate, is provided to the two

channels through the two switches. The predictive signals Vodd and Veven enable one of

the switches S1 or S2, thus routing the falling edge ofCKmaster to either of the SHAs.

The timing mismatch is now equal to the propagation delay mismatch between S1 and

S2, and the two switches inside SHA1 and SHA2, a value that can be maintained well

below 10 picoseconds even with 20% mismatch between the sizes of the switches.

The timing of Vodd and Veven is quite relaxed so long as they contain the falling

edge of CKmaster with enough margin. Thus, they can be produced by a simple

nonoverlapping clock generator.

In reality, each SHA requires both a rising edge and a falling edge to perform

the sample and hold operations. As shown in Fig. 3.13, the falling edges ofCK1x and

the rising edges ofCK2x are alternately applied to the SHAs, while the rising edges of


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35

CK1x and the falling edges ofCK2x are discarded.

Figure 3.12 Basic concept of the clock edge reassignment.

The actual sequence of operation is as follows: during phase 1, the falling edge

ofCK1x is routed to SHA1 and the rising edge ofCK2x to SHA2. During phase 2, the

states ofCK1 and CK2 are stored, and during phase 3, the falling edge ofCK1x is re-

routed to SHA2 and the rising edge ofCK2x to SHA1.

This concept can be easily extended from two channels to three, or more

channels. As discussed in Section 6.2, the front-end sample-and-hold circuit used in this

work incorporates three channels.

Vodd

Veven

CKmaster

CKmaster

SHA2

Veven

Vodd Vin

SHA1

S1

S2

To SHA1 To SHA2
http://chapter5b.pdf/http://chapter5b.pdf/


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Figure 3.13 Detailed operation of clock edge reassignment.

3.5 Reinterpolation

As mentioned in Chapter 3, an important benefit of interpolation is the reduction

of the differential nonlinearity resulting from the offset of the preamplifiers [2,3].

However, integral nonlinearity still remains uncorrected, demanding large input

devices. To alleviate the problem, a reinterpolation method is introduced here. As

depicted in Fig. 3.14(a), the original outputs (VAs) from the preamplifiers are fed into

another bank of interpolation amplifiers to generate a second set of interpolated outputs

(VBs) which, though different from VAs, contain sufficient information to represent the

original analog input signal. If the offset components of the adjacent VAs are

TT

CK1xSHA1

A1

1

CK1

CK2x

SHA2

A2

CK2

SHA1

2

CK1

SHA2

CK2

SHA1

CK1

SHA2CK2

3

EvenEven

Odd

Even

OddOdd

21 3 2 1

CK1x

CK2x

CK1x

CK2x

CK1

CK1x (from A1)

CK2

TT

CK2x (from A2)

A2


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uncorrelated, the standard deviation of the offsets of the corresponding VBs is reduced

by a factor of the square root of 2. As shown in Fig. 3.14(b), INLA or INLB is defined

as the maximum offset error of the zero crossings ofVAs or V

Bs respectively. If only

the interpolatedzero crossings, VBs, are sensed by the following stages and the original

zero crossings, VAs, are discarded, then, the overall INL is reduced by approximately

30%.

Figure 3.15 plots the maximum INL with and without reinterpolation as

predicted by Monte Carlo simulations, confirming the theoretical result. The reduction

of the INL translates into a higher tolerance of offsets in the preamplifiers, allowing

smaller input devices and a two-fold reduction in the capacitance seen by the buffer

driving the first stage.

The redundancy associated with reinterpolation is necessary only in the first

stage of the pipeline, where the cumulative gain is still low; in stages 2 through 5 all

zero crossings are utilized. Thus, reinterpolation is obtained at the cost of a few

additional differential pairs.


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38

Figure 3.14 Reinterpolation (a) implementation, (b) error plot.

(b)

0INLA INLB

A1

B1

A2

Bs: Interpolated Offsets

As: Original Offsets : Original Zero Crossings

VA1

VB1

VA2

VB2

VA3

(a)

INL

Vin

VA1, VA2, VA3 discarded

: Interpolated Zero Crossings

Preamplifiers

Reinterpolation

Amplifiers Interpolation

Amplifiers

A1 + A2

B1

B1 =2

=

2

2A1 2

A2+

=

2

original


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Figure 3.15 INL reduction by reinterpolation observed in Monte Carlo simulations.

SymbolWave

D0:A0:v(va1)

D0:A0:v(va2)

D0:A0:v(va3)

D0:A0:v(va4)

D0:A0:v(va5)

D0:A0:v(va6)

D0:A0:v(va7)

D0:A0:v(va8)

D0:A0:v(va9)

D0:A0:v(va10)

D0:A0:v(va11)

D0:A0:v(va12)

D0:A0:v(va13)

D0:A0:v(va14)

D0:A0:v(va15)D0:A0:v(va16)

Voltages(lin)

-20m

-15m

-10m

-5m

0

5m

10m

15m

20m

Voltage X (lin) (VOLTS)-1

-500m 0 500m1

* offset averaging mechanism through interpolation by 2

SymbolWave

D0:A0:v(vb1)

D0:A0:v(vb2x)

D0:A0:v(vb3x)

D0:A0:v(vb4x)

D0:A0:v(vb5x)

D0:A0:v(vb6x)D0:A0:v(vb7x)

D0:A0:v(vb8x)

D0:A0:v(vb9x)

D0:A0:v(vb10x)

D0:A0:v(vb11x)

D0:A0:v(vb12x)

D0:A0:v(vb13x)

D0:A0:v(vb14x)

D0:A0:v(vb15x)

D0:A0:v(vb16x)

Voltages(lin)

-12m

-10m

-8m

-6m

-4m

-2m

0

2m

4m

6m

8m

10m

Voltage X (lin) (VOLTS)-1-500m 0 500m

1

Panel 2


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40

3.6 Effect of Nonlinearity in Sliding Interpolation

While the first stage of interpolation by a factor of two is quite insensitive to the

nonlinearity of differential pairs [2], the subsequent reinterpolation and interpolation

are susceptible to nonlinearity in each differential pair. Figure 3.16 illustrates the effect.

Curves A and B are the original characteristics with the zero-crossing points at V0 and

V2. After first 2x interpolation, curve C is generated with a zero crossing at V1 and a

slope of one half of the original one. If one more 2x interpolation is applied between

curves B and C as shown in the circled area in Fig. 3.16, the resulting zero-crossing

point should ideally fall midway between V1 and V2, i.e., at Vid. In practice, however,

the actual zero-crossing point, Vact, deviates from Vid because B and C exhibit different

slopes. The difference between Vact and Vid is denoted by .

In the worst case, curve A is flat for Vin > V1 and the slope of curve C is equal

to one half of that of B. Through a simple derivation, it can be shown = (V2 - V1)/6

and hence curve D suffers from a DNL of 1/3 LSB. In order to further increase the

resolution through active 2x interpolation, the linear portion of curves A or B must be

extended accordingly.


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Figure 3.16 Nonlinearity-induced error in 2x interpolation.

B

C

D

B

C

A

ActualPosition

IdealPosition

Vid

Vact

V2

V1

V2

V1

V0

Vin

Vin


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Chapter 4

Circuit Design and Layout

Considerations

4.1 Introduction

In this chapter, the design of the ADCs building blocks as well as various layout

considerations are discussed. All of the analog signal paths are implemented in

differential form to achieve a wide dynamic range and high immunity to common-mode

noise. For the sake of simplicity, some of the circuits are drawn in single-ended form.

4.2 Front-End Sample-and-Hold Circuit

The front-end SHA plays a critical role in the dynamic behavior of the converter.

In order to achieve fast settling, this circuit uses a simple top-plate sampling method and

a PMOS source follower as shown in Fig. 4.1.


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Figure 4.1 Dual-channel interleaved SHA.

The interleaving is realized in the sampling network by alternately connecting

C1 and C2 to Vin whereas the source follower is shared between the two channels. Thus,

gain and offset mismatches arise primarily from the charge injection mismatches ofS1-

S4. The n-well of the source follower is tied to its source to suppress nonlinearity and

gain error due to body effect. Simulations indicate that two such followers operating

differentially achieve a linearity of about 10 bits.

The input-dependent charge injection from S1 and S3 does introduce

nonlinearity but it is partially cancelled by the charge absorbed by S2

and S4. Also,

differential operation as well as large sampling capacitors (1 pF) improve the overall

linearity to about 9 bits.

Vout

Vin M1

C1

VDD

S1 S2

C2

S3 S4

X

CK1aCK1b

CK1a CK1b


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The finite input capacitance of the source follower results in an equivalent

resistor connected between the outputs of the two channels, yielding a gain roll-off at

high frequencies. From another perspective, the capacitance seen at node X and

switches S2 and S4 form a switched-capacitor low-pass filter. With proper design, this

roll-off is limited to 1 dB at an input frequency of 75 MHz.

Figure 4.2 Timing diagram for SHA.

In the actual design, the front-end SHA is realized with triple-channel

interleaving. This is because the sampling phase is quite faster than the hold/

quantization/multiplexing phase, thereby requiring a clock duty cycle of about 30%

[Fig. 4.2(a)]. Since the duty cycle deviates substantially from 50%, it is difficult to

employ dual-channel interleaving without any dead time. To resolve this issue, the

clock period is divided into three equal time slots: one for front-end sampling, one for

CKb

CKc

CKa

Sample

(a)

(b)

Quantize/MUX

CK

Sample Quantize MUX t

(c)


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sub-ADC (coarse quantization), and one for multiplexing [Fig. 4.2(b)]. The timing

diagram ofFig. 4.2(c) is then used to interleave three sampling capacitors. To generate

the time slots with reasonable accuracy, the 150-MHz clock is divided by 3 on the chip.

Figure 4.3 A triple-channel interleaved SHA with a replica.

The actual triple-channel interleaved SHA circuit is shown in Fig. 4.3. As

mentioned before, the replica is scaled down by a factor of two with respect to the main

Vout, r

Vin

M1r

CK1a CK1b

C1r

VDD

S1r S2r

CK1cCK1b

C2r

S3r S4r

C3r

S5r S6r

CK1aCK1c

Vout, m

M1m

CK1aCK1c

C1m

VDD

S1mS2m

CK1a CK1b

C2m

S3mS4m

C3m

S5mS6m

CK1b CK1c

Main SHA Replica SHA

(To Preamps) (To sub-ADC1)


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SHA. The switches connected between Vin and the sampling capacitors use the same

timing sequence in both of the main and the replica SHAs. However, the switches

connected between the sampling capacitors and the PMOS source followers have a

different timing sequence in the two SHAs. For each channel in the main SHA, the

operation sequence is: (1) sampling, (2) holding, (3) holding and connecting the held

sample to the PMOS source follower. On the other hand, the replica operates in a

slightly different sequence: (1) sampling, (2) holding and connecting the held sample

to the PMOS source follower (whose output is then sensed by the first sub-ADC ). (3)

holding.

4.3 Differential Amplifiers

The A/D converter incorporates differential difference amplifiers in the first

stage and simple differential pair in the subsequent stages. The resistors used in the

prototype are realized by non-silicided polysilicon.

As shown in Fig. 4.4, the preamplifier consists of two NMOS differential pairs

with source degeneration. In order to properly transform amplitude quantization into

zero crossings, the design of the preamplifiers requires special attention to several

issues. First, the input-referred offset of the circuit must be less than 1/4 LSB so that it

does not degrade the overall DNL and INL significantly. The offset arises from three

sources: mismatch between the input transistors, mismatch between the load resistors,

and mismatch between the tail current sources. The mismatch of the differential pair


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typically dominates the overall offset.

Figure 4.4 Preamplifier.

By virtue of reinterpolation the tolerable offset is 30% higher and, with the aid

of the data in [39], the dimensions ofM1a - M4a are chosen as W/L = 100 m/0.6m.

This results in a total gate area of 60 m2, about one half of that reported in [19]. The

matching requirement of the output resistors is alleviated by the gain of the preamplifier

and with proper layout. The mismatch of the tail current sources is reduced significantly

by using a channel length of 1.5 m and a channel width of 48 m.

The second issue relates to the gain of the preamplifier. The gain is chosen to be

around two as a trade-off between gain, linearity, and speed. Finally, although the

M1a

VDD

M2a

R1a R2a

Vout

Vout+

Vin+

Vir+

Rc1a

I2aI1a

R1a, R2a: 4x200

Rc1a, Rc2a: 200

I1a-- I4a: 0.4 mA

M1a-- M4a: 8x12/0.6

(4x12/1.5)

M3a M4aVin

Vir

Rc2a

I4aI3a


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48

output of preamplifiers has a small swing, about 200 mV single-ended, the

preamplifiers do require a wide input common-mode range, approximately 800 mV.

This common-mode constraint limits the overdrive voltage of the input devices and the

tail current source. The current densities must therefore be low enough to consume a

reasonable headroom. This is possible for the current source but not for the input

transistors as their linearity determines the DNL and INL in subsequent interpolation

stages.

The reinterpolating and interpolating amplifiers have the same topology but

different device dimensions and bias currents. Figure 4.5 shows the details.

Figure 4.5 Reinterpolating and interpolating amplifiers.

M1b

VDD

M2b

R1b R2b

Vout

Vout+

Vin+

Vin

I2bI1b

M1b, M2b: 12x8/0.6

R1b, R2b: 4x125

Reinterpolating Amp

I1b, I2b: 0.8 mA

Interpolating Amp

M1b, M2b: 12x4/0.6

R1b, R2b: 2x500

Rc1b: 2x200

I1b, I2b: 0.4 mA

Rc1b

Rc1b: 2x200


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4.4 Comparator

The design of the comparators used in the sub-ADCs directly impacts the speed

and power dissipation of the overall converter. Shown in Fig. 4.6 is the high-speed

comparator utilized in the first stage sub-ADC. When CKis low, Sb1 and Sb2 are off. All

the p-switches (S1 - S4) are on and the four internal nodes (P, Q, X, and Y) are pulled up

to VDD with the aid of two equalization switches (Seq and Seqx), placing the comparator

in the reset mode. When CKgoes high, Sb1 and Sb2 turn on and M1 - M4 compare the

positive input voltage,V

in

+

, with the positive reference voltage,V

r

+

, and the negative

input voltage, Vin, with the negative reference voltage, Vr

+. When all of the reset and

equalization PMOS switches are off, the cross-coupled inverters (M5 - M8)

regeneratively amplify the difference between the inputs to rail-to-rail levels. The

digital outputs are buffered by inverters and then fed to the control circuit.

This comparator offers three important advantages over other topologies. First,

the static power dissipation is zero. When CKis low, no static current flows through the

circuit. When CK is high, M7 and M8 ensure that the current is zero. Second, the

comparator requires only a single-phase clock, greatly simplifying the routing of the

clock across the chip.


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Figure 4.6 Comparator used in the first stage (CMP_A).

The third property of the comparator is that the effect of the offsets due to the

cross-coupled transistors is reduced by the dynamic gain of the input stage. This effect

can be described in two phases.

This is because when CKgoes high, nodes X, Y, P, and Q are precharged to VDD

and M5 - M8 are off. The input difference is therefore amplified by M1 - M4 and the

parasitic capacitances at nodes Xand Yuntil Vx and Vy drop below VDD by VTHN. At

M1 M2Vin

+Vr

+

Vout+

Vout

M5 M6 CKS2S1

Sb1

CK

CK

S3CK CKS4

M7 M8

Inv1

Inv2

CK

M3 M4Vin

Vr

Sb2CK

Cf

Cf+

M1, -- M4: 10.8/0.6

M5, -- M8: 2.4/0.6

Seq: 2.4/0.6

Sb1, b2 : 6.0/0.6

S1, 2: 1.8/0.6

Inv1,2 : p-- 4.8/0.6, n-- 1.2/0.6

Seqx: 3.0/0.6

S3, 4: 3.0/0.6

Cf+, f : 8 fF

P Q

X Y

CK

Seq

Seqx


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this point, M7 and M8 turn on but M5 and M6 are still off. The amplification then

continues while M5 and M6 contribute a small regenerative gain until M5 and M6 turn

on, and initiate the final regeneration.

Using SPICE, it is possible to calculate the contribution ofM5 - M6 and M7 - M8

to the input-referred offset. With the device dimensions chosen in this design,

simulations suggest that the offset voltages ofM5 and M6 is divided by a factor of 20

and that ofM7 and M8 by a factor of 2. Since the channel area ofM7 and M8 is about

one fourth of that of the input devices, they contribute roughly equal amounts of input-

referred offset. The overall offset of the comparator is about 10 mV.

Another important phenomenon in the comparator is the large kickback noise

produced at the beginning of reset and regeneration modes. This effect is particularly

critical in the first stage and can introduce significant dynamic offsets, saturating the

second stage and creating nonlinearity. Adding a pair of cross-coupled capacitors with

proper value (around 8 fF) at the input reduces the kickback noise to an acceptable level.

As shown in Fig. 4.7, the comparators in stages 2 to 5 are basically the same as

that in the first stage, except for the input network. The multiplexers consisting ofSi1 -

Si4 select the even- or odd-channel signals in a dual-channel interleaving mode. Due to

the accumulative gain after stage 1, larger comparator offsets can be tolerated in stages

2 to 5. Therefore, the input differential pair uses W/L = 5.4 m/0.6 m.


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Figure 4.7 Comparator used in stages 2 to 5 (CMP_B).

Unlike the first stage, the comparators in stages 2 to 5 do not share the same

input line because they are driven by the interpolation amplifier outputs. Thus, the

kickback noise is less important here.

M1 M2

Vie+

Vio+

Vout-

Vout+

M5 M6 CKS2S1

Sb

CK

CK

CK

S3CK CKS4

M3 M4

Inv1

Inv2

CK

CK_2ec

CK_2oc

Vie

Vio

CK_2ec

CK_2oc

Si2

Si1

Si4

Si3

M1 -- M2: 5.4/0.6

M3 -- M6: 2.4/0.6Seq: 2.4/0.6

Sb: 6.0/0.6

S1, 2: 1.8/0.6

Inv1,2 : p-- 4.8/0.6, n-- 1.2/0.6

Seqx: 3.0/0.6

S3, 4: 3.0/0.6

Si1-i4: 4.8/0.6


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4.5 Clock Edge Reassignment

The clock edge reassignment (CERA) circuit for a dual-channel system is

shown in Fig. 4.8. With proper control signals, Spe and Spo pass the rising edges and Sno

and Sne pass the falling edges of the master clock to SHA1 and SHA2, respectively.

When Voddis high, Sno and Spo are on, allowing SHA1 to receive a falling edge from A2

and SHA2 a rising edge from A1. When Veven is high, the reverse occurs. The falling

edge of A1 and the rising edge of A2 are discarded.

Figure 4.8 Clock edge reassignment circuit for a dual-channel system.

The operation of the CERA circuit is further illustrated in Fig. 4.9. The circuit

operates in two pass modes and one block mode. During the block mode, the clock

signals inside SHA1 or SHA2 are stored on the parasitic capacitance at each node. The

clock edge reassignment concept can be easily extended to a multi-channel system as

well.

Spo

CK

Spe

A1

A 2

SHA1 SHA2

Sno Sne

Vodd Veven

CK1

CK1x

CK2

CK2x


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Figure 4.9 Operational diagram of a dual-channel CERA system.

SHA1

CKA1

A 2

CK

Spo

A1

A 2Sno

Vodd= High & Veven= Low

Vodd & Veven= Low

Holding

SHA2

SHA1 SHA2 SHA1 SHA2

Sne

Spe

Vodd= Low & Veven= High

TT

Even

Odd

21 3 2 1

CK1

CK1x(from A1)

CK2

CK2x(from A2)

21 3

Vodd

Veven

CK1

CK1x

CK2

CK2x


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4.6 Control and Decode Circuit

As shown in Fig. 4.10, the control circuit (NAND_FF) senses the outputs of two

adjacent comparators to generate three control signals, two applied to the MUX, and

one to the ROM. The two-input NAND gate performs 1-of-n encoding and its output

drives a D-type flip-flop, which produces the digital output at the falling edge ofCK.

With the assertion of either CKey or CKoy , the control signal is routed to either the even-

channel MUX or the odd-channel MUX, performing interleaving operation in stages 2

to 5.

Figure 4.10 Block diagram of NAND_FF with comparator.

The detailed circuit of NAND_FF is shown in Fig. 4.11. The core is based on a

TSPC flip-flop structure [38]. The dual-input NAND is merged into the input stage of

the D-FF, while the two interleave-control NANDs are combined with the D-FF output

stage. INV3 and INV4 are scaled to drive the heavy capacitive load inside MUXs with

reasonable delay.

To ROM

D1

D2

CK

CKey

CKoy

Oa2+

Oa2-

Odax2-

Odax2+

Odax1+

To MUX

CMP NAND_FF

D Q

Oe2-

Od2

Oo2-


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Figure 4.11 Details of NAND_FF

M3

Oo-

Oe-

D2

D1

CK

CK_2ey

CK_2oy

Inv1

Od

ND

M1 - M3 : 1.8/0.6

Inv1,2 : p- 4.8/0.6; n- 2.4/0.6

M4 - M5 : 3.0/0.6

M6 - M7 : 2.4/0.6

M9 - M12 : 1.8/0.6

M8 : 1.2/0.6

M13 - M14 : 3.6/0.6

Inv3,4 : p- 19.2/0.6; n- 9.6/0.6

ND: p- 4.8/0.6; n- 2.4/0.6

M1

M7

M2 M6 M9

M4

M5M8

M10

M13

M11

M12

M14

Inv3

Inv2 Inv4


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4.7 ROM and Output Stage

The ROM consists of a dynamic digital circuit with a precharging PMOS as

shown in Fig. 4.12.

Figure 4.12 ROM and output stage.

When CKc is low, Mp precharges the output node Dx and Mx is controlled by

Din. When CKc goes high,Mp turns off andMn turns on. The outputDx is then evaluated

and fed to the following pipelined register array and eventually the output driver. The

registers consist of dynamic TSPC D flip-flops.

The output driver is an open-drain NMOS device producing a current of about

6 mA. The current is drawn from an off-chip termination resistor of 100 , generating

Din

CKc

D Q

Dout

ROM

Ro

Mp: 9.0/0.6

Ro: 100

Mx: 2.4/0.6

Mn: 14.4/0.6

Mo: 18/0.6

DxMp

Mn

Mx

MoD Q

PAD


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58

a voltage swing of 600 mV, a value sufficient for driving off-chip ECL buffers. The

small voltage swings allow sharp edges in the output data waveforms even with the

large capacitance due to the traces on the printed-circuit (PC) board.

One dedicated ground pad is used for all of the output drivers to ensure that the

large ground bounce does not disturb the sensitive analog sections.

4.8 Clock Generator

In a high-speed ADC system, the clock generator requires special attention. As

shown in Fig. 4.13, the clock generator contains four building blocks: two divide-by-

two circuits (DIV2a and DIV2b), one divide-by-three circuit (DIV3), and an output

buffer section (BUF).

The 300-MHz differential master clock signals, CKin and CKin, drive DIV2a and

the output flip-flop of DIV2b. DIV2a produces 150-MHz outputs that are applied to

DIV2b

and DIV3. DIV

2bgenerates 75-MHz clocks required for interleaving the

interpolative stages and DIV3 produces 50-MHz clocks used in the triple-channel front-

end SHA.

The BUF section generates CKa1, CKa2, CK_3a, CK_3b, CK_3c for the front-end

SHAs, CK_2ec, CK_2oc, CK_2ey, CK_2oy for the dual-channel interleaving interpolative

stages, and CKand CKc for the comparators and the pipelining registers. The BUF

section is actually laid out in different parts of the chip, in proximity to the related

sections.


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Figure 4.13 Clock generator.

D QD Q

D QD Q

CKin

CKin

D Q

D Qo_2f1

o_2f2+

o_2c2+

ick+

ick

o_2b2+

o_2b2

o_2c1

o_4c+ o_4c

8

CK CK _2ec CK_2oc CK_2ey CK_2oy

o_2b1+

4.8

3.64 4

8 8 4

CKa2 CK_3a CK_3b CK_3cCKa1 CKc

4x16 4x4 4x4 4x16 4x164x1616 8 8816

8 84 4 8 84 4

DIV2aDIV2b

DIV3

BUF

QD QD QD

Q D Q D

QD

QD

3.0

1.2unityINV=

Local BUFs


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60

Figure 4.14 shows the high-speed differential D-type latch used in the two

divide-by-two circuits. With the device dimensions shown here, the latch operates at

clock frequencies as high as 400 MHz.

Figure 4.14 High-speed differential D latch.

4.9 One Slice of First-Stage Signal Path

Figure 4.15 shows the realization of a slice of the signal path in the first stage.

While interpolation by a factor of 2 tolerates large nonlinearity in differential pairs, the

reinterpolation scheme does require tighter linearity. Hence, the differential amplifiers

in the signal path employ resistive degeneration. The actual design is fully differential.

It is also important to note that the converter requires no floating capacitors and

can therefore utilize native metal-sandwich structures in digital CMOS technologies.

CKc

Q

M6

Mn

M4

M5

M3

M2M1

Q

DD

M1 - M6 : 3.0/0.6

Mn: 12/0.6


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Figure 4.15 Realization of a slice of the signal path in the first stage.

The entire ADC is simulated at the transistor level by StarSim (previously called

ADM), a SPICE-like simulator. The result for typical process parameters and at room

temperature is shown in Fig. 4.16.

Vin

Even Channel

Logic

SlideCommand

InterleaveCommand

VDD

Control

Odd Channel


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Figure 4.16 Simulated output of the 8-bit ADC.

0 10 20 30 40 50 60-80

-60

-40

-20

0

Frequency (MHz)

dB

fsamp

= 153.8462 MHz

SNDR = 43.148 dBHD3 = -51.6222 dB

0 20 40 60 80 100 120-1

-0.5

0

0.5

1

Sample (Time)

Volt

fin = 37.2596 MHz ( 31/128 * fsamp)

(a)

(b)


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4.10 Floor Plan And Layout Considerations

The floor plan and layout of the ADC must deal with issues such as: routing of

critical paths, power and ground isolation, noise coupling from the digital sections to

the analog sections, etc. Due to the nature of sliding interpolation, the high-speed digital

control signals must travel through the analog sections. Also, the sub_ADCs in stages

2 to 5 must be embedded with the interpolating stages. These issues underscore the

importance of careful layout to suppress various noise coupling effects.

Figure 4.17 shows the floor plan of the ADC. In order to reduce the wiring

capacitance in the critical path, the front-end building blocks in the first stage (CMP_A,

reference ladder, preamplifiers, MUX, and the distributed sample-and-hold) are folded

into a U shape. The front-end SHA output and the reference ladder are routed between

the comparator bank (CMP_A) and the preamplifier bank. The reference ladder is made

of silicide poly-resistor with a length of two squares (about 8 ) between consecutive

taps. Each preamplifier provides an empty stripe so that the digital control signals from

CMP_A to MUX can run through it without interfering with the analog signal path. The

digital signals have also been shielded on both sides with analog ground along the entire

path. The ROM generates the four corresponding digital bits in the first stage.


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Figure 4.17 Layout floor plan.

The MUX outputs are connected to metal-3 lines running vertically. Each

differential analog output pair is shielded by analog VDD lines on both sides, providing

isolation and forming the sampling capacitor as well. The even and the odd channels

are uniformly distributed within this building block. Amp2 performs reinterpolation

and contains 5 dual-channel sets which sense the outputs of the MUX and subsequently

reinterpolate the new outputs to drive the next stage.

CMP_A

Preamp

MUX &

ROM

16

15

14

13

12

11

9

10

8

7

1

2

3

4

5

6

16

15

14

13

12

11

9

10

8

7

1

2

3

4

5

6

18

17-1

0

16

15

14

13

12

11

9

10

8

7

1

2

3

4

5

6

18

17-1

0

even/odde/o

e/o

e/o

e/oe/o

e/o

e/o

e/o

e/o

e/o

e/o

e/oe/o

e/o

e/o

e/oe/o

e/o

e/o

5 (e)

5 (o)

4 (e)

4 (o)

3 (e)

3 (o)

2 (e)

2 (o)

1 (e)

1 (o)

5 (e)

5 (o)

4 (e)

4 (o)

3 (e)3 (o)

2 (e)

2 (o)

1 (e)

1 (o)

7 (e)

7 (o)

6 (e)

6 (o)

3

2

1

5 (e)

5 (o)

4 (e)

4 (o)

3 (e)3 (o)

2 (e)

2 (o)

1 (e)

1 (o)

7 (e)

7 (o)

6 (e)

6 (o)

DistributedSampling

Amp2

InterpolationAmp

ROM

MUX &

DistributedSampling

CMP_B

ReferenceLadder

SHA

Clock Generator

Stage 2


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A more detailed diagram of the first stage is shown in Fig. 4.18. Note that the

positioning of preamplifiers 1, 2, 3 and 13, 14, 15 creates a U-shaped layout. This

strategy is chosen because preamplifiers 1 and 15 share the same reference voltages,

etc.

The actual sliding/multiplexing mechanism is depicted in more detail for the

lower and upper banks in Fig. 4.19 and Fig. 4.20, respectively. The sliding/interleaving

command reaches a unit cell (in the middle column) in each slice from the left and then

connects to the cells in the adjacent two slices above and below.

Stage 2 consists of reinterpolation and interpolation amplifiers, and another

MUX and distributed sampling circuit. All of these circuits are in differential and dual-

channel form. Only three comparators are required in CMP_B to decide which sections

are needed to provide the zero-crossing information to the following stage. The ROM

creates the two bits based on the results of the comparators. Stages 3 to 5 are identical

to stage 2.

Since all of the switches in the MUX are PMOS devices, a large n-well is used

to accommodate them. With properly-spaced substrate contacts, the n-well isolates the

switches from the noisy common p-substrate.


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Figure 4.18 Detailed circuit arrangement in the first stage.

Cntleven

Vin+Vin

Vref

+Vref

1

2

15

14

3

13

Cntlodd

Cntleven

Cntlodd

Cntleven

Cntlodd

Cntleven

Vo1

(even) (odd)

Vo2

(even) (odd)

Vo3

(even) (odd)

CMP_A Preamps MUXNAND_FF

unit cell


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Figure 4.19 Sliding/multiplexing mechanism of the lower bank.

Vo2

(even) (odd)

Vo3

(even) (odd)

Vo4

(even) (odd)

2

3

1

14

13

15


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Figure 4.20 Sliding/multiplexing mechanism of the upper bank.

Vo2

(even) (odd)

Vo3

(even) (odd)

Vo4

(even) (odd)

14

13

15

2

3

1


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Figure 4.21 Die photo.

Fig. 4.21 shows the die photo. The chip size is 1.5 mm x 1.2 mm with the active

area about 1.2 mm2. The analog differential input signals, Vin+ and Vin

, enter from the

left side of the chip and are shielded with a common VDD in metal 2. Digital outputs

leave the chip from the lower and the right sides of the chip. Three different power lines

SHA

ADC1

Ref

Preamp

ADC2

MUXReinterpolation

Amp

ClockGenerator

InterpolationAmp

Stage 3

Stage 4

Stage 5

Ladder

CKin+ CKin

Vin+

Vin


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70

are used in this layout, one for the analog section, one for the digital section, and one

for the first sub_ADC.

The front-end SHA is placed at the left-top corner and right above the reference

ladder so that its outputs readily reach the preamplifiers and the first sub_ADC. The

high-speed (300-MHz) input clocks, CKin+ and CKin

, and the clock generator are

placed on the top of the chip.

The modularity of the design can be seen in stages 2 to 5. The resuling layout is

quite compact and relatively easy to handle in transistor-level simulations.


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Chapter 5

Experimental Results

5.1 Introduction

In this chapter, the test setup and the experimental results obtained from a

prototype fabricated in a 0.6-m CMOS technology are described. Testing an 8-bit

converter at sampling rates greater than 100 MHz entails many challenges, requiring

great care in the design of the test board and the setup. In order to avoid the parasitics

of typical packages, a chip-on-board assembly is adopted. Since building a single chip-

on-board assembly to test high-speed ADCs is time-consuming and error-prone, a

mother-board-and-daughter-board configuration is used to reduce the work associated

with changing the device under test. The raw digital output data of the ADC is collected

by a logic analyzer and subsequently fed into a personal computer for error correction

and performance analysis. MATLAB is used to characterize the results of both low-


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frequency and dynamic tests. INL and DNL are measured at low input frequencies (still

with a sampling rate of 150 MHz), while SNDR and SFDR are obtained for input

frequencies up to the Nyquist rate.

5.2 Design of Chip-on-Board Assembly

The first version of the test board is made of double-copper-layer PC board.

Shown in Fig. 5.1 the chip (bare die) is mounted in the middle of the central cavity on

the board by conductive epoxy to reduce the ground inductance.

Figure 5.1 Chip-on-board assembly.

CKout

ICK

ICK+

DVdd1

VR_2

BootCntlVR18

Vin+Vin-

AVdd

NB1S

NB1BC

A0 A1 A2 A3 B0 B1 C0 C1 D0D1 E0E1

CVdd

DVdd2

NB1C

NB1B

VR8

NB1A

GND

AVdd2


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Figure 5.2 Zoom-in of the central cavity area.

The analog inputs are fed from the top of the board, while the complementary

clocks are coming from the right with 50- termination resistors. The high-speed

digital outputs are placed on the bottom side of the board. The solid dots are through-

holes which connect the top ground areas to the bottom ground plane. Since there are

no protection diodes on the pads inside the chip, discrete diodes are used for all the

biasing nodes on the board to minimize the probability of damage due to electrostatic

E1

E0

D1D0

C1C0B1B0A3

A2A1

A0

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