EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com XRD9826 16-Bit Linear CIS/CCD Sensor Signal Processor with Serial Control October 2000-1 FEATURES · 16-Bit Resolution · One-channel 6MSPS Pixel Rate · Triple-channel 2MSPS Pixel Rate · 6-Bit Programmable Gain Amplifier · 8-Bit Programmable Offset Adjustment · CIS or CCD Compatibility · Internal Clamp for CIS or CCD AC Coupled Configurations · 3.3V or 5V Operation & I/O Compatibility · Serial Load Control Registers · Low Power CMOS: 200mW-typ · Low Cost 20-Lead Packages · USB Compliant APPLICATIONS · Color and Grayscale Flatbed Scanners · Color and Grayscale Sheetfed Scanners · Multifunction Peripherals · Digital Color Copiers · General Purpose CIS or CCD Imaging · Low Cost Data Acquisition · Simple and Direct Interface to Canon 600 DPI Sensors GENERAL DESCRIPTION The XRD9826 is a complete linear CIS or CCD sensor signal processor on a single monolithic chip. The XRD9826 includes a high speed 16-bit resolution ADC, a 6-bit Programmable Gain Amplifier with gain adjust- ment of 1 to 10, and 8-bit programmable input referred offset calibration range of 800mV. In the CCD configuration the input signal is AC coupled with an external capacitor. An internal clamp sets the black level. In the CIS configuration, the clamp switch can be disabled and the CIS output signal is DC coupled from the CIS sensor to the XRD9826. The CIS signal is level shifted to VRB in order to use the full range of the ADC. In the CIS configuration the input can also be AC coupled similar to the CCD configura- tion. This enables CIS signals with large black levels to be internally clamped to a DC reference equal to the black level. The DC reference is internally subtracted from the input signal. The CIS configuration can also be used in other applications that do not require CDS function, such as low cost data acquisition. Rev. 1.10 ORDERING INFORMATION Package Type Temperature Range Part Number 20-Lead SOIC 0°C to +70°C XRD9826ACD 20-Lead SSOP 0°C to +70°C XRD9826ACU
· Internal Clamp for CIS or CCD AC CoupledConfigurations
· 3.3V or 5V Operation & I/O Compatibility
· Serial Load Control Registers
· Low Power CMOS: 200mW-typ
· Low Cost 20-Lead Packages
· USB Compliant
APPLICATIONS
· Color and Grayscale Flatbed Scanners
· Color and Grayscale Sheetfed Scanners
· Multifunction Peripherals
· Digital Color Copiers
· General Purpose CIS or CCD Imaging
· Low Cost Data Acquisition
· Simple and Direct Interface to Canon 600 DPISensors
GENERAL DESCRIPTION
The XRD9826 is a complete linear CIS or CCD sensorsignal processor on a single monolithic chip. TheXRD9826 includes a high speed 16-bit resolution ADC,a 6-bit Programmable Gain Amplifier with gain adjust-ment of 1 to 10, and 8-bit programmable input referredoffset calibration range of 800mV.
In the CCD configuration the input signal is AC coupledwith an external capacitor. An internal clamp sets theblack level. In the CIS configuration, the clamp switchcan be disabled and the CIS output signal is DCcoupled from the CIS sensor to the XRD9826. The CISsignal is level shifted to VRB in order to use the full
range of the ADC. In the CIS configuration the inputcan also be AC coupled similar to the CCD configura-tion. This enables CIS signals with large black levelsto be internally clamped to a DC reference equal to theblack level. The DC reference is internally subtractedfrom the input signal.
The CIS configuration can also be used in otherapplications that do not require CDS function, such aslow cost data acquisition.
Rev. 1.10
ORDERING INFORMATION
Package Type Temperature Range Part Number
20-Lead SOIC 0°C to +70°C XRD9826ACD
20-Lead SSOP 0°C to +70°C XRD9826ACU
XRD9826
2
Rev. 1.10
Figure 1. Functional Block Diagram
RED
GRN
BLU
VDCEXT
VREF+
DB7:0
DVDD
DGND
AVDD
AGND
ADCCLK
CLAMP
SYNCH
PGA
TIMING&
CONTROL LOGIC
AVDD
6-BIT GAINREGISTERS
16-BITADC
RL
AGND
DATAI/O
PORT
BUFFERVRT
VRB
TripleS/H &
3-1
MUX
8-BIT DAC
16 8
8-BIT OFFSETREGISTERS
6
8
+
_
AGND
VDCREF
DC/AC
INT/EXT_V DCREF
CIS/CCD
G<5:0>
O<7:0>
R G B
R G B
CLP
CLA
MP
PowerDown
PowerDown
VRTCCD
CIS
VBG* CIS REF Circuit
* CIS REF Circuit
DC Reference
Note: * For Canon CIS Sensor
XRD9826
3
Rev. 1.10
AVDD
VREF+XRD9826ACD
20
19
18
17
16
15
14
13
12
RED
GRN
BLU
VDCEXT
AGND
1
2
3
4
5
6
7
8
9
DVDD
DB0
DB1
DB2
DB4
DGND ADCCLK
DB3
10 11
DB5/SCLK
DB6/SDATA
DB7/LD CLAMP
SYNCH
20-Lead SOIC
PIN DESCRIPTION
Pin # Symbol Description1 DVDD Digital VDD (for Output Drivers)2 DB0 Data Output Bit 03 DB1 Data Output Bit 14 DB2 Data Output Bit 25 DB3 Data Output Bit 36 DB4 Data Output Bit 47 DB5/SCLK Data Output Bit 5 & Data Input SCLK8 DB6/SDATA Data Output Bit 6 & Data Input SDATA9 DB7/LD Data Output Bit 7 & LD
10 DGND Digital Ground (for Output Drivers)11 ADCCLK A/D Converter Clock12 CLAMP Clamp and Video Sample Clock13 SYNCH Start of New Line and Serial Data Input Control14 AGND Analog Ground15 VREF+ A/D Positive Reference for Decoupling Cap16 VDCEXT External DC Reference17 BLU Blue Input18 GRN Green Input19 RED Red Input20 AVDD Analog Power Supply
Note 1: The additional ±100 mV of adjustment with respect to the black level input range is needed to compensatefor any additional offset introduced by the XRD9826 Buffer/PGA internally.
Note 2: It is not recommended to operate the part between 3.6V and 4.4V.
Input Leakage Current 100 nACIN Input Capacitance 10 pF
VINPP
AC Input Voltage Range 0 AVDD
-1.4 V CIS AC; INT VDCREF
Config Reg => XXX010XXGain=1 (Note 1)
AC Input Voltage Range 0 DVREF
V CCD AC; INT VDCREF
Config Reg=> XXX011XX
Gain=1 (Note 1)VIN DC Input Voltage Range -0.1 AVDD-1.4 V CIS DC; INT VDCREF
Config Reg => XXX000XXGain=1 (Note 2)
DC Input Voltage Range VDCEXT
-0.1 VDCEXT
+ V CIS DC; EXT VDCREF
DVREF Config Reg=> XXX100XXGain=1 (Note 3)V
DCEXT+DV
REF < AV
DD
VDCEXT
External DC Reference 0.3 AVDD
/2 V CIS DC; EXT VDCREF
Config Reg=> XXX100XX
VINBW Input Bandwidth 3 MHzVIN
CTChannel to Channel Crosstalk -60 -50 dB f
in=3MHz
Internal Clamp Specifications
VCLAMP
Clamp Voltage AGND 50 mV CIS (AC) Config3.5 V
RTV CCD (AC) Config
RINT
Clamp Switch On Resistance 100 150 ΩROFF Clamp Switch Off Resistance 10 MΩ
Note 1: VINPP is the signal swing before the external capacitor tied to the MUX inputs.Note 2: The -0.1V minimum is specified in order to accommodate black level signals lower than the external DC
reference (clamp) voltage.Note 3: The VDCEXT-0.1V minimum is specified in order to accommodate black level signals lower than the external DC
trars Rising ADCCLK to rising 0 SYNCH must rise equal toSYNCH or after ADCCLK, See Figure 18
tclpw CLAMP Pulse Width 30 ns Note 2
Write Timing Specifications
tsclkw SCLK Pulse Width 40 ns
tdz LD Low to SCLK High 20 ns
tds Input Data Set-up Time 20 ns
tdh Input Data Hold Time 0 ns
tdl SCLK High to LD High 50 ns
ADC Digital Output Specifications
tap Aperture Delay 10 ns
tdv Output Data Valid 40 ns
tsa SYNCH to ADCCLK 15 ns 3ch Pixel Md
tlat Latency 8 cycles Config 00, 11
tlat Latency 6 pixels Config 01, 10
Digital Input Specifications
VIH Input High Voltage AVDD-2.5 V
VIL
Input Low Voltage 1 V
IIH
High Voltage Input Current 5 µA
IIL Low Voltage Input Current 5 µA
CIN
Input Capacitance 10 pF
Note 1: System performance is specified for typical digital system timing specifications.
Note 2: The actual minimum ‘tclpw’ is dependent on the external capacitor value, the CIS output impedance.During ‘clamp’ operation, sufficient time needs to be allowed for the external capacitor to charge up to thecorrect operating level. Refer to the description in Theory of Operation, CIS Config.
SR Slew Rate (10% to 90% DVDD) 2 15 ns CL=10pF, DVDD=3.3V
XRD9826
8
Rev. 1.10
THEORY OF OPERATION
CIS Configuration (Contact Image Sensor)
The XRD9826 has two configurations for CIS applica-tions. Each configuration is set by the control registersaccessed through the serial port.
Mode 1. DC Coupled
If the CIS does not have leading or trailing black pixelsas shown in Figure 2, then DC couple the CIS output tothe XRD9826 input.
Optically Shielded
PixelsValid Pixels
Figure 2. Typical Output CIS Mode
Adjust the offset of the CIS (-100 mV to 500 mV) bysetting the internal registers of the XRD9826 to set theblack pixel value when the LEDs of the CIS are off.When the LEDs are on, use the XRD9826 Program-
mable Gain to maximize the ADCs dynamic range.Figure 3, shows a typical application for a CIS with anoffset of -100mV to 500mV.
XRD9826
9
Rev. 1.10
The input is added to VRB before the signal passesthrough the ADC. If the CIS output is zero, then theoutput of the ADC will be zero code. This enables theCIS to be referenced to the bottom ladder referencevoltage to use the full range of the ADC.
Some CIS sensors have an output with an offsetvoltage of greater than 500mV. If the CIS output is
Figure 3. Application with Offset in the Range (-100mv to 500mv)
RL
VRT
VRB
VDD
RED
XRD9826
CIS
MUX
N/CN/C
N/C
beyond the offset range of the XRD9826 (see OffsetControl DAC, Pg. 22) set the internal mode registers toexternal reference. An external reference voltageequal to the value of the CIS offset voltage can beapplied to VDCEXT (Figure 4) in order to meet thedynamic range of the XRD9826. Figure 4, is a diagramof the XRD9826 in the external reference mode for CIS,DC coupled applications.
XRD9826
10
Rev. 1.10
The DC reference voltage applied to VDCEXT does nothave to be accurate. The internal offset DAC voltageis still used in this mode for fine adjustment. VDCEXT
Figure 4. Application with Offset Greater Than (-100mv to 500mv)
RL
VRT
VRB
VDD
RED
XRD9826
DCREFERENCE
C
I
SM
U
X
N/CN/C
VDCEXT
cannot be used as an input from the CIS. Any signalapplied to VDCEXT will be subtracted from the outputsignal of the multiplexer.
XRD9826
11
Rev. 1.10
Figure 5. Typical Application Circuitry CIS DC Coupled Non-Inverted Mode
If the CIS signal has a black reference for the videosignal, an external capacitor C
EXT is used. When
CLAMP (clamp) pin is set high an internal switch allows
one side of the external capacitor to be set to ground.It then is level shifted to correspond to the bottom ladderreference voltage of the ADC (Figure 7).
ADCCLK Events↓ ADC Sample & PGA Start Tracking next Pixel
MSB Data Out↑ LSB Data OutHI ADC Track PGA OutputLO ADC Hold/Convert
Table 1.
CIS Mode Timing -- DC Coupled(CLAMP disabled)
ADCCLK
tckhw tcklw
tckpd
tap tap
Pixel N-1 Pixel N
tdv
Pixel N+1
CIS
tdv
[5:0]
[11:6]
N-8
MSBN-8
LSB
N-7
MSBN-7
LSB
N-6
MSB
N-6
LSBN-5
MSB
N-5LSB
DB
Figure 6. Timing Diagram for Figure 5
XRD9826
13
Rev. 1.10
This value corresponds to the black reference of theimage sensor. When the CLAMP pin is set back to low,the ADC samples the video signal with respect to theblack reference. The typical value for the externalcapacitor is 100pF. This value should be adjustedaccording to the time constant (Tc) needed in aparticular application. The CLAMP pin has an internal150 ohm impedance (R
INT) which is in series with the
external capacitor (CEXT
).
Figure 7. CIS AC Coupled Application
Therefore, Tc =1/RINT
CEXT
If the input to the external capacitor has a sourceimpedance (R
Figure 8. Typical Application Circuitry CIS AC Coupled Non-Inverted
XRD9826
15
Rev. 1.10
CIS Mode Timing -- AC Coupled(CLAMP enabled)
ADCCLK
tckhw tcklw
tckpd
tap tap
Pixel N-1 Pixel N
tdv
Pixel N+1
CIS
tdv
[5:0]
[11:6]
N-8 N-8LSB
N-7 N-7LSB
N-6 N-6LSB
N-5 N-5LSB
CLAMP
tclpw
MSB MSB MSB MSBDB
Figure 9. Timing Diagram for Figure 8.
ADCCLK Events↓ ADC Sample & PGA Start Track of next Pixel
MSB Data Out (8 Upper Bits)↑ LSB Data Out (8 Lower Bits)HI ADC Track PGA Output
LO ADC Hold/Convert
Table 3.
CLAMP EventsHI PGA Tracks VCLAMP & CEXT is Charged to
VBLACK - VCLAMP, which is equal to VBLACK
LO PGA Tracks VINPP
Table 4.
Note: There is an 8 clock latency for the output
XRD9826
16
Rev. 1.10
Internal CIS Reference Circuit (DB 4 = 1)
The XRD9826 has an internal register reserved forinterfacing to the Canon CIS model number CVA-60216K. When this register is selected, the VDCEXT(Pin 16) becomes an output voltage of 1.24 volts. Thisvoltage can be directly connected to the VREF (Pin 5)of the Canon sensor. This reduces the amount of
components needed for biasing the Canon CIS sensor(the external diodes and resistors typically used in thisapplication have been included inside the XRD9826 forthis mode of operation). Below is a typical applicationcircuit using the XRD9826 and the Canon CVA-60216KCIS sensor.
CIS Line-By-Line Rotating Gain and Offset (Configuration DB1 = 1, DB0 = 1)
Line-by-line rotating gain and offset minimizes theamount of write cycles per scan. Pre-loaded values ofgain and offset can be loaded for each color before thefirst line is scanned. Each gain and offset is cycled
through line-by-line so that the gain and offset do nothave to be loaded in between lines. Below is the typicalapplication circuit and timing for this configuration.
XRD9826
18
Rev. 1.10
Figure 12. Timing Diagram for Figure 11.
CIS Rotating Gain and Offset
Line-By-Line (Md 11)
ADCCLK
CIS
SYNCH
GAIN/
OFFSET
LD
Red Pixel Line Scan Grn Pixel Line Scan Blu Pixel Line Scan
Red Gain/Offset Cycle Grn Gain/Offset Cycle Blu Gain/Offset Cycle
Reset Internal Mux Color to Red Channel (LD = 110YYYYYY11)
tsa
tsypw
Note: Y = Previous State
Tri-State (SYNCH = LO)
CCD Configuration (Charge Coupled Device)
Mode 1. AC Coupled
In the CCD configuration of operation, an externalcapacitor needs to be chosen according to the equa-tions below. The typical value for the external capacitoris 100pF. This value should be adjusted according tothe time constant (Tc) needed in a particular applica-tion. The CLAMP pin has an internal 150 ohm imped-ance (R
INT) which is in series with the external capacitor
(CEXT
).
Therefore, Tc =1/RINT
CEXT
If the input to the external capacitor has a loadimpedance (R
EXT), then
Tc=1/(R
INT+R
EXT)C
EXT
When CLAMP (clamp) pin is set high an internal switchallows one side of the external capacitor to be set toVRT (Figure 13). This value corresponds to the blackreference of the CCD. When the CLAMP pin is set backto low, the ADC samples the video signal with respectto the black reference. The difference between theblack reference and the video signal is the actual pixelvalue of the video content. Since this value is refer-enced to the top ladder reference voltage of the ADC azero input signal would yield a full scale output code.Therefore, the output of the conversion is inverted(internally) to correspond to zero scale output code.
XRD9826
19
Rev. 1.10
Area or Linear CCD Applications
Figure 13 is a block diagram for applications with Areaor Linear CCDs (The timing for Area CCDs and B/WCCDs is the same). For Area or Linear CCD applica-tions, a global offset is loaded into the serial port at thebeginning of a line. The gain is set to adjust for thehighest color intensity of the CCD output. Once the
pixel values have been sampled, the gain and offset areadjusted at the beginning of the next line. For example,if there is a line-to-line variation between the blackreference pixels, the offset is adjusted. The gain isalways adjusted for the highest color intensity.
Figure 13. CCD AC Coupled Application
RL
VRT
VRB
VDD
RED
XRD9826
CLAMP
M
U
X
AREA
or
LINEAR
CCDN/CN/CN/C
XRD9826
20
Rev. 1.10
Figure 14. Typical Application Circuitry Single Channel CCD AC Coupled Inverted Mode.
DVDD (3V - 5V)AVDD
VCC (5V - 15V)
DGND
AGND
DIGITALASIC
CCD
N/C
N/C
N/C100PF
0.1u
F
0.1u
F
0.01
uF
0.1u
F
0.01
uF
XRD9826
DVDD1
DB02DB13DB24DB35DB46DB5/SCLK7DB6/SDATA8DB7/LD9
DGND10
ADCCLK11
CLAMP12
SYNCH13
AGND14
VREF+15
VDCEXT16
BLU17
GRN18
RED19
AVDD20
XRD9826
21
Rev. 1.10
tdv tdv
AREA, LINEAR or B/W CCD -- AC Coupled(CLAMP Enabled)
Pixel N-1 Pixel N Pixel N+1
CCDChannel N
ADCCLK
tckpd
taptap
tckhw tcklw
CLAMP
tclpw
N-8MSB
N-8LSB
N-7MSB
N-7LSB
N-6MSB
N-6
LSB[5:0]
[11:6]DB
Figure 15. Timing Diagram for Figure 14.
Triple Channel CCD Application
Figure 6 is a block diagram for pixel-by-pixel applica-tions with triple channel CCDs. During the opticallyshielded section of a pixel, CLAMP must go high tostore the black reference on each capacitor to the input.
The gain and offset is automatically rotated to adjust foreach channel input. The MSBs (8 upper bits) areavailable on the output bus on the falling edge ofADCCLK. The LSBs (8 lower bits) are available on therising edge of ADCCLK.
Typical CCDs have outputs with black references.Therefore, DC Coupled is not recommended for CCDapplications.
Offset Control DAC
The offset DAC is controlled by 8 bits. The offset rangeis 800 mV ranging from -200 mV to +600 mV (when DB5is set to 0) and -400 mV to +400 mV (when DB5 is setto 1). Therefore, the resolution of the 8-Bit offset DACis 3.14 mV. However, the XRD9826 has +/- 100 mVreserved for internal offsets. Therefore, the effectiverange for adjusting for CIS offsets or black reference is600 mV. The offset adjustment is used primarily tocorrect for the difference between the black level of theimage sensor and the bottom ladder reference voltage(VRB) of the ADC. By adjusting the black level tocorrespond to VRB, the entire range of the ADC can beused.
If the offset of the CIS output is greater than 500 mV anexternal reference can be applied to VDCEXT. Theexternal reference can be used to adjust for largeoffsets only when the internal mode is configuredthrough the serial port.
Since the offset DAC adjustment is done before thegain stage, it is gain-dependent. For example, if thegain needs to be changed between lines (red to blue,etc.), the offset is calibrated before the signal passesthrough the PGA.
PGA (Programmable Gain Amplifier) DAC
The gain of the input waveform is controlled by a 6-BitPGA. The PGA is used along with the offset DAC forthe purpose of using the entire range of the ADC. ThePGA has a linear gain from 1 to 10. Figure 19 is a plotof the transfer curve for the PGA gain.
PGA GAIN TRANSFER CURVEGAIN 1 - 10
1
2
3
4
5
6
7
8
9
10
0 10 20 30 40 50 60
CODE
GA
IN
Figure 20. Transfer Curve for the 6-Bit PGA
After the signal is level shifted to correspond with thebottom ladder reference voltage, the system can becalibrated such that a white video pixel can representthe top ladder reference voltage to the ADC. This allowsfor a full scale conversion maximizing the resolution ofthe ADC.
Analog to Digital Converter
The ADC is a 16-bit, 10 MSPS analog-to-digital con-verter for high speed and high accuracy. The ADC usesa subranging architecture to maintain low power con-sumption at high conversion rates. The output of theADC is on an 8-bit databus. The 8-bit databus supports8x8 output data. ADCCLK samples the input on itsfalling edge. After the input is sampled, the MSB (8upper bits) is latched to the output drivers. On the risingedge of the ADCCLK, the LSB (8 lower bits) is latchedto the output drivers. The output needs to bedemultiplexed with external circuitry or a digital ASIC.There is an 8 clock cycle latency (Config 00, 11) or 6pixel count latency (Config 01, 10) for the analog-to-digital converter.
The VRT
and VRB
reference voltages for the ADC aregenerated internally, unless the external V
RT is se-
lected. In the external VRT
mode, the VRT
voltage is setthrough the VREF+ pin. This allows the user to selectthe dynamic range of the ADC.
XRD9826
27
Rev. 1.10
Serial Load Control Registers
The serial load registers are controlled by a three wireserial interface through the bi-directional parallel port toreduce the pin count of this device. When SYNCH is setto high, the output bus is tri-stated and the serialinterface is activated. DB7/LD, DB5/SCLK and DB6/SDATA are the three input signals that control thisprocess. The DB7/LD signal is set low to initiate theloading of the internal registers.
There are internal registers that are accessed via an 11-bit data string. Data is shifted in on the rising edge ofSCLK and loaded to the registers on the rising edge ofLD. The data on pin DB6/SDATA is latched automati-cally after eleven DB5/SCLKs have been counted. Ifeleven clocks are not present on DB5/SCLK before theDB7/LD signal returns high, no data will be loaded intothe internal registers. If more than 11 clocks arepresent on DB5/SCLK, the additional clocks will beignored. The data corresponding to the first elevenDB5/SCLKs will be loaded only.
The first three MSBs choose which internal register willbe selected. The remaining 8 LSBs contain the dataneeded for programming the internal register for aparticular configuration.
Power-Up State of the Internal Registers
The control register settings upon initial power-up arefor CIS, DC Coupled configuration (VRT is set tointernal, Input DC Reference=AGND and the input tothe ADC is selected through the RED channel). Gain isunity and Offset is set to zero. The test modes aredisabled in the power-up state.
EXAR Corporation reserves the right to make changes to the products contained in this publication in order toimprove design, performance or reliability. EXAR Corporation assumes no responsibility for the use of anycircuits described herein, conveys no license under any patent or other right, and makes no representationthat the circuits are free of patent infringement. Charts and schedules contained here in are only for illustra-tion purposes and may vary depending upon a user’s specific application. While the information in this publi-cation has been carefully checked; no responsibility, however, is assumed for in accuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where thefailure or malfunction of the product can reasonably be expected to cause failure of the life support system orto significantly affect its safety or effectiveness. Products are not authorized for use in such applicationsunless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury ordamage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation isadequately protected under the circumstances.
Copyright 2000 EXAR CorporationDatasheet October 2000Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
