16-BIT MCU - USER MANUAL

ST10R163

16-BIT MCU

USER MANUAL

FEBRUARY 1996

1

2

USE IN LIFE SUPPORT DEVICES OR SYSTEMS MUST BE EXPRESSLY AUTHORIZED.

SGS-THOMSON PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORTDEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF SGS-THOMSON Microelectronics.As used herein:

1. Life support devices or systems are those which (a)are intended for surgical implant into the body, or (b)support or sustain life, and whose failure to perform,when properly used in accordance with instructions foruse provided with the product, can be reasonably ex-pected to result in significant injury to the user.

2. A critical component is any component of a life sup-port device or system whose failure to perform can rea-sonably be expected to cause the failure of the lifesupport device or system, or to affect its safety or effec-tiveness.

III

Table of Contents

1 - ARCHITECTURAL OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91.1 BASIC CPU CONCEPTS AND OPTIMIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.2 THE ON-CHIP SYSTEM RESOURCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

1.3 THE ON-CHIP PERIPHERAL BLOCKS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

1.4 THE APPLICATION-SPECIFIC SYNCHRONOUS SERIAL PORT . . . . . . . . . . . . . . . . . . 17

1.5 PROTECTED BITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

2 - MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192.1 INTERNAL RAM AND SFR AREA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.2 EXTERNAL MEMORY SPACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

2.3 CROSSING MEMORY BOUNDARIES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3 - CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273.1 INSTRUCTION PIPELINING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

3.2 BIT-HANDLING AND BIT-PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.3 INSTRUCTION STATE TIMES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

3.4 CPU SPECIAL FUNCTION REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4 - INTERRUPT AND TRAP FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . 534.1 INTERRUPT SYSTEM STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

4.2 OPERATION OF THE PEC CHANNELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

4.3 PRIORITIZATION OF INTERRUPT AND PEC SERVICE REQUESTS . . . . . . . . . . . . . . 64

4.4 SAVING THE STATUS DURING INTERRUPT SERVICE. . . . . . . . . . . . . . . . . . . . . . . . . 66

4.5 SAVING THE STATUS DURING INTERRUPT SERVICE. . . . . . . . . . . . . . . . . . . . . . . . . 67

4.6 INTERRUPT RESPONSE TIMES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

4.7 INTERRUPT RESPONSE TIMES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

4.8 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

4.9 TRAP FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

5 - PARALLEL PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775.1 PORT 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

5.2 PORT 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

5.3 PORT 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

5.4 PORT 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89

5.1 PORT 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

5.5 PORT 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98

5.6 PORT 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100

6 - DEDICATED PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

7 - EXTERNAL BUS INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1077.1 SINGLE CHIP MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108

7.2 EXTERNAL BUS MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108

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Table of Contents

7.3 PROGRAMMABLE BUS CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

7.4 READY CONTROLLED BUS CYCLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

7.5 CONTROLLING THE EXTERNAL BUS CONTROLLER. . . . . . . . . . . . . . . . . . . . . . . . . 120

7.6 EBC IDLE STATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127

7.7 EXTERNAL BUS ARBITRATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

7.8 THE XBUS INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130

8 - GENERAL PURPOSE TIMER UNITS . . . . . . . . . . . . . . . . . . . . . . . . . . 131

8.1 TIMER BLOCK GPT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131

8.2 TIMER BLOCK GPT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145

9 - ASYNCHRONOUS/SYNCHRONOUS SERIAL INTERFACE . . . . . . . . 159

9.1 ASYNCHRONOUS OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

9.2 SYNCHRONOUS OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

9.3 HARDWARE ERROR DETECTION CAPABILITIES . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

9.4 ASC0 BAUD RATE GENERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

9.5 ASC0 INTERRUPT CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168

10 - SYNCHRONOUS SERIAL PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

11 - WATCHDOG TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

12 - SYSTEM RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

12.1 THE ST10R163’S PINS AFTER RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

12.2 RESET OUTPUT PIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194

12.3 WATCHDOG TIMER OPERATION AFTER RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

12.4 RESET VALUES FOR THE ST10R163 REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

12.5 THE INTERNAL RAM AFTER RESET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

12.6 PORTS AND EXTERNAL BUS CONFIGURATION DURING RESET. . . . . . . . . . . . . . . 194

12.7 APPLICATION-SPECIFIC INITIALIZATION ROUTINE. . . . . . . . . . . . . . . . . . . . . . . . . . 195

13 - POWER REDUCTION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

13.1 IDLE MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199

13.2 POWER DOWN MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200

13.3 STATUS OF OUTPUT PINS DURING IDLE AND POWER DOWN MODE . . . . . . . . . . 201

14 - SYSTEM CLOCK GENERATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

14.1 PLL OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203

14.2 OPERATION WITHOUT PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

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Table of Contents

15 - SYSTEM PROGRAMMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20515.1 INSTRUCTIONS PROVIDED AS SUBSETS OF INSTRUCTIONS. . . . . . . . . . . . . . . . . 205

15.2 MULTIPLICATION AND DIVISION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

15.3 BCD CALCULATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207

15.4 STACK OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207

15.5 REGISTER BANKING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .210

15.6 PROCEDURE CALL ENTRY AND EXIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

15.7 TABLE SEARCHING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213

15.8 PERIPHERAL CONTROL AND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

15.9 FLOATING POINT SUPPORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

15.10TRAP/INTERRUPT ENTRY AND EXIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

15.11UNSEPARABLE INSTRUCTION SEQUENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

15.12OVERRIDING THE DPP ADDRESSING MECHANISM. . . . . . . . . . . . . . . . . . . . . . . . . 214

16 - REGISTER SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21716.1 CPU GENERAL PURPOSE REGISTERS (GPRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

16.2 SPECIAL FUNCTION REGISTERS ORDERED BY NAME. . . . . . . . . . . . . . . . . . . . . . . 220

16.3 REGISTERS ORDERED BY ADDRESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

17 - INSTRUCTION SET SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

18 - DEVICE SPECIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

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VI

INTRODUCTION

High Performance 16-Bit CPU With Four-StagePipeline

80 ns minimum instruction cycle time, with mostinstructions executed in 1 cycle

400 ns multiplication (16-bit *16-bit), 800 nsdivision (32-bit/16-bit)

Multiple high bandwidth internal data buses

Register based design with multiple variableregister banks

Single cycle context switching support

16 MBytes linear address space for code anddata (von Neumann architecture)

System stack cache support with automaticstack overflow/underflow detection

Control Oriented Instruction Set with HighEfficiency

Bit, byte, and word data types

Flexible and efficient addressing modes for highcode density

Enhanced boolean bit manipulation with directaddressability of 4 Kbitsfor peripheral control and user defined flags

Hardware traps to identify exception conditionsduring runtime

HLL support for semaphore operations andefficient data access

Integrated On-chip Memory

2 KByte internal RAM for variables, registerbanks, system stack and code

External Bus Interface

Multiplexed or non-multiplexed busconfigurations

Segmentation capability and chip select signalgeneration

8-bit or 16-bit data bus

Programmable Bus configuration for fiveprogrammable address areas

16-Priority-Level Interrupt System

28 interrupt nodes with separate interruptvectors

200/400 ns typical/maximum interrupt latency incase of internal program execution

Fast external interrupts

8-Channel Peripheral Event Controller (PEC)

Interrupt driven single cycle data transfer Transfer count option (standard CPU interrupt

after a programmablenumber of PEC transfers)

Eliminates overhead of saving and restoringsystem state for interrupt requests

Intelligent On-chip Peripheral Subsystems

2 Multifunctional General Purpose Timer UnitsGPT1: three 16-bit timers/ counters, 320 nsmaximum resolutionGPT2: two 16-bit timers/counters, 160 nsmaximum resolution

Asynchronous/Synchronous Serial Channel(USART)with baud rate generator, parity, framing, andoverrun error detection

High Speed Synchronous Serial Channelprogrammable data length and shift direction

Watchdog Timer with programmable timeintervals

Bootstrap Loader for flexible systeminitialization

77 IO Lines With Individual Bit Addressability

Tri-stated in input mode Push/pull or open drain output mode

Different Temperature Ranges

0 to +70 °C, –40 to +85 °C

Multifunctional CMOS Process

Low Power CMOS Technology, including powersaving Idle and Power Down modes

100-Pin Plastic Quad Flat Pack (PQFP)Package

EIAJ standard, 0.65 mm (25.6 mil) lead spacing,surface mount technology

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VII

FEATURES

Complete Development Support

A variety of software and hardware developmenttools for the SGS-THOMSON family of 16-bitmicrocontrollers is available from experiencedinternational tool suppliers. The high quality andreliability of these tools is already proven in manyapplications and by many users. The toolenvironment for the SGS-THOMSON 16-bitmicrocontrollers includes the following tools:

Compilers (C, MODULA2, FORTH)

Macro-Assemblers, Linkers, Locaters, LibraryManagers, Format-Converters

Architectural Simulators

HLL debuggers

Real-Time operating systems

VHDL chip models

In-Circuit Emulators (based on bondout orstandard chips)

Plug-In emulators

Emulation and Clip-Over adapters, productionsockets

Logic Analyzer disassemblers

Evaluation Boards with monitor programs

Industrial boards (also for CAN, FUZZY,PROFIBUS, FORTH applications)

Network driver software (CAN, PROFIBUS)

Abbreviations

The following acronyms and termini are usedwithin this document:

ALE . . Address Latch Enable

ALU . . Arithmetic and Logic Unit

ASC . . Asynchronous/synchronous SerialController

CAN . . . Controller Area Network (License Bosch)

CISC . Complex Instruction Set Computing

CMOS Complementary Metal Oxide Silicon

CPU . . Central Processing Unit

EBC . . External Bus Controller

ESFR . Extended Special Function Register

Flash . Non-volatile memory that may beelectrically erased

GPR. . General Purpose Register

GPT . . General Purpose Timer unit

HLL . . High Level Language

IO . . . . Input / Output

PEC . . Peripheral Event Controller

PLA . . Programmable Logic Array

RAM. . Random Access Memory

RISC . Reduced Instruction Set Computing

ROM. . Read Only Memory

SFR . . Special Function Register

SSC . . Synchronous Serial Controller

XBUS . . Internal representation of the External Bus

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VIII

INTRODUCTION

Notes :

8

February 1996 1/10

This is advance information from SGS-THOMSON.Details aresubject tochange without notice.

ST10R163User Manual

1 - ARCHITECTURAL OVERVIEW

The architecture of the ST10R163 combines theadvantages of both RISC and CISC processors ina very well-balanced way. The sum of the featureswhich are combined result in a high performancemicrocontroller, which is the right choice not onlyfor today’s applications, but also for future engi-neering challenges. The ST10R163 not only inte-grates a powerful CPU core and a set of peripher-

al units into one chip, but also connects the unitsin a very efficient way. One of the four buses usedconcurrently on the ST10R163 is the XBUS, an in-ternal representation of the external bus interface.This bus provides a standardized method of inte-grating application-specific peripherals to producederivates of the standard ST10R163.

Figure 1-1. ST10R163 Functional Block Diagram

VR02078B

OSC WDTInterrupt Controller

P1 P3P4 P6 P2

PEC

SSP

RAMAreaROM Internal

CoreCPU

GPT1 P5GPT2P0 ASCBUS CTL

XBUS-Module XBUS-Module

PLL

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1 - ARCHITECTURAL OVERVIEW (ST10R163)

1.1 BASIC CPU CONCEPTS AND OPTIMIZATION

The main core of the CPU consists of a 4-stage in-struction pipeline, a 16-bit arithmetic and logic unit(ALU) and dedicated SFRs. Additional hardwarehas been spent for a separate multiply and divideunit a bit-mask generator and a barrel shifter.

To meet the demand for greater performance andflexibility, a number of areas has been optimizedin the processor core. Functional blocks in theCPU core are controlled by signals from the in-struction decode logic. These are summarized be-low, and described in detail in the following sec-tions:

1) High Instruction Bandwidth / Fast Execution2) High Function 8-bit and 16-bit Arithmetic and

Logic Unit

3) Extended Bit Processing and Peripheral Con-trol

4) High Performance Branch-, Call-, and LoopProcessing

5) Consistent and Optimized Instruction Formats6) Programmable Multiple Priority Interrupt Struc-

ture

Figure 1-2. CPU Block Diagram

VR02080B

CPU

SPSTKOVSTKUN

Instr.Reg.Instr.Ptr.Exec.Unit

4-StagePipeline

MDH

MDL

PSWSYSCON Context Ptr.

Mul/Div-HWGen

-

R15

R0

General

Purpose

Registers

Bit-Mask

Barrel Shifter

ALU

(16-bit)

Data PagePtr. CodeSeg.Ptr.

RAM

R15

R0

ROM

16

16

32

BUSCON 0BUSCON 1BUSCON 2BUSCON 3BUSCON 4 ADDRSEL 4

ADDRSEL 3ADDRSEL 2ADDRSEL 1

1 KByte

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BASIC CPU CONCEPTS AND OPTIMIZATION (Cont’d)

Hiigh Instruction Bandwidth / Fast ExecutionBased on the hardware provisions, most of theST10R163’s instructions can be exected in justone machine cycle, which requires 100 ns at 20MHz CPU clock (resp. 80 ns at 25 MHz CPUclock). For example, shift and rotate instructionsare always processed within one machine cycle,independent of the number of bits to be shifted.Branch-, multiply- and divide instructions normallytake more than one machine cycle. These instruc-tions, however, have also been optimized. For ex-ample, branch instructions only require an addi-tional machine cycle, when a branch is taken, andmost branches taken in loops require no additionalmachine cycles at all, due to the ‘Jump Cache’.A 32-bit / 16-bit division takes 1µs (resp. 0.8 µs),a 16-bit * 16-bit multiplication takes 0.5µs (resp.0.4 µs) at 20 MHz (resp. 25 MHz) CPU clock.The instruction cycle time has been dramaticallyreduced through the use of instruction pipelining.This technique allows the core CPU to processportions of multiple sequential instruction stagesin parallel. The following four stage pipeline pro-vides the optimum balancing for the CPU core:FETCH: In this stage, an instruction is fetchedfrom the internal ROM or RAM or from the externalmemory, based on the current IP value.DECODE: In this stage, the previously fetched in-struction is decoded and the required operandsare fetched.EXECUTE: In this stage, the specified operation isperformed on the previously fetched operands.WRITE BACK: In this stage, the result is written tothe specified location.If this technique were not used, each instructionwould require four machine cycles. This increasedperformance allows a greater number of tasks andinterrupts to be processed.

Instruction DecoderInstruction decoding is primarily generated fromPLA outputs based on the selected opcode. Nomicrocode is used and each pipeline stage re-ceives control signals staged in control registersfrom the decode stage PLAs. Pipeline holds areprimarily caused by wait states for external mem-ory accesses and cause the holding of signals inthe control registers. Multiple-cycle instructionsare performed through instruction injection andsimple internal state machines which modify re-quired control signals.High Function 8-bit and 16-bit Arithmetic and Log-ic UnitAll standard arithmetic and logical operations areperformed in a 16-bit ALU. In addition, for byte op-

erations, signals are provided from bits six andseven of the ALU result to correctly set the condi-tion flags. Multiple precision arithmetic is providedthrough a ’CARRY-IN’ signal to the ALU from pre-viously calculated portions of the desired opera-tion. Most internal execution blocks have been op-timized to perform operations on either 8-bit or 16-bit quantities. Once the pipeline has been filled,one instruction is completed per machine cycle,except for multiply and divide. An advanced Boothalgorithm has been incorporated to allow four bitsto be multiplied and two bits to be divided per ma-chine cycle. Thus, these operations use two cou-pled 16-bit registers, MDL and MDH, and requirefour and nine machine cycles, respectively, to per-form a 16-bit by 16-bit (or 32-bit by 16-bit) calcula-tion plus one machine cycle to setup and adjustthe operands and the result. Even these longermultiply and divide instructions can be interruptedduring their execution to allow for very fast inter-rupt response. Instructions have also been provid-ed to allow byte packing in memory while provid-ing sign extension of bytes for word wide arithme-tic operations. The internal bus structure also al-lows transfers of bytes or words to or from periph-erals based on the peripheral requirements.

A set of consistent flags is automatically updatedin the PSW after each arithmetic, logical, shift, ormovement operation. These flags allow branchingon specific conditions. Support for both signedand unsigned arithmetic is provided through user-specifiable branch tests. These flags are also pre-served automatically by the CPU upon entry intoan interrupt or trap routine.All targets for branch calculations are also com-puted in the central ALU.

A 16-bit barrel shifter provides multiple bit shifts ina single cycle. Rotates and arithmetic shifts arealso supported.

Extended Bit Processing and PeripheralControl

A large number of instructions has been dedicatedto bit processing. These instructions provide effi-cient control and testing of peripherals while en-hancing data manipulation. Unlike other microcon-trollers, these instructions provide direct access totwo operands in the bit-addressable space withoutrequiring to move them into temporary flags.

The same logical instructions available for wordsand bytes are also supported for bits. This allowsthe user to compare and modify a control bit for aperipheral in one instruction. Multiple bit shift in-structions have been included to avoid long in-struction streams of single bit shift operations.These are also performed in a single machine cy-cle.

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n addition, bit field instructions have been provid-ed, which allow the modification of multiple bitsfrom one operand in a single instruction.

High Performance Branch-, Call-, and LoopProcessing

Due to the high percentage of branching in con-troller applications, branch instructions have beenoptimized to require one extra machine cycle onlywhen a branch is taken. This is implemented byprecalculating the target address while decodingthe instruction. To decrease loop execution over-head, three enhancements have been provided:

• The first solution provides single cycle branchexecution after the first iteration of a loop. Thus,only one machine cycle is lost during the execu-tion of the entire loop. In loops which fall throughupon completion, no machine cycles are lost whenexiting the loop. No special instructions are re-quired to perform loops, and loops are automati-cally detected during execution of branch instruc-tions.

• The second loop enhancement allows the detec-tion of the end of a table and avoids the use of twocompare instructions embedded in loops. Onesimply places the lowest negative number at theend of the specific table, and specifies branching ifneither this value nor the compared value havebeen found. Otherwise the loop is terminated if ei-ther condition has been met. The terminating con-dition can then be tested.

• The third loop enhancement provides a moreflexible solution than the Decrement and Skip onZero instruction which is found in other microcon-trollers. Through the use of Compare and Incre-ment or Decrement instructions, the user canmake comparisons to any value. This allows loopcounters to cover any range. This is particularlyadvantageous in table searching.

Saving of system state is automatically performedon the internal system stack avoiding the use of in-structions to preserve state upon entry and exit ofinterrupt or trap routines. Call instructions pushthe value of the IP on the system stack, and re-quire the same execution time as branch instruc-tions.

Instructions have also been provided to supportindirect branch and call instructions. This supportsimplementation of multiple CASE statementbranching in assembler macros and high level lan-guages.

Consistent and Optimized Instruction Formats

To obtain optimum performance in a pipelined de-sign, an instruction set has been designed which

incorporates concepts from Reduced InstructionSet Computing (RISC). These concepts primarilyallow fast decoding of the instructions and oper-ands while reducing pipeline holds. These con-cepts, however, do not preclude the use of com-plex instructions, which are required by microcon-troller users. The following goals were used to de-sign the instruction set:

1) Provide powerful instructions to perform opera-tions which currently require sequences ofinstructions and are frequently used. Avoidtransfer into and out of temporary registerssuch as accumulators and carry bits. Performtasks in parallel such as saving state uponentry into interrupt routines or subroutines.

2) Avoid complex encoding schemes by placingoperands in consistent fields for each instruc-tion. Also avoid complex addressing modeswhich are not frequently used. This decreasesthe instruction decode time while also simplify-ing the development of compilers and assem-blers.

3) Provide most frequently used instructions withone-word instruction formats. All other instruc-tions are placed into two-word formats. Thisallows all instructions to be placed on wordboundaries, which alleviates the need for com-plex alignment hardware. It also has the benefitof increasing the range for relative branchinginstructions.

The high performance offered by the hardware im-plementation of the CPU can efficiently be utilizedby a programmer via the highly functionalST10R163 instruction set which includes the fol-lowing instruction classes:

• Arithmetic Instructions• Logical Instructions• Boolean Bit Manipulation Instructions• Compare and Loop Control Instructions• Shift and Rotate Instructions• Prioritize Instruction• Data Movement Instructions• System Stack Instructions• Jump and Call Instructions• Return Instructions• System Control Instructions• Miscellaneous Instructions

Possible operand types are bits, bytes and words.Specific instruction support the conversion (exten-sion) of bytes to words. A variety of direct, indirector immediate addressing modes are provided tospecify the required operands.

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Programmable Multiple Priority InterruptSystemThe following enhancements have been includedto allow processing of a large number of interruptsources:1) Peripheral Event Controller (PEC): This proc-

essor is used to off-load many interruptrequests from the CPU. It avoids the overheadof entering and exiting interrupt or trap routinesby performing single-cycle interrupt-drivenbyte or word data transfers between any twolocations in segment 0 with an optional incre-ment of either the PEC source or the destina-tion pointer. Just one cycle is ’stolen’ from thecurrent CPU activity to perform a PEC service.

2) Multiple Priority Interrupt Controller: This con-troller allows all interrupts to be placed at anyspecified priority. Interrupts may also begrouped, which provides the user with the abil-ity to prevent similar priority tasks from inter-rupting each other. For each of the possibleinterrupt sources there is a separate controlregister, which contains an interrupt requestflag, an interrupt enable flag and an interruptpriority bitfield. Once having been accepted bythe CPU, an interrupt service can only be inter-rupted by a higher prioritized service request.For standard interrupt processing, each of thepossible interrupt sources has a dedicated vec-tor location.

3) Multiple Register Banks: This feature allows theuser to specify up to sixteen general purposeregisters located anywhere in the internal RAM.A single one-machine-cycle instruction allowsto switch register banks from one task toanother.

4) Interruptable Multiple Cycle Instructions:Reduced interrupt latency is provided by allow-ing multiple-cycle instructions (multiply, divide)to be interruptable.

With an interrupt response time within a rangefrom just 250 ns to 500 ns at 20 MHz CPU clock(resp. 200 ns to 400 ns at 25 MHz CPU clock) (incase of maximum speed program execution), theST10R163 is capable of reacting very fast on non-deterministic events.Its fast external interrupt inputs are sampled every50 ns at 20 MHz CPU clock (resp. 40 ns at 25 MHzCPU clock) and allow to recognize even very shortexternal signals.The ST10R163 also provides an excellent mecha-nism to identify and to process exceptions or errorconditions that arise during run-time, ’HardwareTraps’. Hardware traps cause an immediate non-

maskable system reaction which is similiar to astandard interrupt service (branching to a dedicat-ed vector table location). The occurrence of ahardware trap is additionally signified by an indi-vidual bit in the trap flag register (TFR). Except foranother higher prioritized trap service being inprogress, a hardware trap will interrupt any currentprogram execution. In turn, hardware trap servic-es can normally not be interrupted by standard orPEC interrupts.

Software interrupts are supported by means of the’TRAP’ instruction in combination with an individu-al trap (interrupt) number.

1.2 THE ON-CHIP SYSTEM RESOURCES

The ST10R163 controllers provide a number ofpowerful system resources designed around theCPU. The combination of CPU and these resourc-es results in the high performance of the membersof this controller family.

Peripheral Event Controller (PEC) andInterrupt Control

The Peripheral Event Controller allows to respondto an interrupt request with a single data transfer(word or byte) which only consumes one instruc-tion cycle and does not require to save and restorethe machine status. Each interrupt source is prior-itized every machine cycle in the interrupt controlblock. If PEC service is selected, a PEC transfer isstarted. If CPU interrupt service is requested, thecurrent CPU priority level stored in the PSW regis-ter is tested to determine whether a higher priorityinterrupt is currently being serviced. When an in-terrupt is acknowledged, the current state of themachine is saved on the internal system stack andthe CPU branches to the system specific vectorfor the peripheral.

The PEC contains a set of SFRs which store thecount value and control bits for eight data transferchannels. In addition, the PEC uses a dedicatedarea of RAM which contains the source and desti-nation addresses. The PEC is controlled similar toany other peripheral through SFRs containing thedesired configuration of each channel.

An individual PEC transfer counter is implicitlydecremented for each PEC service except whenperforming in the continuous transfer mode. Whenthis counter reaches zero, a standard interrupt isperformed to the vector location related to the cor-responding source. PEC services are very wellsuited, for example, to move register contentsto/from a memory table. The ST10R163 has 8PEC channels each of which offers such fast inter-rupt-driven data transfer capabilities.

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THE ON-CHIP SYSTEM RESOURCES(Cont’d)

Memory Areas

The memory space of the ST10R163 is configuredin a Von Neumann architecture which means thatcode memory, data memory, registers and IOports are organized within the same linear ad-dress space which covers up to 16 MBytes. Theentire memory space can be accessed bytewiseor wordwise. Particular portions of the on-chipmemory have additionally been made directly bitaddressable.

A 1 KByte 16-bit wide internal RAM providesfast access to General Purpose Registers(GPRs), user data (variables) and system stack.The internal RAM may also be used for code. Aunique decoding scheme provides flexible userregister banks in the internal memory while opti-mizing the remaining RAM for user data.

The CPU disposes of an actual register contextconsisting of up to 16 wordwide and/or bytewideGPRs, which are physically located within the on-chip RAM area. A Context Pointer (CP) registerdetermines the base address of the active registerbank to be accessed by the CPU at a time. Thenumber of register banks is only restricted by theavailable internal RAM space. For easy parameterpassing, a register bank may overlap others.

A system stack of up to 512 words is provided as astorage for temporary data. The system stack isalso located within the on-chip RAM area, and it isaccessed by the CPU via the stack pointer (SP)register. Two separate SFRs, STKOV andSTKUN, are implicitly compared against the stackpointer value upon each stack access for the de-tection of a stack overflow or underflow.

Hardware detection of the selected memory spaceis placed at the internal memory decoders and al-lows the user to specify any address directly or in-directly and obtain the desired data without usingtemporary registers or special instructions.

For Special Function Registers 1024 Bytes ofthe address space are reserved. The standardSpecial Function Register area (SFR) uses 512bytes, while the Extended Special Function Regis-ter area (ESFR) uses the other 512 bytes.(E)SFRs are wordwide registers which are usedfor controlling and monitoring functions of the dif-ferent on-chip units. Unused (E)SFR addressesare reserved for future members of the ST10R163family with enhanced functionality.

External Bus Interface

In order to meet the needs of designs where morememory is required than is provided on chip, up to16 MBytes of external RAM and/or ROM can beconnected to the microcontroller via its externalbus interface. The integrated External Bus Con-troller (EBC) allows to access external memoryand/or peripheral resources in a very flexible way.For up to five address areas the bus mode (multi-plexed / demultiplexed), the data bus width (8-bit /16-bit) and even the length of a bus cycle (wait-states, signal delays) can be selected independ-ently. This allows to access a variety of memoryand peripheral components directly and with max-imum efficiency. The EBC can control external ac-cesses in one of the following four different exter-nal access modes:

– 16-/18-/20-/24-bit Addresses, 16-bit Data, de-multiplexed

– 16-/18-/20-/24-bit Addresses, 8-bit Data, demul-tiplexed

– 16-/18-/20-/24-bit Addresses, 16-bit Data, Multi-plexed

– 16-/18-/20-/24-bit Addresses, 8-bit Data, Multi-plexed

The demultiplexed bus modes use PORT1 for ad-dresses and PORT0 for data input/output. Themultiplexed bus modes use PORT0 for both ad-dresses and data input/output. All modes usePort 4 for the upper address lines (A16...) if select-ed.

Important timing characteristics of the externalbus interface (waitstates, ALE length andRead/Write Delay) have been made programma-ble to allow the user the adaption of a wide rangeof different types of memories and/or peripherals.Access to very slow memories or peripherals issupported via a particular ’Ready’ function.

For applications which require less than 64KBytes of address space, a non-segmented mem-ory model can be selected, where all locations canbe addressed by 16 bits, and thus Port 4 is notneeded as an output for the upper address bits(A23/A19/A17...A16), as is the case when usingthe segmented memory model.

The on-chip XBUS is an internal representationof the external bus and allows to access integrat-ed application-specific peripherals/modules in thesame way as external components. It provides adefined interface for these customized peripher-als.

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THE ON-CHIP SYSTEM RESOURCES(Cont’d)

Clock Generator

The on-chip clock generator includes a PLL(Phase Lock Loop) circuit that allows to operatethe ST10R163 on a variety of frequency externalclock while still providing maximum performances.The PLL multiplies the external clock frequency bya programmable factor of 1.5, 2, 2.5, 3, 4 or 5. ThePLL also provides fail safe mechanisms which al-low to detect frequency deviations and to performemergency actions in case of an external clockfailure. The PLL may also be disabled, in whichcase the ST10R163 will directly run on the exter-nal input clock divided by 2 or not. The clock gen-erator provides a CPU clock signal that controls allactivities of the controller hardware.This internalclock signal is also referred to as “CPU clock”.Two separated clock signals are generated for theCPU itself and the peripheral part of the chip.While the CPU clock is stopped during waitstatesor during the idle mode, the peripheral clock keepsrunning. Both clocks are switched off, when thepower down mode is entered.

1.3 THE ON-CHIP PERIPHERAL BLOCKS

The ST10R163 family clearly separates peripher-als from the core. This structure permits the maxi-mum number of operations to be performed in par-allel and allows peripherals to be added or re-moved from family members without modificationsto the core. Each functional block processes dataindependently and communicates informationover common buses. Peripherals are controlled bydata written to the respective Special FunctionRegisters (SFRs). These SFRs are located eitherwithin the standard SFR area(00’FE00h...00’FFFFh) or within the extendedESFR area (00’F000h...00’F1FFh).

These built in peripherals either allow the CPU tointerface with the external world, or provide func-tions on-chip that otherwise were to be added ex-ternally in the respective system.

The ST10R163 peripherals are:

– Two General Purpose Timer Blocks (GPT1 andGPT2)

– Two Serial Interfaces (ASC0 and SSC)

– A Watchdog Timer

– Seven IO ports with a total of 77 IO lines

– An integrated application-specific SynchronousSerial Port (X-peripheral number 0)

Each peripheral also contains a set of SpecialFunction Registers (SFRs), which control thefunctionality of the peripheral and temporarilystore intermediate data results. Each peripheralhas an associated set of status flags. Individuallyselected clock signals are generated for each pe-ripheral from binary multiples of the CPU clock.

Peripheral Interfaces

The on-chip peripherals generally have two differ-ent types of interfaces, an interface to the CPUand an interface to external hardware. Communi-cation between CPU and peripherals is performedthrough Special Function Registers (SFRs) andinterrupts. The SFRs serve as control/status anddata registers for the peripherals. Interrupt re-quests are generated by the peripherals based onspecific events which occur during their operation(eg. operation complete, error, etc.).

For interfacing with external hardware, specificpins of the parallel ports are used, when an inputor output function has been selected for a periph-eral. During this time, the port pins are controlledby the peripheral (when used as outputs) or by theexternal hardware which controls the peripheral(when used as inputs). This is called the ’alternate(input or output) function’ of a port pin, in contrastto its function as a general purpose IO pin.

Peripheral Timing

Internal operation of CPU and peripherals isbased on the CPU clock (fCPU). The on-chip oscil-lator derives the CPU clock from the crystal orfrom the external clock signal. The clock signalwhich is gated to the peripherals is independentfrom the clock signal which feeds the CPU. DuringIdle mode the CPU’s clock is stopped while theperipherals continue their operation. PeripheralSFRs may be accessed by the CPU once perstate. When an SFR is written to by software in thesame state where it is also to be modified by theperipheral, the software write operation has priori-ty. Further details on peripheral timing are includ-ed in the specific sections about each peripheral.

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THE ON-CHIP PERIPHERAL BLOCKS (Cont’d)

Programming Hints

Access to SFRsAll SFRs reside in data page 3 of the memoryspace. The following addressing mechanisms al-low to access the SFRs:

– indirect or direct addressing with16-bit (mem)addresses it must be guaranteed that the useddata page pointer (DPP0...DPP3) selects datapage 3.

– accesses via the Peripheral Event Controller(PEC) use the SRCPx and DSTPx pointers in-stead of the data page pointers.

– short 8-bit (reg) addresses to the standardSFR area do not use the data page pointers butdirectly access the registers within this 512 Bytearea.

– short 8-bit (reg) addresses to the extendedESFR area require switching to the 512 Byte ex-tended SFR area. This is done via the EXTen-sion instructions EXTR, EXTP(R), EXTS(R).

Byte write operations to word wide SFRs via in-direct or direct 16-bit (mem) addressing or bytetransfers via the PEC force zeros in the non-ad-dressed byte. Byte write operations via short 8-bit(reg) addressing can only access the low byte ofan SFR and force zeros in the high byte. It istherefore recommended, to use the bit field in-structions (BFLDL and BFLDH) to write to anynumber of bits in either byte of an SFR without dis-turbing the non-addressed byte and the unselect-ed bits.

Reserved Bits

Some of the bits which are contained in theST10R163’s SFRs are marked as ’Reserved’.User software should never write ’1’s to reservedbits. These bits are currently not implemented andmay be used in future products to invoke newfunctions. In this case, the active state for thesefunctions will be ’1’, and the inactive state will be’0’. Therefore writing only ‘0’s to reserved loca-tions provides portability of the current software tofuture devices. Read accesses to reserved bits re-turn ‘0’s.

Parallel Ports

The ST10R163 provides up to 77 IO lines whichare organized into six input/output ports and oneinput port. All port lines are bit-addressable, andall input/output lines are individually (bit-wise) pro-

grammable as inputs or outputs via direction reg-isters. The IO ports are true bidirectional portswhich are switched to high impedance state whenconfigured as inputs. The output drivers of threeIO ports can be configured (pin by pin) forpush/pull operation or open-drain operation viacontrol registers. During the internal reset, all portpins are configured as inputs.

All port lines have programmable alternate inputor output functions associated with them. PORT0and PORT1 may be used as address and datalines when accessing external memory, whilePort 4 outputs the additional segment address bitsA23/19/17...A16 in systems where segmentationis used to access more than 64 KBytes of memo-ry. Port 6 provides optional bus arbitration signals(BREQ, HLDA, HOLD) and chip select signals.Port 2 accepts the fast external interrupt inputs.Port 3 includes alternate functions of timers, serialinterfaces, the optional bus control signal BHEand the system clock output (CLKOUT). Port 5 isused for timer control signals. All port lines that arenot used for these alternate functions may beused as general purpose IO lines.

Serial Channels

Serial communication with other microcontrollers,processors, terminals or external peripheral com-ponents is provided by two serial interfaces withdifferent functionality, an Asynchronous/Synchro-nous Serial Channel (ASC0).

They support full-duplex asynchronous communi-cation at up to 625 KBaud and half-duplex syn-chronous communication at up to 5 MBaud (2.5MBaud on the ASC0) @ 20 MHz CPU clock. TheSSC may be configured so it interfaces with serial-ly linked peripheral components.

Two dedicated baud rate generators allow to setup all standard baud rates without oscillator tun-ing. For transmission, reception and error han-dling 4 separate interrupt vectors are provided onchannel ASC0.

In asynchronous mode, 8- or 9-bit data frames aretransmitted or received, preceded by a start bitand terminated by one or two stop bits. For multi-processor communication, a mechanism to distin-guish address from data bytes has been included(8-bit data plus wake up bit mode).In synchronous mode, the ASC0 transmits or re-ceives bytes (8 bits) synchronously to a shift clockwhich is generated by the ASC0.

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THE ON-CHIP PERIPHERAL BLOCKS (Cont’d)

General Purpose Timer (GPT) Unit

The GPT units represent a very flexible multifunc-tional timer/counter structure which may be usedfor many different time related tasks such as eventtiming and counting, pulse width and duty cyclemeasurements, pulse generation, or pulse multi-plication.

The five 16-bit timers are organized in two sepa-rate modules, GPT1 and GPT2. Each timer ineach module may operate independently in anumber of different modes, or may be concatenat-ed with another timer of the same module.

Each timer can be configured individually for oneof three basic modes of operation, which are Tim-er, Gated Timer, and Count er Mode. In TimerMode the input clock for a timer is derived from theinternal CPU clock divided by a programmableprescaler, while Counter Mode allows a timer tobe clocked in reference to external events (via Tx-IN).Pulse width or duty cycle measurement is support-ed in Gated Timer Mode where the operation of atimer is controlled by the ‘gate’ level on its externalinput pin TxIN.

The count direction (up/down) for each timer isprogrammable by software or may additionally bealtered dynamically by an external signal (TxEUD)to facilitate eg. position tracking.

The core timers T3 and T6 have output togglelatches (TxOTL) which change their state on eachtimer over-flow/underflow. The state of theselatches may be output on port pins (TxOUT) ormay be used internally to concatenate the coretimers with the respective auxiliary timers resultingin 32/33-bit timers/counters for measuring longtime periods with high resolution.

Various reload or capture functions can be select-ed to reload timers or capture a timer’s contentstriggered by an external signal or a selectabletransition of toggle latch TxOTL.

The maximum resolution of the timers in moduleGPT1 is 400 ns (@ 20 MHz CPU clock). With itsmaximum resolution of 200 ns (@ 20 MHz CPUclock) the GPT2 timers provide precise event con-trol and time measurement.

Watchdog Timer

The Watchdog Timer represents one of the fail-safe mechanisms which have been implemented

to prevent the controller from malfunctioning forlonger periods of time.

The Watchdog Timer is always enabled after a re-set of the chip, and can only be disabled in thetime interval until the EINIT (end of initialization)instruction has been executed. Thus, the chip’sstart-up procedure is always monitored. The soft-ware has to be designed to service the WatchdogTimer before it overflows. If, due to hardware orsoftware related failures, the software fails to doso, the Watchdog Timer overflows and generatesan internal hardware reset and pulls theRSTOUTpin low in order to allow external hardware compo-nents to reset.

The Watchdog Timer is a 16-bit timer, clockedwith the CPU clock divided either by 2 or by 128.The high byte of the Watchdog Timer register canbe set to a prespecified reload value (stored inWDTREL) in order to allow further variation of themonitored time interval. Each time it is serviced bythe application software, the high byte of theWatchdog Timer is reloaded. Thus, time intervalsbetween 25 µs and 420 ms can be monitored (@20 MHz). The default Watchdog Timer interval af-ter reset is 6.55 ms (@ 20 MHz).

1.4 THE APPLICATION-SPECIFICSYNCHRONOUS SERIAL PORT

The ST10R163 has an additional customer specif-ic Synchronous Serial Port (SSP). The SSP is im-plemented as an X-Peripheral onto the XBUS inthe address range 00’EF00h...00’EFFFh, a 256Byte range (10 byte addresses used).

The SSP is a simple synchronous serial portwhich allows to communicate with external slavedevices such as EEPROM via a three-wire inter-face at up to 10 MBit/s (@20MHz CPU clock). TheSSP can be programmed to send command, ad-dress or data information to a peripheral or receivedata from a peripheral. For a write operation, theSSP can send up to tree bytes (24 bits) to a pe-ripheral. For a read operation, the SSP can firstsend up to three bytes to a peripheral before re-ceiving one byte from the peripheral. During eachtransfer, one of the two dedicated chip enable sig-nals selects one of the slaves devices connectedto the SSP.

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1.5 PROTECTED BITS

The ST10R163 provides a special mechanismtoprotect bits which can be modified by the on-chiphardware from being changed unintentionally by

software accesses to related bits (see also chap-ter “The Central Processing Unit”).The following bits are protected:

Σ = 25 protected bits.

Register Bit Name Notes

T2IC, T3IC, T4IC T2IR, T3IR, T4IR GPT1 timer interrupt request flags

T5IC, T6IC T5IR, T6IR GPT2 timer interrupt request flags

CRIC CRIR GPT2 CAPREL interrupt request flag

T3CON, T6CON T3OTL, T6OTL GPTx timer output toggle latches

S0TIC, S0TBIC S0TIR, S0TBIR ASC0 transmit(buffer) interrupt request flags

S0RIC, S0EIC S0RIR, S0EIR ASC0 receive/error interrupt request flags

S0CON S0REN ASC0 receiver enable flag

TFR TFR.15,14,13 Class A trap flags

TFR TFR.7,3,2,1,0 Class B trap flags

XPyIC (y=3...0) XPyIR (y=3...0) X-Peripheral y interrupt request flag

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ST10R163User Manual

2 - MEMORY ORGANIZATION

The memory space of the ST10R163 is configuredin a “Von Neumann” architecture. This means thatcode and data are accessed within the same line-ar address space. All of the physically separatedmemory areas, including internal RAM, the inter-nal Special Function Register Areas (SFRs andESFRs), the address areas for integrated XBUS

peripherals and external memory are mapped intoone common address space.The ST10R163 provides a total addressablememory space of 16 MBytes. This address spaceis arranged as 256 segments of 64 KBytes each,and each segment is again subdivided into fourdata pages of 16 KBytes each (see figure below).

Figure 2-1. Memory Areas and Address

VR02081B

Segment

Segment

Segment

Segment

2

255

254

FF FFFFH

H0000FF

03 0000 H

H000002

H000001

H000000

FE 0000 H

Data Page1023

0PageData

Data Page3

RAM/SFR Area

MemoryExternal

FFFF00 H

H00 F000

H00 C000

H00 8000

H00 4000

H00 0000

Data Page0

1PageData

Data Page2

3PageData

Address Space16 MByte KByte64

SegmentSystem 0

Segment

1

0

’

’

’

’

’

’

’

’

’

’

’

’

’

XSSP’E00000 H

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2 - MEMORY ORGANIZATION (ST10R163)

SpaceMost internal memory areas are mapped into seg-ment 0, the system segment. The upper 4 KByteof segment 0 (00’F000h...00’FFFFh) hold the In-ternal RAM and Special Function Register Areas(SFR and ESFR).

Code and data may be stored in any part of the in-ternal memory areas, except for the SFR blocks,which may be used for control / data, but not for in-structions.

Note: The ST10R163 is a Romless device: pro-gram ROM must be in external memory.

Bytes are stored at even or odd byte addresses.Words are stored in ascending memory locationswith the low byte at an even byte address beingfollowed by the high byte at the next odd byte ad-dress. Double words (code only) are stored in as-cending memory locations as two subsequentwords. Single bits are always stored in the speci-fied bit position at a word address. Bit position 0 isthe least significant bit of the byte at an even byteaddress, and bit position 15 is the most significantbit of the byte at the next odd byte address. Bit ad-dressing is supported for a part of the SpecialFunction Registers, a part of the internal RAM andfor the General Purpose Registers.

Figure 2-2. Storage of Words, Byte and Bits in a Byte Organized Memory

Note: Byte units forming a single word or a double word must always be stored within the same physical (internal, exter-nal, ROM, RAM) and organizational (page, segment) memory area.

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2.1 INTERNAL RAM AND SFR AREA

The RAM/SFR area is located within data page 3and provides access to 1 KByte of on-chip RAM(organized as 512*16) and to two 512 Byte blocksof Special Function Registers (SFRs).The internal RAM serves for several purposes:– System Stack (programmable size)

– General Purpose Register Banks (GPRs)

– Source and destination pointers for the Periph-eral Event Controller (PEC)

– Variable and other data storage, or

– Code storage.

Figure 2-3. Internal RAM Area and SFR Areas

Note: The upper 256 bytes of SFR area, ESFR area and internal RAM are bit-addressable (see shaded blocks in thefigure above).

VR02082B

RAM/SFR Area

InternalROMArea

Memory

External

FFFF00 H

H00 F000

H00 C000

H00 8000

H00 4000

H00 0000

KByte64SegmentSystem 0

00 HFFFF

FE0000 H

FA0000 H

F00000 H

4 KByte

Internal

RAM

Reserved

ESFR Area

SFR Area

RAM/SFR Area

H00 F200

’

’

’

’

’

’

’

’

’

’

’

0PageData

Data Page 1

2PageData

Data Page 3

H00 EF00’

XSSP

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INTERNAL RAM AND SFR AREA (Cont’d)Code accesses are always made on even byte ad-dresses. The highest possible code storage loca-tion in the internal RAM is either 00’FDFEh for sin-gle word instructions or 00’FDFCh for double wordinstructions. The respective location must containa branch instruction (unconditional), because se-quential boundary crossing from internal RAM tothe SFR area is not supported and causes errone-ous results.Any word and byte data in the internal RAM canbe accessed via indirect or long 16-bit addressingmodes, if the selected DPP register points to datapage 3. Any word data access is made on an evenbyte address. The highest possible word datastorage location in the internal RAM is 00’FDFEh.For PEC data transfers, the internal RAM can beaccessed independent of the contents of the DPPregisters via the PEC source and destinationpointers.The upper 256 Byte of the internal RAM(00’FD00h through 00’FDFFh) and the GPRs ofthe current bank are provided for single bit stor-age, and thus they are bit addressable.

System Stack

The system stack may be defined within the inter-nal RAM. The size of the system stack is control-led by bitfield STKSZ in register SYSCON (see ta-ble below).

For all system stack operations the on-chip RAMis accessed via the Stack Pointer (SP) register.The stack grows downward from higher towardslower RAM address locations. Only word access-es are supported to the system stack. A stackoverflow (STKOV) and a stack underflow(STKUN) register are provided to control the lowerand upper limits of the selected stack area. Thesetwo stack boundary registers can be used not onlyfor protection against data destruction, but also al-low to implement a circular stack with hardwaresupported system stack flushing and filling (exceptfor the 1KByte stack option).

The technique of implementing this circular stackis described in chapter “System Programming”.

<STKSZ> Stack Size (Words) Internal RAM Addresses (Words)

0 0 0 b 256 00’FBFEh...00’FA00h (Default after Reset)

0 0 1 b 128 00’FBFEh...00’FB00h

0 1 0 b 64 00’FBFEh...00’FB80h

0 1 1 b 32 00’FBFEh...00’FBC0h

1 0 0 b --- Reserved. Do not use this combination.



1 1 1 b 512 00’FDFEh...00’FA00h (Note: No circular stack)

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INTERNAL RAM AND SFR AREA (Cont’d)General Purpose RegistersThe General Purpose Registers (GPRs) use ablock of 16 consecutive words within the internalRAM. The Context Pointer (CP) register deter-mines the base address of the currently activeregister bank. This register bank may consist of upto 16 word GPRs (R0, R1, ..., R15) and/or of up to16 byte GPRs (RL0, RH0, ..., RL7, RH7). The six-teen byte GPRs are mapped onto the first eightword GPRs (see table below).In contrast to the system stack, a register bankgrows from lower towards higher address loca-tions and occupies a maximum space of 32 bytes.The GPRs are accessed via short 2-, 4- or 8-bitaddressing modes using the Context Pointer (CP)register as base address (independent of the cur-rent DPP register contents). Additionally, each bit

in the currently active register bank can be ac-cessed individually.The ST10R163 supports fast register bank (con-text) switching. Multiple register banks can physi-cally exist within the internal RAM at the sametime. Only the register bank selected by the Con-text Pointer register (CP) is active at a given time,however. Selecting a new active register bank issimply done by updating the CP register. A partic-ular Switch Context (SCXT) instruction performsregister bank switching and an automatic savingof the previous context. The number of implement-ed register banks (arbitrary sizes) is only limitedby the size of the available internal RAM.Details on using, switching and overlapping regis-ter banks are described in chapter “System Pro-gramming”.

Mapping of General Purpose Registers to RAM Addresses

Internal RAM Address Byte Registers Word Register

<CP> + 1Eh --- R15

<CP> + 1Ch --- R14

<CP> + 1Ah --- R13

<CP> + 18h --- R12

<CP> + 16h --- R11

<CP> + 14h --- R10

<CP> + 12h --- R9

<CP> + 10h --- R8

<CP> + 0Eh RH7RL7 R7

<CP> + 0Ch RH6RL6 R6

<CP> + 0Ah RH5RL5 R5

<CP> + 08h RH4RL4 R4





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INTERNAL RAM AND SFR AREA (Cont’d)PEC Source and Destination PointersThe 16 word locations in the internal RAM from00’FCE0h to 00’FCFEh (just below the bit-ad-dressable section) are provided as source anddestination address pointers for data transfers onthe eight PEC channels. Each channel uses a pairof pointers stored in two subsequent word loca-tions with the source pointer (SRCPx) on the lowerand the destination pointer (DSTPx) on the higherword address (x = 7...0).Whenever a PEC data transfer is performed, thepair of source and destination pointers, which is

selected by the specified PEC channel number, isaccessed independent of the current DPP registercontents and also the locations referred to bythese pointers are accessed independent of thecurrent DPP register contents. If a PEC channel isnot used, the corresponding pointer locations areaavailable and can be used for word or byte datastorage.

For more details about the use of the source anddestination pointers for PEC data transfers seesection “Interrupt and Trap Functions”.

Figure 2-4. Location of the PEC Pointers

VR02083B

DSTP7

SRCP7

PEC

Source

and

Destination

Pointers

DSTP0

SRCP0

Internal

RAM

00’FCFE

00’FCFC

00’FCE2

00’FCE000’F9FE

00’FA00

00’FCE0

00’FCFE

00’FD00

00’FDDE

H

H

H

H

H

H

H

H

H

H

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INTERNAL RAM AND SFR AREA (Cont’d)Special Function RegistersThe functions of the CPU, the bus interface, the IOports and the on-chip peripherals of theST10R163 are controlled via a number of SpecialFunction Registers (SFRs). These SFRs are ar-ranged within two areas of 512 Byte size each.The first register block, the SFR area, is located inthe 512 Bytes above the internal RAM(00’FFFFh...00’FE00h), the second register block,the Extended SFR (ESFR) area, is located in the512 Bytes below the internal RAM(00’F1FFh...00’F000h).Special function registers can be addressed via in-direct and long 16-bit addressing modes. Using an8-bit offset together with an implicit base addressallows to address word SFRs and their respectivelow bytes. However, thisdoes not work for the re-spective high bytes!Note: Writing to any byte of an SFR causes thenon-addressed complementary byte to becleared!The upper half of each register block is bit-ad-dressable, so the respective control/status bitscan directly be modified or checked using bit ad-dressing.When accessing registers in the ESFR area using8-bit addresses or direct bit addressing, an ExtendRegister (EXTR) instruction is required before, toswitch the short addressing mechanism from thestandard SFR area to the Extended SFR area.This is not required for 16-bit and indirect address-es. The GPRs R15...R0 are duplicated, ie. theyare accessible within both register blocks via short2-, 4- or 8-bit addresses without switching.Example:EXTR #4

;Switch to ESFR area for the next 4instructions

MOV ODP2, #data16

;ODP2 uses 8-bit reg addressing

BFLDL DP6, #mask, #data8

;Bit addressing for bit fields

BSET DP1H.7

;Bit addressing for single bits

MOV T8REL, R1

;T8REL uses 16-bit address, R1 isduplicated...

;...and also accessible via the ESFRmode

;(EXTR is not required for thisaccess)

;------- ;-------------------

;The scope of the EXTR #4 instructionends here!

MOV T8REL, R1

;T8REL uses 16-bit address, R1 isduplicated...

;...and does not require switching

In order to minimize the use of the EXTR instruc-tions the ESFR area mostly holds registers whichare mainly required for initialization and mode se-lection. Registers that need to be accessed fre-quently are allocated to the standard SFR area,wherever possible.

Note : The development tools are equipped tomonitor accesses to the ESFR area and will auto-matically insert EXTR instructions, or issue awarning in case of missing or excessive EXTR in-structions.

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2.2 EXTERNAL MEMORY SPACE

The ST10R163 is capable of using an addressspace of up to 16 MByte. Only parts of this ad-dress space are occupied by internal memory are-as. All addresses which are not used for on-chipRAM, for registers or internal Xperipherals mayreference external memory locations. This exter-nal memory is accessed via the ST10R163’s ex-ternal bus interface.

Four memory bank sizes are supported:

– Non-segmented mode: 64KByte with A15...A0on PORT0 or PORT1

– 2- bit segmented mode: 256 KByte withA17...A16 on Port 4 and A15...A0 on PORT0 orPORT1

– 4-bit segmented mode: 1 MByte with A19...A16on Port 4 and A15...A0 on PORT0 or PORT1

– 8-bit segmented mode: 16 MByte with A23...A16on Port 4 and A15...A0 on PORT0 or PORT1

Each bank can be directly addressed via the ad-dress bus, while the programmable chip selectsignals can be used to select various memorybanks.

The ST10R163 also supports four different bustypes :

– Multiplexed 16-bit Bus, with address and data onPORT0 (Default after Reset)

– Multiplexed 8-bit Bus, with address and data onPORT0/P0L

– Demultiplexed 16-bit Bus, with address onPORT1 and data on PORT0

– Demultiplexed 8-bit Bus, with address onPORT1 and data on P0L

Memory model and bus mode are selected duringreset by pin EA and PORT0 pins. For further de-tails about the external bus configuration and con-trol please refer to chapter ”The External Bus In-terface”.

External word and byte data can only be accessedvia indirect or long 16-bit addressing modes usingone of the four DPP registers. There is no shortaddressing mode for external operands. Any worddata access is made to an even byte address.

For PEC data transfers the external memory insegment 0 can be accessed independent of thecontents of the DPP registers via the PEC sourceand destination pointers.

The external memory is not provided for single bitstorage and therefore it is not bit addressable.

2.3 CROSSING MEMORY BOUNDARIES

The address space of the ST10R163 is implicitlydivided into equally sized blocks of different gran-ularity and into logical memory areas. Crossingthe boundaries between these blocks (code or da-ta) or areas requires special attention to ensurethat the controller executes the desired opera-tions.

Memory Areas are partitions of the addressspace that represent different kinds of memory (ifprovided at all). These memory areas are the in-ternal RAM/SFR area, and the external memory.Accessing subsequent data locations that belongto different memory areas is no problem. Howev-er, when executing code, the different memory ar-eas must be switched explicitly via branch instruc-tions. Sequential boundary crossing is not sup-ported and leads to erroneous results.

Note : Changing from the external memory area tothe internal RAM/SFR area takes place withinsegment 0.

Segments are contiguous blocks of 64 KByteeach. They are referenced via the code segmentpointer CSP for code fetches and via an explicitsegment number for data accesses overriding thestandard DPP scheme.During code fetching segments are not changedautomatically, but rather must be switched explic-itly. The instructions JMPS, CALLS and RETS willdo this.In larger sequential programs make sure that thehighest used code location of a segment containsan unconditional branch instruction to the respec-tive following segment, to prevent the prefetcherfrom trying to leave the current segment.

Data Pages are contiguous blocks of 16 KByteeach. They are referenced via the data pagepointers DPP3...0 and via an explicit data pagenumber for data accesses overriding the standardDPP scheme. Each DPP register can select oneof the possible 1024 data pages. The DPP registerthat is used for the current access is selected viathe two upper bits of the 16-bit data address. Sub-sequent 16-bit data addresses that cross the 16KByte data page boundaries therefore will use dif-ferent data page pointers, while the physical loca-tions need not be subsequent within memory.

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ST10R163User Manual

3 - CENTRAL PROCESSING UNIT

Basic tasks of the CPU are to fetch and decode in-structions, to supply operands for the arithmeticand logic unit (ALU), to perform operations onthese operands in the ALU, and to store the previ-ously calculated results. As the CPU is the mainengine of the ST10R163 controller, it is also af-fected by certain actions of the peripheral subsys-tem.

Since a four stage pipeline is implemented in theST10R163, up to four instructions can be proc-essed in parallel. Most instructions of theST10R163 are executed in one machine cycle (ie.100 ns @ 20 MHz CPU clock) due to this parallel-ism. This chapter describes how the pipelineworks for sequential and branch instructions ingeneral, and which hardware provisions havebeen made to speed the execution of jump in-

structions in particular. The general instructiontiming is described including standard and excep-tional timing.

While internal memory accesses are normally per-formed by the CPU itself, external peripheral ormemory accesses are performed by a particularon-chip External Bus Controller (EBC), which isautomatically invoked by the CPU whenever acode or data address refers to the external ad-dress space. If possible, the CPU continues oper-ating while an external memory access is inprogress. If external data are required but are notyet available, or if a new external memory accessis requested by the CPU, before a previous ac-cess has been completed, the CPU will be held bythe EBC until the request can be satisfied. TheEBC is described in a dedicated chapter.

Figure 3-1. CPU Block Diagram

VR02080B

CPU

SPSTKOVSTKUN

Instr.Reg.Instr.Ptr.Exec.Unit

4-StagePipeline

MDH

MDL

PSWSYSCON Context Ptr.

Mul/Div-HWGen

-

R15

R0

General

Purpose

Registers

Bit-Mask

Barrel Shifter

ALU(16-bit)

Data PagePtr. CodeSeg.Ptr.

RAM

R15

R0

ROM

16

16

32

BUSCON 0BUSCON 1BUSCON 2BUSCON 3BUSCON 4 ADDRSEL 4

ADDRSEL 3ADDRSEL 2ADDRSEL 1

1 KByte

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3 - CENTRAL PROCESSING UNIT (ST10R163)

The on-chip peripheral units of the ST10R163work nearly independently of the CPU with a sep-arate clock generator. Data and control informa-tion is interchanged between the CPU and theseperipherals via Special Function Registers(SFRs). Whenever peripherals need a non-deter-ministic CPU action, an on-chip Interrupt Control-ler compares all pending peripheral service re-quests against each other and prioritizes one ofthem. If the priority of the current CPU operation islower than the priority of the selected peripheralrequest, an interrupt will occur.Basically, there are two types of interrupt process-ing:

• Standard interrupt processing forces the CPUto save the current program status and the returnaddress on the stack before branching to the inter-rupt vector jump table.

• PEC interrupt processing steals just one ma-chine cycle from the current CPU activity to per-form a single data transfer via the on-chip Periph-eral Event Controller (PEC).

System errors detected during program execution(hardware traps) or an external non-maskable in-terrupt are also processed as standard interruptswith a very high priority.

In contrast to other on-chip peripherals, there is acloser conjunction between the watchdog timerand the CPU. If enabled, the watchdog timer ex-pects to be serviced by the CPU within a program-mable period of time, otherwise it will reset thechip. Thus, the watchdog timer is able to preventthe CPU from going totally astray when executingerroneous code. After reset, the watchdog timerstarts counting automatically, but it can be disa-bled via software, if desired.

Beside its normal operation there are the followingparticular CPU states:• Reset state: Any reset (hardware, software,watchdog) forces the CPU into a predefined activestate.• IDLE state: The clock signal to the CPU itself isswitched off, while the clocks for the on-chip pe-ripherals keep running.

• POWER DOWN state: All of the on-chip clocksare switched off.

A transition into an active CPU state is forced byan interrupt (if being IDLE) or by a reset (if being inPOWER DOWN mode).The IDLE, POWER DOWN and RESET statescan be entered by particular ST10R163 systemcontrol instructions.

A set of Special Function Registers is dedicated tothe functions of the CPU core:• General System Configuration: SYSCON

(RP0H)

• CPU Status Indication and Control: PSW• Code Access Control: IP, CSP

• Data Paging Control: DPP0, DPP1, DPP2,DPP3

• GPRs Access Control: CP• System Stack Access Control: SP, STKUN,

STKOV

• Multiply and Divide Support: MDL, MDH, MDC• ALU Constants Support: ZEROS, ONES

3.1 INSTRUCTION PIPELINING

The instruction pipeline of the ST10R163 parti-tiones instruction processing into four stages ofwhich each one has its individual task:1st –>FETCH:In this stage the instruction selected by the In-struction Pointer (IP) and the Code SegmentPointer (CSP) is fetched from either the internalRAM or external memory.2nd –>DECODE:In this stage the instructions are decoded and, ifrequired, the operand addresses are calculatedand the respective operands are fetched. For allinstructions, which implicitly access the systemstack, the SP register is either decremented or in-cremented, as specified. For branch instructionsthe Instruction Pointer and the Code SegmentPointer are updated with the desired branch targetaddress (provided that the branch is taken).3rd –>EXECUTE:In this stage an operation is performed on the pre-viously fetched operands in the ALU. Additionally,the condition flags in the PSW register are updat-ed as specified by the instruction. All explicit writesto the SFR memory space and all auto-incrementor auto-decrement writes to GPRs used as indi-rect address pointers are performed during the ex-ecute stage of an instruction, too.4th –>WRITE BACK:In this stage all external operands and the remain-ing operands within the internal RAM space arewritten back.A particularity of the ST10R163 are the injected in-structions. These injected instructions are gener-ated internally by the machine to provide the timeneeded to process instructions, which cannot beprocessed within one machine cycle. They are au-tomatically injected into the decode stage of thepipeline, and then they pass through the remain-ing stages like every standard instruction. Pro-gram interrupts are performed by means of inject-ed instructions, too. Although these internally in-jected instructions will not be noticed in reality,they are introduced here to ease the explanationof the pipeline in the following.

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INSTRUCTION PIPELINING (Cont’d)

Sequential Instruction Processing

Each single instruction has to pass through eachof the four pipeline stages regardless of whetherall possible stage operations are really performedor not. Since passing through one pipeline stagetakes at least one machine cycle, any isolated in-struction takes at least four machine cycles to becompleted. Pipelining, however, allows parallel(ie. simultaneous) processing of up to four instruc-tions. Thus, most of the instructions seem to be

processed during one machine cycle as soon asthe pipeline has been filled once after reset (seefigure below).

Instruction pipelining increases the average in-struction throughput considered over a certain pe-riod of time. In the following, any execution timespecification of an instruction always refers to theaverage execution time due to pipelined parallelinstruction processing.

Figure 3-2. Sequential Instruction Pipelining

Standard Branch Instruction Processing

Instruction pipelining helps to speed sequentialprogram processing. In the case that a branch istaken, the instruction which has already beenfetched providently is mostly not the instructionwhich must be decoded next. Thus, at least oneadditional machine cycle is normally required tofetch the branch target instruction. This extra ma-

chine cycle is provided by means of an injected in-struction (see figure below).

If a conditional branch is not taken, there is no de-viation from the sequential program flow, and thusno extra time is required. In this case the instruc-tion after the branch instruction will enter the de-code stage of the pipeline at the beginning of thenext machine cycle after decode of the conditionalbranch instruction.

Figure 3-3. Standard Branch Instruction Pipelining

1 MachineCycle

FETCH I2

I1

I3

I2

I1

I4

I3

I2

I1

I6

I5

I4

I3

I5

I4

I3

I2

I1

DECODE

EXECUTE

WRITEBACK

time

1 MachineCycle

FETCH In+2

BRANCH

In

. . .

ITARGET

(IINJECT)

BRANCH

In

ITARGET+1

ITARGET

(IINJECT)

BRANCH

ITARGET+3

ITARGET+2

ITARGET+1

ITARGET

ITARGET+2

ITARGET+1

ITARGET

(IINJECT)

BRANCH

In

. . .

. . .

DECODE

EXECUTE

WRITEBACK

time

Injection

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INSTRUCTION PIPELINING (Cont’d)Cache Jump Instruction ProcessingThe ST10R163 incorporates a jump cache to opti-mize conditional jumps, which are processed re-peatedly within a loop. Whenever a jump on cacheis taken, the extra time to fetch the branch targetinstruction can be saved and thus the correspond-ing cache jump instruction in most cases takesonly one machine cycle.This performance is achieved by the followingmechanism:Whenever a cache jump instruction passesthrough the decode stage of the pipeline for thefirst time (and provided that the jump condition ismet), the jump target instruction is fetched as usu-al, causing a time delay of one machine cycle. Incontrast to standard branch instructions, however,the target instruction of a cache jump instruction

(JMPA, JMPR, JB, JBC, JNB, JNBS) is additional-ly stored in the cache after having been fetched.After each repeatedly following execution of thesame cache jump instruction, the jump target in-struction is not fetched from progam memory buttaken from the cache and immediatly injected intothe decode stage of the pipeline (see figure be-low).A time saving jump on cache is always taken afterthe second and any further occurrence of thesame cache jump instruction, unless an instruc-tion which, has the fundamental capability ofchanging the CSP register contents (JMPS,CALLS, RETS, TRAP, RETI), or any standard in-terrupt has been processed during the period oftime between two following occurrences of thesame cache jump instruction.

Figure 3-4. Cache Jump Instruction Pipelining

In+2

Cache Jmp

In

. . .

ITARGET+1

ITARGET

Cache Jmp

In

ITARGET+2

ITARGET+1

ITARGET

Cache Jmp

In+2

Cache Jmp

In

. . .

ITARGET

(IINJECT)

Cache Jmp

In

ITARGET+1

ITARGET

(IINJECT)

Cache Jmp

1 MachineCycle

FETCH

DECODE

EXECUTE

WRITEBACK

1st loop iteration

Injection Injection of cachedTarget Instruction

Repeated loop iteration

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Particular Pipeline Effects

Since up to four different instructions are proc-essed simultaneously, additional hardware hasbeen spent in the ST10R163 to consider all causaldependencies which may exist on instructions indifferent pipeline stages without a loss of perform-ance. This extra hardware (ie. for ’forwarding’ op-erand read and write values) resolves most of thepossible conflicts (eg. multiple usage of buses) ina time optimized way and thus avoids that thepipeline becomes noticeable for the user in mostcases. However, there are some very rare cases,where the circumstance that the ST10R163 is apipelined machine requires attention by the pro-grammer. In these cases the delays caused bypipeline conflicts can be used for other instruc-tions in order to optimize performance.

n Context Pointer Updating

An instruction, which calculates a physical GPRoperand address via the CP register, is mostly notcapable of using a new CP value, which is to beupdated by an immediately preceding instruction.Thus, to make sure that the new CP value is used,at least one instruction must be inserted betweena CP-changing and a subsequent GPR-using in-struction, as shown in the following example:

In: SCXT CP, #0FC00h;

;select a new context

I n+1: ....

;must not be an instruction using;a GPR

I n+2: MOV R0, #dataX

;write to GPR 0 in the new context

n Data Page Pointer Updating

An instruction, which calculates a physical oper-and address via a particular DPPn (n=0 to 3) reg-ister, is mostly not capable of using a new DPPnregister value, which is to be updated by an imme-diately preceding instruction. Thus, to make surethat the new DPPn register value is used, at leastone instruction must be inserted between a DPPn-changing instruction and a subsequent instructionwhich implicitly uses DPPn via a long or indirectaddressing mode, as shown in the following ex-ample:

I n: MOV DPP0, #4

;select data page 4 via DPP0

I n+1: ....

;must not be an instruction using DPP0

I n+2: MOV DPP0:0000h, R1

;move contents of R1 to address;location 01’0000h (in data page 4);supposed segmentation is enabled

n Explicit Stack Pointer Updating

None of the RET, RETI, RETS, RETP or POP in-structions is capable of correctly using a new SPregister value, which is to be updated by an imme-diately preceding instruction. Thus, in order to usethe new SP register value without erroneouslyperformed stack accesses, at least one instructionmust be inserted between an explicitly SP-writingand any subsequent of the just mentioned implic-itly SP-using instructions, as shown in the follow-ing example:

I n: MOV SP, #0FA40h

;select a new top of stack

I n+1: ....

;must not be an instruction popping;operands from the system stack

I n+2: POP R0

;pop word value from new top of stack;into R0

n External Memory Access Sequences

The effect described here will only become notice-able, when watching the external memory accesssequences on the external bus (eg. by means of aLogic Analyzer). Different pipeline stages can si-multaneously put a request on the External BusController (EBC). The sequence of instructionsprocessed by the CPU may diverge from the se-quence of the corresponding external memory ac-cesses performed by the EBC, due to the prede-fined priority of external memory accesses:

1st Write Data2nd Fetch Code3rd Read Data.

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n Controlling Interrupts

Software modifications (implicit or explicit) of thePSW are done in the execute phase of the respec-tive instructions. In order to maintain fast interruptresponses, however, the current interrupt prioriti-zation round does not consider these changes, ie.an interrupt request may be acknowledged afterthe instruction that disables interrupts via IEN orILVL or after the following instructions. Time criti-cal instruction sequences therefore should not be-gin directly after the instruction disabling inter-rupts, as shown in the following example:INT_OFF: BCLR IEN

;globally disable interrupts

I N-1

;non-critica l instruction

CRIT_1ST : I N

;begin of uninterruptable crit ical;sequence

. . .

CRIT_LAST: I N+x

;end of uninterruptable critical;sequence

INT_ON: BSET IEN

;globally re-enable interrupts

Note: The described delay of 1 instruction also ap-plies for enabling the interrupts system ie. no inter-rupt requests are acknowledged until the instruc-tion following the enabling instruction.

n Initialization of Port Pins

Modifications of the direction of port pins (input oroutput) become effective only after the instructionfollowing the modifying instruction. As bit instruc-tions (BSET, BCLR) use internal read-modify-write sequences accessing the whole port, in-structions modifying the port direction should befollowed by an instruction that does not access thesame port (see example below).WRONG: BSET DP3.13;

;change direction of P3.13 to output

BSET P3.5 ;

;P3.13 is still input, the rd-mod-wr;reads pin P3.13

RIGHT: BSET DP3.13;

;change direction of P3.13 to output

NOP

;any instruction not accessing port 3

BSET P3.5 ;

;P3.13 is now output,the rd-mod-wr;reads the P3.13 output latch

n Changing the System Configuration

The instruction following an instruction that chang-es the system configuration via register SYSCON(eg. segmentation, stack size) cannot use thenew resources (eg. stack). In these cases an in-struction that does not access these resourcesshould be inserted.

n BUSCON/ADDRSEL

The instruction following an instruction that chang-es the properties of an external address area can-not access operands within the new area. In thesecases an instruction that does not access this ad-dress area should be inserted. Code accesses tothe new address area should be made after an ab-solute branch to this area.

Note : As a rule, instructions that change externalbus properties should not be executed from the re-spective external memory area.

n Updating the Stack Pointer

An instruction that changes the contents of thestack pointer SP (MOV, ADD, SUB) may not befollowed directly by an instruction that implicitlyuses the SP, ie. a POP or RETURN instruction. Toensure proper operation an instruction should beinserted that does not use the stack pointer.

n Timing

Instruction pipelining reduces the average instruc-tion processing time in a wide scale (from four toone machine cycles, mostly). However, there aresome rare cases, where a particular pipeline situ-ation causes the processing time for a single in-struction to be extended either by a half or by onemachine cycle. Although this additional time rep-resents only a tiny part of the total program execu-tion time, it might be of interest to avoid thesepipeline-caused time delays in time critical pro-gram modules.

Besides a general execution time description, thefollowing section provides some hints on how tooptimize time-critical program parts with regard tosuch pipeline-caused timing particularities.

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3.2 BIT-HANDLING AND BIT-PROTECTION

The ST10R163 provides several mechanisms tomanipulate bits. These mechanisms either manip-ulate software flags within the internal RAM, con-trol on-chip peripherals via control bits in their re-spective SFRs or control IO functions via portpins.The instructions BSET, BCLR, BAND, BOR, BX-OR, BMOV, BMOVN explicitly set or clear specificbits. The instructions BFLDL and BFLDH allow tomanipulate up to 8 bits of a specific byte at onetime. The instructions JBC and JNBS implicitlyclear or set the specified bit when the jump is tak-en. The instructions JB and JNB (also conditionaljump instructions that refer to flags) evaluate thespecified bit to determine if the jump is to be taken.Note: Bit operations on undefined bit locations willalways read a bit value of ‘0’, while the write ac-cess will not affect the respective bit location.All instructions that manipulate single bits or bitgroups internally use a read-modify-write se-quence that accesses the whole word, which con-tains the specified bit(s).This method has several consequences:• Bits can only be modified within the internal ad-dress areas, ie. internal RAM and SFRs. Externallocations cannot be used with bit instructions.The upper 256 bytes of the SFR area, the ESFRarea and the internal RAM are bit-addressable(see chapter “Memory Organization”), ie. thoseregister bits located within the respective sectionscan be directly manipulated using bit instructions.

The other SFRs must be accessed byte/wordwise.

Note : All GPRs are bit-addressable independentof the allocation of the register bank via the con-text pointer CP. Even GPRs which are allocated tonot bit-addressable RAM locations provide thisfeature.

• The read-modify-write approach may be criticalwith hardware-effected bits. In these cases thehardware may change specific bits while the read-modify-write operation is in progress, where thewriteback would overwrite the new bit value gen-erated by the hardware. The solution is either theimplemented hardware protection (see below) orrealized through special programming (see “Par-ticular Pipeline Effects”).

Protected bits are not changed during the read-modify-write sequence, ie. when hardware setseg. an interrupt request flag between the read andthe write of the read-modify-write sequence. Thehardware protection logic guarantees that only theintended bit(s) is/are affected by the write-backoperation.

Note : If a conflict occurs between a bit manipula-tion generated by hardware and an intended soft-ware access the software access has priority anddetermines the final value of the respective bit.

A summary of the protected bits implemented inthe ST10R163 can be found at the end of chapter“Architectural Overview”.

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3.3 INSTRUCTION STATE TIMES

Basically, the time to execute an instruction de-pends on where the instruction is fetched from,and where possible operands are read from orwritten to. The fastest processing mode of theST10R163 is to execute a program fetched fromfast external memory (no wait states), using a 16-bit demultiplexed bus. In that case most of the in-structions can be processed within just one ma-chine cycle, which is also the general minimumexecution time.

All external memory accesses are performed bythe ST10R163’s on-chip External Bus Controller(EBC), which works in parallel with the CPU.

This section summarizes the execution times in avery condensed way. A detailled description of theexecution times for the various instructions andthe specific exceptions can be found in the“ST10Family Programming Manual” .

The table below shows the minimum executiontimes required to process a ST10R163 instructionfetched from the internal RAM or from externalmemory. These execution times apply to most of

the ST10R163 instructions - except some of thebranches, the multiplication and the division in-structions and a special move instruction. Thenumbers in the table are in units of [ns], refer to aCPU clock of 20 MHz and assume no waitstates.Execution from the internal RAM provides flexibili-ty in terms of loadable and modifiable code on theaccount of execution time.Execution from external memory strongly de-pends on the selected bus mode and the program-ming of the bus cycles (waitstates).The operand and instruction accesses listed be-low can extend the execution time of an instruc-tion:– Internal RAM operand reads via indirect ad-

dressing modes– Internal SFR operand reads immediately after

writing– External operand reads– External operand writes– Testing Branch Conditions immediately after

PSW writes

Minimum Execution Times

Instruction Fetch Word Operand Access

Memory Area Word InstructionDoublewordInstruction

Read from Write to

Internal RAM 300 400 0/50 0

16-bit Demux Bus 100 200 100 100

16-bit Mux Bus 150 300 150 150

8-bit Demux Bus 200 400 200 200

8-bit Mux Bus 300 600 300 300

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3.4 CPU SPECIAL FUNCTION REGISTERS

The core CPU requires a set of Special FunctionRegisters (SFRs) to maintain the system state in-formation, to supply the ALU with register-ad-dressable constants and to control system andbus configuration, multiply and divide ALU opera-tions, code memory segmentation, data memorypaging, and accesses to the General PurposeRegisters and the System Stack.The access mechanism for these SFRs in theCPU core is identical to the access mechanism forany other SFR. Since all SFRs can simply be con-trolled by means of any instruction, which is capa-ble of addressing the SFR memory space, a lot offlexibility has been gained, without the need tocreate a set of system-specific instructions.Note, however, that there are user access restric-tions for some of the CPU core SFRs to ensureproper processor operations. The instructionpointer IP and code segment pointer CSP cannotbe accessed directly at all. They can only bechanged indirectly via branch instructions.

The PSW, SP, and MDC registers can be modifiednot only explicitly by the programmer, but also im-plicitly by the CPU during normal instructionprocessing. Note that any explicit write request(via software) to an SFR supersedes a simultane-ous modification by hardware of the same regis-ter.

Note : Any write operation to a single byte of anSFR clears the non-addressed complementarybyte within the specified SFR.Non-implemented (reserved) SFR bits cannot bemodified, and will always supply a read value of’0’.

The System Configuration Register SYSCON

This bit-addressable register provides generalsystem configuration and control functions. Thereset value for register SYSCON depends on thestate of the PORT0 pins during reset.

SYSCON (FF12h / 89h) SFR Reset Value: 0XX0h

XPER-SHARE

VISIBLE- - - -

SSPEN

ROMS1

WRCFG

5 4 3 2 1 011 10 9 8 7 615 14 13 12

- - rwrw rw rwrw rw

STKSZSGTDIS

ROMEN

rw

BYTDIS

CLKEN

rw - rwrw

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CPU SPECIAL FUNCTION REGISTERS (Cont’d)

Note: Register SYSCON cannot be changed after execution of the EINIT instruction.The function of bits XPER-SHARE, VISIBLE, WRCFG, BYTDIS, ROMEN and ROMS1 is described in more detailin chapter “The External Bus Controller”.

Bit Function

XPER-SHAREXBUS Peripheral Share Mode Control

‘0’: External accesses to XBUS peripherals are disabled‘1’: XBUS peripherals are accessible via the external bus during hold mode.

VISIBLEVisible Mode Control

‘0’: Accesses to XBUS peripherals are done internally‘1’: XBUS peripheral accesses are made visible on the external pins.

SSPENXperipheral SSP Enable Control‘0’: SSP is disabled. Pins P4.[7..4] are general purpose IOs or segment address lines‘1’: SSP is enabled. Pins P4.[7..4] are SSP IOs or segment address lines

WRCFGWrite Configuration Control (Set according to pin P0H.0 during reset)

‘0’: Pins WR and BHE retain their normal function‘1’: Pin WR acts as WRL, pin BHE acts as WRH

CLKENSystem Clock Output Enable (CLKOUT)

‘0’: CLKOUT disabled: pin may be used for general purpose IO‘1’: CLKOUT enabled: pin outputs the system clock signal

BYTDISDisable/Enable Control for Pin BHE (Set according to data bus width)

‘0’: Pin BHE enabled‘1’: Pin BHE disabled, pin may be used for general purpose IO

ROMEN

Internal ROM Enable (Set according to pin EA during reset)

‘0’: Internal ROM disabled: accesses to the ROM area use the external bus‘1’: Internal ROM enabled

This bit is not relevant on the ST10R163 since it does not include internal ROM. It should bekept to 0

SGTDISSegmentation Disable/Enable Control

‘0’: Segmentation enabled (CSP is saved/restored during interrupt entry/exit)‘1’: Segmentation disabled (Only IP is saved/restored)

ROMS1

Internal ROM Mapping

‘0’: Internal ROM area mapped to segment 0 (00’0000h...00’7FFFh)‘1’: Internal ROM area mapped to segment 1 (01’0000h...01’7FFFh)

This bit is not relevant on the ST10R165 since it does not include internal ROM. It should bekept to 0.

STKSZSystem Stack Size

Selects the size of the system stack (in the internal RAM) from 32 to 1024 words

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CPU SPECIAL FUNCTION REGISTERS (Cont’d)System Clock Output Enable (CLKEN)The system clock output function is enabled bysetting bit CLKEN in register SYSCON to ’1’. If en-abled, port pin P3.15 takes on its alternate func-tion as CLKOUT output pin. The clock output is a50 % duty cycle clock whose frequency equals theCPU operating frequency (fOUT = fCPU).Note: The output driver of port pin P3.15 isswitched on automatically, when the CLKOUTfunction is enabled. The port direction bit is disre-garded.After reset, the clock output function is disabled(CLKEN = ‘0’).Segmentation Disable/Enable Control (SGT-DIS)Bit SGTDIS allows to select either the segmentedor non-segmented memory mode.In non-segmented memory mode (SGTDIS=’1’)it is assumed that the code address space is re-stricted to 64 KBytes (segment 0) and thus 16 bitsare sufficient to represent all code addresses. Forimplicit stack operations (CALL or RET) the CSPregister is totally ignored and only the IP is savedto and restored from the stack.

In segmented memory mode (SGTDIS=’0’) it isassumed that the whole address space is availa-ble for instructions. For implicit stack operations(CALL or RET) the CSP register and the IP aresaved to and restored from the stack. After resetthe segmented memory mode is selected.

Note : Bit SGTDIS controls if the CSP register ispushed onto the system stack in addition to the IPregister before an interrupt service routine is en-tered, and it is repopped when the interrupt serv-ice routine is left again.

System Stack Size (STKSZ)

This bitfield defines the size of the physical systemstack, which is located in the internal RAM of theST10R163. An area of 32...512 words or all of theinternal RAM may be dedicated to the systemstack. A “circular stack” mechanism allows to usea bigger virtual stack than this dedicated RAM ar-ea.

These techniques as well as the encoding of bit-field STKSZ are described in more detail in chap-ter “System Programming”.

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CPU SPECIAL FUNCTION REGISTERS (Cont’d)The Processor Status Word PSWThis bit-addressable register reflects the currentstate of the microcontroller. Two groups of bitsrepresent the current ALU status, and the current

CPU interrupt status. A separate bit (USR0) withinregister PSW is provided as a general purposeuser flag.

PSW (FF10h / 88h) SFR Reset Value: 0000h

Bit Function

NNegative Result

Set, when the result of an ALU operation is negative.

CCarry Flag

Set, when the result of an ALU operation produces a carry bit.

VOverflow Result

Set, when the result of an ALU operation produces an overflow.

ZZero Flag

Set, when the result of an ALU operation is zero.

EEnd of Table Flag

Set, when the source operand of an instruction is 8000h or 80h.

MULIPMultip lication/Div ision In Progress

‘0’: There is no multiplication/division in progress.‘1’: A multiplication/division has been interrupted.

USR0User General Purpose Flag

May be used by the application software.

HLDEN,ILVL, IEN

Interrupt and EBC Control Fields

Define the response to interrupt requests and enable external bus arbitration. (Described in section“Interrupt and Trap Functions”)

HLDEN

MULIPUSR0- NZ CVE

5 4 3 2 1 011 10 9 8 7 615 14 13 12

rw rw rw rwrw rw rw-rw -rw

IEN --ILVL

rw

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ALU Status (N, C, V, Z, E, MULIP)

The condition flags (N, C, V, Z, E) within the PSWindicate the ALU status due to the last recentlyperformed ALU operation. They are set by most ofthe instructions due to specific rules, which de-pend on the ALU or data movement operation per-formed by an instruction.

After execution of an instruction which explicitlyupdates the PSW register, the condition flags can-not be interpreted as described in the following,because any explicit write to the PSW register su-persedes the condition flag values, which are im-plicitly generated by the CPU. Explicitly readingthe PSW register supplies a read value which rep-resents the state of the PSW register after execu-tion of the immediately preceding instruction.

Note: After reset, all of the ALU status bits arecleared.

• N-Flag: For most of the ALU operations, the N-flag is set to ’1’, if the most significant bit of the re-sult contains a ’1’, otherwise it is cleared. In thecase of integer operations the N-flag can be inter-preted as the sign bit of the result (negative: N=’1’,positive: N=’0’). Negative numbers are alwaysrepresented as the 2’s complement of the corre-sponding positive number. The range of signednumbers extends from ’–8000h’ to ’+7FFFh’ for theword data type, or from ’–80h’ to ’+7Fh’ for the bytedata type.For Boolean bit operations with only oneoperand the N-flag represents the previous stateof the specified bit. For Boolean bit operations withtwo operands the N-flag represents the logicalXORing of the two specified bits.

• C-Flag: After an addition the C-flag indicates thata carry from the most significant bit of the speci-fied word or byte data type has been generated.After a subtraction or a comparison the C-flag indi-cates a borrow, which represents the logical nega-tion of a carry for the addition.This means that the C-flag is set to ’1’, ifno carryfrom the most significant bit of the specified wordor byte data type has been generated during asubtraction, which is performed internally by theALU as a 2’s complement addition, and the C-flagis cleared when this complement addition causeda carry.The C-flag is always cleared for logical, multiplyand divide ALU operations, because these opera-tions cannot cause a carry anyhow.For shift and rotate operations the C-flag repre-sents the value of the bit shifted out last. If a shift

count of zero is specified, the C-flag will becleared. The C-flag is also cleared for a prioritizeALU operation, because a ’1’ is never shifted outof the MSB during the normalization of an oper-and.For Boolean bit operations with only one operandthe C-flag is always cleared. For Boolean bit oper-ations with two operands the C-flag represents thelogical ANDing of the two specified bits.

• V-Flag: For addition, subtraction and 2’s comple-mentation the V-flag is always set to ’1’, if the re-sult overflows the maximum range of signed num-bers, which are representable by either 16 bits forword operations (’–8000h’ to ’+7FFFh’), or by 8bits for byte operations (’–80h’ to ’+7Fh’), other-wise the V-flag is cleared. Note that the result ofan integer addition, integer subtraction, or 2’scomplement is not valid, if the V-flag indicates anarithmetic overflow.For multiplication and division the V-flag is set to’1’, if the result cannot be represented in a worddata type, otherwise it is cleared. Note that a divi-sion by zero will always cause an overflow. In con-trast to the result of a division, the result of a mul-tiplication is valid regardless of whether the V-flagis set to ’1’ or not.Since logical ALU operations cannot produce aninvalid result, the V-flag is cleared by these opera-tions.

The V-flag is also used as ’Sticky Bit’ for rotateright and shift right operations. With only using theC-flag, a rounding error caused by a shift right op-eration can be estimated up to a quantity of onehalf of the LSB of the result. In conjunction with theV-flag, the C-flag allows evaluating the roundingerror with a finer resolution (see table below).For Boolean bit operations with only one operandthe V-flag is always cleared. For Boolean bit oper-ations with two operands the V-flag represents thelogical ORing of the two specified bits.

Shift Right Rounding Error Evaluation

C-Flag

V-Flag

Rounding Error Quantity

0

0

1

1

0

1

0

1

- No rounding error -

0< Rounding error <1/2 LSB

Rounding error =1/2 LSB

Rounding error >1/2 LSB

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CPU SPECIAL FUNCTION REGISTERS (Cont’d)• Z-Flag: The Z-flag is normally set to ’1’, if the re-sult of an ALU operation equals zero, otherwise itis cleared.For the addition and substraction with carry the Z-flag is only set to ’1’, if the Z-flag already containsa ’1’ and the result of the current ALU operationadditionally equals zero. This mechanism is pro-vided for the support of multiple precision calcula-tions.For Boolean bit operations with only one operandthe Z-flag represents the logical negation of theprevious state of the specified bit. For Boolean bitoperations with two operands the Z-flag repre-sents the logical NORing of the two specified bits.For the prioritize ALU operation the Z-flag indi-cates, if the second operand was zero or not.

• E-Flag: The E-flag can be altered by instruc-tions, which perform ALU or data movement oper-ations. The E-flag is cleared by those instructionswhich cannot be reasonably used for table searchoperations. In all other cases the E-flag is set de-pending on the value of the source operand to sig-nify whether the end of a search table is reachedor not. If the value of the source operand of an in-struction equals the lowest negative number,which is representable by the data format of thecorresponding instruction (’8000h’ for the worddata type, or ’80h’ for the byte data type), the E-flag is set to ’1’, otherwise it is cleared.

• MULIP-Flag: The MULIP-flag will be set to ’1’ byhardware upon the entrance into an interrupt serv-ice routine, when a multiply or divide ALU opera-tion was interrupted before completion. Depend-ing on the state of the MULIP bit, the hardware de-

cides whether a multiplication or division must becontinued or not after the end of an interrupt serv-ice. The MULIP bit is overwritten with the contentsof the stacked MULIP-flag when the return-from-interrupt-instruction (RETI) is executed. This nor-mally means that the MULIP-flag is cleared againafter that.

Note : The MULIP flag is a part of the task environ-ment! When the interrupting service routine doesnot return to the interrupted multiply/divide instruc-tion (ie. in case of a task scheduler that switchesbetween independent tasks), the MULIP flag mustbe saved as part of the task environment and mustbe updated accordingly for the new task beforethis task is entered.

CPU Interrupt Status (IEN, ILVL)

The Interrupt Enable bit allows to globally enable(IEN=’1’) or disable (IEN=’0’) interrupts. The four-bit Interrupt Level field (ILVL) specifies the priorityof the current CPU activity. The interrupt level isupdated by hardware upon entry into an interruptservice routine, but it can also be modified via soft-ware to prevent other interrupts from being ac-knowledged. In case an interrupt level ’15’ hasbeen assigned to the CPU, it has the highest pos-sible priority, and thus the current CPU operationcannot be interrupted except by hardware traps orexternal non-maskable interrupts. For detailsplease refer to chapter “Interrupt and Trap Func-tions”.

After reset all interrupts are globally disabled, andthe lowest priority (ILVL=0) is assigned to the ini-tial CPU activity.

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The Instruction Pointer IPThis register determines the 16-bit intra-segmentaddress of the currently fetched instruction withinthe code segment selected by the CSP register.The IP register is not mapped into the ST10R163’saddress space, and thus it cannot directly be ac-cessed by the programmer. The IP can, however,

be modified indirectly via the stack by means of areturn instruction.

The IP register is implicitly updated by the CPU forbranch instructions and after instruction fetch op-erations.

IP (---- / --) --- Reset Value: 0000h

The Code Segment Pointer CSPThis non-bit addressable register selects the codesegment being used at run-time to access instruc-tions. The lower 8 bits of register CSP select oneof up to 256 segments of 64 Kbytes each, whilethe upper 8 bits are reserved for future use.Code memory addresses are generated by direct-ly extending the 16-bit contents of the IP registerby the contents of the CSP register as shown inthe figure below.In case of the segmented memory mode the se-lected number of segment address bits (7...0, 3...0or 1...0) of register CSP is output on the segmentaddress pins A23/A19/A17...A16 of Port 4 for all

external code accesses. For non-segmentedmemory mode or Single Chip Mode the content ofthis register is not significant, because all code ac-cesses are automatically restricted to segment 0.

Note : The CSP register can only be read but notwritten by data operations. It is, however, modifiedeither directly by means of the JMPS and CALLSinstructions, or indirectly via the stack by means ofthe RETS and RETI instructions.Upon the acceptance of an interrupt or the execu-tion of a software TRAP instruction, the CSP reg-ister is automatically set to zero.

CSP (FE08h / 04h) SFR Reset Value: 0000h

Bit Function

ip Specifies the intra segment offset, from where the current instruction is to be fetched. IP refers tothe current segment <SEGNR>.

5 4 3 2 1 011 10 9 8 7 615 14 13 12

(r)(w)

ip

Bit Function

SEGNRSegment Number

Specifies the code segment, from where the current instruction is to be fetched. SEGNR is ignoredwhen segmentation is disabled.

- -- --

5 4 3 2 1 011 10 9 8 7 615 14 13 12

- - - r-- --

- --

-

SEGNR

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Figure 3-5. Addressing via the Code Segment Pointer

Note: When segmentation is disabled, the IP value is used directly as the 16-bit address.

0

1

255

254

Code Segment

00’0000h

FF’FFFFh

01’0000h

FE’0000h

CSP Register IP Register 00 1515

24/20/18 bit Physical Code Address

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CPU SPECIAL FUNCTION REGISTERS (Cont’d)The Data Page Pointers DPP0, DPP1, DPP2,DPP3

These four non-bit addressable registers select upto four different data pages being active simulta-neously at run-time. The lower 10 bits of eachDPP register select one of the 1024 possible 16-Kbyte data pages while the upper 6 bits are re-served for future use. The DPP registers allow toaccess the entire memory space in pages of 16Kbytes each.

The DPP registers are implicitly used, wheneverdata accesses to any memory location are madevia indirect or direct long 16-bit addressing modes(except for override accesses via EXTended in-structions and PEC data transfers). After reset,the Data Page Pointers are initialized in a way thatall indirect or direct long 16-bit addresses result inidentical 18-bit addresses. This allows to accessdata pages 3...0 within segment 0 as shown in thefigure below. If the user does not want to use anydata paging, no further action is required.

DPP0 (FE00h / 00h) SFR Reset Value: 0000h




Bit Function

DPPxPNData Page Number of DPPx

Specifies the data page selected via DPPx. Only the least significant two bits of DPPx are sig-nificant when segmentation is disabled.

- --

5 4 3 2 1 011 10 9 8 7 615 14 13 12

- rw-- --

- --

-

DPP0PN

- --

5 4 3 2 1 011 10 9 8 7 615 14 13 12

- rw-- --

- --

-

DPP1PN

- --

5 4 3 2 1 011 10 9 8 7 615 14 13 12

- rw-- --

- --

-

DPP2PN

- --

5 4 3 2 1 011 10 9 8 7 615 14 13 12

- rw-- --

- --

-

DPP3PN

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CPU SPECIAL FUNCTION REGISTERS (Cont’d)Data paging is performed by concatenating thelower 14 bits of an indirect or direct long 16-bit ad-dress with the contents of the DDP register select-ed by the upper two bits of the 16-bit address. Thecontent of the selected DPP register specifies oneof the 1024 possible data pages. This data pagebase address together with the 14-bit page offsetforms the physical 24/20/18-bit address.

In case of non-segmented memory mode, only thetwo least significant bits of the implicitly selectedDPP register are used to generate the physicaladdress. Thus, extreme care should be takenwhen changing the content of a DPP register, if a

non-segmented memory model is selected, be-cause otherwise unexpected results could occur.In case of the segmented memory mode the se-lected number of segment address bits (9...2, 5...2or 3...2) of the respective DPP register is output onthe segment address pins A23/A19/A17...A16 ofPort 4 for all external data accesses.A DPP register can be updated via any instruction,which is capable of modifying an SFR.Note : Due to the internal instruction pipeline, anew DPP value is not yet usable for the operandaddress calculation of the instruction immediatelyfollowing the instruction updating the DPP regis-ter.

Figure 3-6. Addressing via the Data Page Pointers

1023

Data Pages 16-bit Data Address015 14

14-bitIntra-Page Address(concatenated withcontent of DPPx)

1022

1021

2

1

0

3 DPP3

DPP2

DPP1

DPP0

1 1

1 0

0 1

0 0

DPP Registers

After reset or with segmentation disabled the DPP registers select data pages 3...0.All of the internal memory is accessible in these cases.

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The Context Pointer CP

This non-bit addressable register is used to selectthe current register context. This means that theCP register value determines the address of thefirst General Purpose Register (GPR) within thecurrent register bank of up to 16 wordwide and/orbytewide GPRs.

Note: It is the user’s responsibility that the physi-cal GPR address specified via CP register plusshort GPR address must always be an internalRAM location. If this condition is not met, unex-pected results may occur.

– Do notsetCP below 00’F600h or above 00’FDFEh– Be careful using the upper GPRs with CP above

00’FDE0hThe CP register can be updated via any instruc-tion which is capable of modifying an SFR.Note : Due to the internal instruction pipeline, anew CP value is not yet usable for GPR addresscalculations of the instruction immediately follow-ing the instruction updating the CP register.The Switch Context instruction (SCXT) allows tosave the content of register CP on the stack andupdating it with a new value in just one machinecycle.

CP (FE10h / 08h) SFR Reset Value: FC00h

Figure 3-7Register Bank Selection via Register CP

Bit Function

cp

Modifiable portion of register CP

Specifies the (word) base address of the current register bank.When writing a value to register CP with bits CP.11...CP.9 = ‘000’, bits CP.11...CP.10 are set to‘11’ by hardware, in all other cases all bits of bit field “cp” receive the written value.

1 01

5 4 3 2 1 011 10 9 8 7 615 14 13 12

rrwr rr

1 1

r

cp

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CPU SPECIAL FUNCTION REGISTERS (Cont’d)Several addressing modes use register CP implic-itly for address calculations. The addressingmodes mentioned below are described in chapter“Instruction Set Summary”.Short 4-Bit GPR Addresses (mnemonic: Rw orRb) specify an address relative to the memory lo-cation specified by the contents of the CP register,ie. the base of the current register bank.Depending on whether a relative word (Rw) orbyte (Rb) GPR address is specified, the short 4-bitGPR address is either multiplied by two or not be-fore it is added to the content of register CP (seefigure below). Thus, both byte and word GPR ac-cesses are possible in this way.GPRs used as indirect address pointers are al-ways accessed wordwise. For some instructions

only the first four GPRs can be used as indirectaddress pointers. These GPRs are specified viashort 2-bit GPR addresses. The respective physi-cal address calculation is identical to that for theshort 4-bit GPR addresses.

Short 8-Bit Register Addresses (mnemonic: regor bitoff) within a range from F0h to FFh interpretthe four least significant bits as short 4-bit GPRaddress, while the four most significant bits are ig-nored. The respective physical GPR address cal-culation is identical to that for the short 4-bit GPRaddresses. For single bit accesses on a GPR, theGPR’s word address is calculated as just de-scribed, but the position of the bit within the wordis specified by a separate additional 4-bit value.

Figure 3-8. Implicit CP Use by Short GPR Addressing Modes

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CPU SPECIAL FUNCTION REGISTERS (Cont’d)The Stack Pointer SPThis non-bit addressable register is used to pointto the top of the internal system stack (TOS). TheSP register is pre-decremented whenever data isto be pushed onto the stack, and it is post-incre-mented whenever data is to be popped from thestack. Thus, the system stack grows from highertoward lower memory locations.Since the least significant bit of register SP is tiedto ’0’ and bits 15 through 12 are tied to ’1’ by hard-ware, the SP register can only contain values from

F000h to FFFEh. This allows to access a physicalstack within the internal RAM of the ST10R163. Avirtual stack (usually bigger) can be realized viasoftware. This mechanism is supported by regis-ters STKOV and STKUN (see respective descrip-tions below).The SP register can be updated via any instruc-tion, which is capable of modifying an SFR.Note : Due to the internal instruction pipeline, aPOP or RETURN instruction must not immediatelyfollow an instruction updating the SP register.

SP (FE12h / 09h) SFR Reset Value: FC00h

Bit Function

spModifiable portion of register SP

Specifies the top of the internal system stack.

1 01

5 4 3 2 1 011 10 9 8 7 615 14 13 12

rrwr rr

1 1

r

sp

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CPU SPECIAL FUNCTION REGISTERS (Cont’d)The Stack Overflow Pointer STKOVThis non-bit addressable register is comparedagainst the SP register after each operation,which pushes data onto the system stack (eg.PUSH and CALL instructions or interrupts) and af-ter each substraction from the SP register. If thecontent of the SP register is less than the contentof the STKOV register, a stack overflow hardwaretrap will occur.Since the least significant bit of register STKOV istied to ’0’ and bits 15 through 12 are tied to ’1’ byhardware, the STKOV register can only containvalues from F000h to FFFEh.The Stack Overflow Trap (entered when (SP) <(STKOV)) may be used in two different ways:• Fatal error indication treats the stack overflowas a system error through the associated trapservice routine. Under these circumstances datain the bottom of the stack may have been overwrit-

ten by the status information stacked upon servic-ing the stack overflow trap.

• Automatic system stack flushing allows to usethe system stack as a ’Stack Cache’ for a biggerexternal user stack. In this case register STKOVshould be initialized to a value, which representsthe desired lowest Top of Stack address plus 12according to the selected maximum stack size.This considers the worst case that will occur,when a stack overflow condition is detected justduring entry into an interrupt service routine.Then, six additional stack word locations are re-quired to push IP, PSW, and CSP for both the in-terrupt service routine and the hardware trap serv-ice routine.

More details about the stack overflow trap serviceroutine and virtual stack management are given inchapter “System Programming”.

STKOV (FE14h / 0Ah) SFR Reset Value: FA00h

Bit Function

stkovModif iable portion of register STKOV

Specifies the lower limit of the internal system stack.

1 01

5 4 3 2 1 011 10 9 8 7 615 14 13 12

rrwr rr

1 1

r

stkov

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CPU SPECIAL FUNCTION REGISTERS (Cont’d)The Stack Underflow Pointer STKUNThis non-bit addressable register is comparedagainst the SP register after each datapop opera-tion from the system stack (eg. POP and RET in-structions) and after each addition to the SP regis-ter. If the content of the SP register is greater thanthe content of the STKUN register, a stack under-flow hardware trap will occur.Since the least significant bit of register STKUN istied to ’0’ and bits 15 through 12 are tied to ’1’ byhardware, the STKUN register can only containvalues from F000h to FFFEh.The Stack Underflow Trap (entered when (SP) >(STKUN)) may be used in two different ways:• Fatal error indication treats the stack underflowas a system error through the associated trapservice routine.• Automatic system stack refilling allows to usethe system stack as a ’Stack Cache’ for a bigger

external user stack. In this case register STKUNshould be initialized to a value, which representsthe desired highest Bottom of Stack address.More details about the stack underflow trap serv-ice routine and virtual stack management are giv-en in chapter “System Programming”.Scope of Stack Limit ControlThe stack limit control realized by the register pairSTKOV and STKUN detects cases where thestack pointer SP is moved outside the definedstack area either by ADD or SUB instructions or byPUSH or POP operations (explicit or implicit, ie.CALL or RET instructions).This control mechanism is not triggered, ie. nostack trap is generated, when– the stack pointer SP is directly updated via MOV

instructions– the limits of the stack area (STKOV, STKUN) are

changed, so that SP is outside of the new limits.

STKUN (FE16h / 0Bh) SFR Reset Value: FC00h

Bit Function

stkunModifiable portion of register STKUN

Specifies the upper limit of the internal system stack.

1 01

5 4 3 2 1 011 10 9 8 7 615 14 13 12

rrwr rr

1 1

r

stkun

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The Multiply/Divide High Register MDH

This register is a part of the 32-bit multiply/divideregister, which is implicitly used by the CPU, whenit performs a multiplication or a division. After amultiplication, this non-bit addressable registerrepresents the high order 16 bits of the 32-bit re-sult. For long divisions, the MDH register must beloaded with the high order 16 bits of the 32-bit div-idend before the division is started. After any divi-sion, register MDH represents the 16-bit remain-der.

Whenever this register is updated via software,the Multiply/Divide Register In Use (MDRIU) flagin the Multiply/Divide Control register (MDC) is setto ’1’.

When a multiplication or division is interrupted be-fore its completion and when a new multiply or di-vide operation is to be performed within the inter-rupt service routine, register MDH must be savedalong with registers MDL and MDC to avoid erro-neous results.

A detailed description of how to use the MDH reg-ister for programming multiply and divide algo-rithms can be found in chapter “System Program-ming”.

The Multiply/Divide Low Register MDL

This register is a part of the 32-bit multiply/divideregister, which is implicitly used by the CPU, whenit performs a multiplication or a division. After amultiplication, this non-bit addressable registerrepresents the low order 16 bits of the 32-bit re-sult. For long divisions, the MDL register must beloaded with the low order 16 bits of the 32-bit divi-dend before the division is started. After any divi-sion, register MDL represents the 16-bit quotient.

Whenever this register is updated via software,the Multiply/Divide Register In Use (MDRIU) flagin the Multiply/Divide Control register (MDC) is setto ’1’. The MDRIU flag is cleared, whenever theMDL register is read via software.

When a multiplication or division is interrupted be-fore its completion and when a new multiply or di-vide operation is to be performed within the inter-rupt service routine, register MDL must be savedalong with registers MDH and MDC to avoid erro-neous results.

A detailed description of how to use the MDL reg-ister for programming multiply and divide algo-rithms can be found in chapter “System Program-ming”.

MDH (FE0Ch / 06h) SFR Reset Value: 0000h

MDL (FE0Eh / 07h) SFR Reset Value: 0000h

Bit Function

mdh Specifies the high order 16 bits of the 32-bit multiply and divide register MD.

Bit Function

mdl Specifies the low order 16 bits of the 32-bit multiply and divide register MD.

5 4 3 2 1 011 10 9 8 7 615 14 13 12

rw

mdh

5 4 3 2 1 011 10 9 8 7 615 14 13 12

rw

mdl

50

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CPU SPECIAL FUNCTION REGISTERS (Cont’d)The Multiply/Divide Control Register MDCThis bit addressable 16-bit register is implicitlyused by the CPU, when it performs a multiplicationor a division. It is used to store the required controlinformation for the corresponding multiply or di-vide operation. Register MDC is updated by hard-ware during each single cycle of a multiply or di-vide instruction.When a division or multiplication was interruptedbefore its completion and the multiply/divide unit isrequired, the MDC register must first be savedalong with registers MDH and MDL (to be able torestart the interrupted operation later), and then itmust be cleared to be prepared for the new calcu-lation. After completion of the new division or mul-

tiplication, the state of the interrupted multiply ordivide operation must be restored.

The MDRIU flag is the only portion of the MDCregister which might be of interest for the user.The remaining portions of the MDC register are re-served for dedicated use by the hardware, andshould never be modified by the user in anotherway as described above. Otherwise, a correctcontinuation of an interrupted multiply or divideoperation cannot be guaranteed.

A detailed description of how to use the MDC reg-ister for programming multiply and divide algo-rithms can be found in chapter “System Program-ming”.

MDC (FF0Eh / 87h) SFR Reset Value: 0000h

Bit Function

MDRIU

Multiply/Divide Register In Use

‘0’:Cleared, when register MDL is read via software.‘1’:Set when register MDL or MDH is written via software, or when a multiplyor divide instruction is executed.

!!Internal Machine Status

The multiply/divide unit uses these bits to control internal operations.Never modify these bits without saving and restoring register MDC.

- !!--

5 4 3 2 1 011 10 9 8 7 615 14 13 12

- r(w)-- --

- --

-

!!!!!!!!!!!!- -

- - r(w) r(w) r(w) r(w) r(w) r(w) r(w)

MDRIU

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CPU SPECIAL FUNCTION REGISTERS (Cont’d)The Constant Zeros Register ZEROSAll bits of this bit-addressable register are fixed to’0’ by hardware. This register can be read only.Register ZEROS can be used as a register-ad-dressable constant of all zeros, ie. for bit manipu-lation or mask generation. It can be accessed viaany instruction, which is capable of addressing aSFR.

The Constant Ones Register ONESAll bits of this bit-addressable register are fixed to’1’ by hardware. This register can be read only.Register ONES can be used as a register-ad-dressable constant of all ones, ie. for bit manipula-tion or mask generation. It can be accessed viaany instruction, which is capable of addressing anSFR.

ZEROS (FF1Ch / 8Eh) SFR Reset Value: 0000h

ONES (FF1Eh / 8Fh) SFR Reset Value: FFFFh

0 0 000

5 4 3 2 1 011 10 9 8 7 615 14 13 12

r rrr rr

0 00

r

0000000 0

r r r r r r r r r

1 1 111

5 4 3 2 1 011 10 9 8 7 615 14 13 12

r rrr rr

1 11

r

1111111 1

r r r r r r r r r

52

February 1996 1/24


ST10R163User Manual

4 - INTERRUPT AND TRAP FUNCTIONS

The architecture of the ST10R163 supports sever-al mechanisms for fast and flexible response toservice requests that can be generated from vari-ous sources internal or external to the microcon-troller.These mechanisms include:Normal Interrupt ProcessingThe CPU temporarily suspends the current pro-gram execution and branches to an interrupt serv-ice routine in order to service an interrupt request-ing device. The current program status (IP, PSW,in segmentation mode also CSP) is saved on theinternal system stack. A prioritization scheme with16 priority levels allows the user to specify the or-der in which multiple interrupt requests are to behandled.

Interrupt Processing via the Peripheral EventController (PEC)A faster alternative to normal software controlledinterrupt processing is servicing an interrupt re-questing device with the ST10R163’s integratedPeripheral Event Controller (PEC). Triggered byan interrupt request, the PEC performs a singleword or byte data transfer between any two loca-tions in segment 0 (data pages 0 through 3)through one of eight programmable PEC ServiceChannels. During a PEC transfer the normal pro-gram execution of the CPU is halted for just 1 in-struction cycle. No internal program status infor-

mation needs to be saved. The same prioritizationscheme is used for PEC service as for normal in-terrupt processing. PEC transfers share the 2highest priority levels.

Trap Functions

Trap functions are activated in response to specialconditions that occur during the execution of in-structions. A trap can also be caused externally bythe Non-Maskable Interrupt pin NMI. Severalhardware trap functions are provided for handlingerroneous conditions and exceptions that ariseduring the execution of an instruction. Hardwaretraps always have highest priority and cause im-mediate system reaction. The software trap func-tion is invoked by the TRAP instruction, whichgenerates a software interrupt for a specified inter-rupt vector. For all types of traps the current pro-gram status is saved on the system stack.

External Interrupt Processing

Although the ST10R163 does not provide dedicat-ed interrupt pins, it allows to connect external in-terrupt sources and provides several mechanismsto react on external events, including standard in-puts, non-maskable interrupts and fast external in-terrupts. These interrupt functions are alternateport functions, except for the non-maskable inter-rupt and the reset input.

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4 - INTERRUPT AND TRAP FUNCTIONS (ST10R163)

4.1 INTERRUPT SYSTEM STRUCTURE

The ST10R163 provides 20 separate interruptnodes that may be assigned to 16 priority levels.In order to support modular and consistent soft-ware design techniques, each source of an inter-rupt or PEC request is supplied with a separate in-terrupt control register and interrupt vector. Thecontrol register contains the interrupt request flag,the interrupt enable bit, and the interrupt priority ofthe associated source. Each source request is ac-tivated by one specific event, depending on theselected operating mode of the respective device.The only exceptions are the two serial channels ofthe ST10R163, where an error interrupt requestcan be generated by different kinds of error. How-ever, specific status flags which identify the type oferror are implemented in the serial channels’ con-trol registers.The ST10R163 provides a vectored interrupt sys-tem. In this system specific vector locations in thememory space are reserved for the reset, trap,and interrupt service functions. Whenever a re-quest occurs, the CPU branches to the locationthat is associated with the respective interruptsource. This allows direct identification of thesource that caused the request. The only excep-tions are the class B hardware traps, which allshare the same interrupt vector. The status flagsin the Trap Flag Register (TFR) can then be usedto determine which exception caused the trap. Forthe special software TRAP instruction, the vectoraddress is specified by the operand field of the in-struction, which is a seven bit trap number.

The reserved vector locations build a jump table inthe low end of the ST10R163’s address space(segment 0). The jump table is made up of the ap-propriate jump instructions that transfer control tothe interrupt or trap service routines, which maybe located anywhere within the address space.The entries to the jump table are located at thelowest addresses in code segment 0 of the ad-dress space. Each entry occupies 2 words, exceptfor the reset vector and the hardware trap vectors,which occupy 4 or 8 words.

The table below lists all sources that are capableof requesting interrupt or PEC service in theST10R163, the associated interrupt vectors, theirlocations and the associated trap numbers. It alsolists the mnemonics of the affected Interrupt Re-quest flags and their corresponding Interrupt Ena-ble flags. The mnemonics are composed of a partthat specifies the respective source, followed by apart that specifies their function (IR=Interrupt Re-quest flag, IE=Interrupt Enable flag).

Note: The two X-Peripheral nodes in the table are pre-pared to accept interrupt requests, one of them isconnected to the PLL Unlock interrupt request andanother one is connected to the SSP X-PeripheralReceive/Transmit interrupt request.The “External Interrupt Nodes” use naming conven-tions that are compatible with the respectiveST10F167 and ST10R165 interrupt nodes

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INTERRUPT SYSTEM STRUCTURE(Cont’d)

Note: Each entry of the interrupt vector table provides room for two word instructions or one doubleword instruction. Therespective vector location results from multiplying the trap number by 4 (4 bytes per entry).

Source of Interrupt or PECService Request

RequestFlag

EnableFlag

InterruptVector

VectorLocation

TrapNumber

External Interrupt 0 CC8IR CC8IE CC8INT 00’0060h 18h / 24

External Interrupt 1 CC9IR CC9IE CC9INT 00’0064h 19h / 25

External Interrupt 2 CC10IR CC10IE CC10INT 00’0068h 1Ah / 26

External Interrupt 3 CC11IR CC11IE CC11INT 00’006Ch 1b h/ 27

External Interrupt 4 CC12IR CC12IE CC12INT 00’0070h 1Ch / 28

External Interrupt 5 CC13IR CC13IE CC13INT 00’0074h 1Dh / 29

External Interrupt 6 CC14IR CC14IE CC14INT 00’0078h 1Eh / 30

External Interrupt 7 CC15IR CC15IE CC15INT 00’007Ch 1Fh / 31

GPT1 Timer 2 T2IR T2IE T2INT 00’0088h 22h / 34

GPT1 Timer 3 T3IR T3IE T3INT 00’008Ch 23h / 35




GPT2 CAPREL Register CRIR CRIE CRINT 00’009Ch 27h / 39

ASC0 Transmit S0TIR S0TIE S0TINT 00’00A8h 2Ah / 42

ASC0 Transmit Buffer S0TBIR S0TBIE S0TBINT 00’011Ch 47h / 71

ASC0 Receive S0RIR S0RIE S0RINT 00’00ACh 2Bh / 43

ASC0 Error S0EIR S0EIE S0EINT 00’00B0h 2Ch / 44

X-Peripheral Node 1 XP1IR XP1IE XP1INT 00’0104h 41h / 65

X-Peripheral Node 3 XP3IR XP3IE XP3INT 00’010Ch 43h / 67

55

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INTERRUPT SYSTEM STRUCTURE(Cont’d)The table below lists the vector locations for hard-ware traps and the corresponding status flags inregister TFR. It also lists the priorities of trap serv-ice for cases, where more than one trap conditionmight be detected within the same instruction. Af-ter any reset (hardware reset, software reset in-struction SRST, or reset by watchdog timer over-flow) program execution starts at the reset vectorat location 00’0000h. Reset conditions have prior-ity over every other system activity and thereforehave the highest priority (trap priority III).

Software traps may be performed from any vectorlocation between 00’0000h and 00’01FCh. A serv-ice routine entered via a software TRAP instruc-tion is always executed on the current CPU prioritylevel which is indicated in bit field ILVL in registerPSW. This means that routines entered via thesoftware TRAP instruction can be interrupted byall hardware traps or higher level interrupt re-quests.

Exception ConditionTrapFlag

TrapVector

VectorLocation

TrapNumber

TrapPriority

Reset Functions:Hardware ResetSoftware ResetWatchdog Timer Overflow

RESETRESETRESET

00’0000h00’0000h00’0000h

00h00h00h

IIIIIIIII

Class A Hardware Traps:Non-Maskable InterruptStack OverflowStack Underflow

NMISTKOFSTKUF

NMITRAPSTOTRAPSTUTRAP

00’0008h00’0010h00’0018h

02h04h06h

IIIIII

Class B Hardware Traps:Undefined OpcodeProtected Instruction FaultIllegal Word Operand AccessIllegal Instruction AccessIllegal External Bus Access

UNDOPCPRTFLTILLOPAILLINAILLBUS

BTRAPBTRAPBTRAPBTRAPBTRAP

00’0028h00’0028h00’0028h00’0028h00’0028h

0Ah0Ah0Ah0Ah0Ah

IIIII

Reserved [2Ch – 3Ch] [0Bh – 0Fh]

Software TrapsTRAP Instruction

Any[00’0000h –00’01FCh]in stepsof 4h

Any[00h – 7Fh]

CurrentCPU Priority

56

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Normal Interrupt Processing and PEC Service

During each instruction cycle one out of all sourc-es which require PEC or interrupt processing isselected according to its interrupt priority. This pri-ority of interrupts and PEC requests is program-mable in two levels. Each requesting source canbe assigned to a specific priority. A second level(“group priority”) allows to specify an internal orderfor simultaneous requests from a group of differ-ent sources on the same priority level. At the endof each instruction cycle the source request withthe highest current priority will be determined bythe interrupt system. This request will then beserviced, if its priority is higher than the currentCPU priority in register PSW.

Interrupt System Register Description

Interrupt processing is controlled globally by regis-ter PSW through a general interrupt enable bit(IEN) and the CPU priority field (ILVL). Additional-ly the different interrupt sources are controlled in-dividually by their specific interrupt control regis-ters (...IC). Thus, the acceptance of requests bythe CPU is determined by both the individual inter-rupt control registers and the PSW. PEC servicesare controlled by the respective PECCx register

and the source and destination pointers, whichspecify the task of the respective PEC servicechannel.

Interrupt Control Registers

All interrupt control registers are organized identi-cally. The lower 8 bits of an interrupt control regis-ter contain the complete interrupt status informa-tion of the associated source, which is requiredduring one round of prioritization, the upper 8 bitsof the respective register are reserved.. All inter-rupt control registers are bit-addressable and allbits can be read or written via software. This al-lows each interrupt source to be programmed ormodified with just one instruction. When access-ing interrupt control registers through instructionswhich operate on word data types, their upper 8bits (15...8) will return zeros, when read, and willdiscard written data.

The layout of the Interrupt Control registers shownbelow applies to each xxIC register, where xxstands for the mnemonic for the respectivesource.

xxIC (yyyyh / zzh) <SFR area> Reset Value: - - 00h

Bit Function

GLVL

Group Level

Defines the internal order for simultaneous requests of the same priority.3: Highest group priority0: Lowest group priority

ILVL

Interrupt Priority Level

Defines the priority level for the arbitration of requests.Fh: Highest priority level0h: Lowest priority level

xxIE

Interrupt Enable Control Bit (individually enables/disables a specific source)

‘0’: Interrupt request is disabled

‘1’: Interrupt Request is enabled

xxIR

Interrupt Request Flag

‘0’: No request pending

‘1’: This source has raised an interrupt request

5 4 3 2 1 011 10 9 8 7 615 14 13 12

rw rw- - - - rw rw- - - -

xxIExxIR GLVLILVL

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The Interrupt Request Flag is set by hardwarewhenever a service request from the respectivesource occurs. It is cleared automatically upon en-try into the interrupt service routine or upon a PECservice. In the case of PEC service the InterruptRequest flag remains set, if the COUNT field inregister PECCx of the selected PEC channel dec-rements to zero. This allows a normal CPU inter-rupt to respond to a completed PEC block trans-fer.Note: Modifying the Interrupt Request flag via software

causes the same effects as if it had been set orcleared by hardware.

Interrupt Priority Level and Group Level

The four bits of bit field ILVL specify the prioritylevel of a service request for the arbitration of si-multaneous requests. The priority increases withthe numerical value of ILVL, so 0000b is the low-est and 1111b is the highest priority level.

When more than one interrupt request on a specif-ic level becomes active at the same time, the val-ues in the respective bit fields GLVL are used forsecond level arbitration to select one request forbeing serviced. Again the group priority increaseswith the numerical value of GLVL, so 00b is thelowest and 11b is the highest group priority.

Note: All interrupt request sources that are enabled andprogrammed to the same priority level must alwaysbe programmed to different group priorities. Other-wise an incorrect interrupt vector will be generated.

Upon entry into the interrupt service routine, thepriority level of the source that won the arbitrationand who’s priority level is higher than the currentCPU level, is copied into bit field ILVL of register

PSW after pushing the old PSW contents on thestack.

The interrupt system of the ST10R163 allowsnesting of up to 15 interrupt service routines of dif-ferent priority levels (level 0 cannot be arbitrated).

Interrupt requests that are programmed to prioritylevels 15 or 14 (ie, ILVL=111Xb) will be servicedby the PEC, unless the COUNT field of the asso-ciated PECC register contains zero. In this casethe request will be serviced by normal interruptprocessing instead. Interrupt requests that areprogrammed to priority levels 13 through 1 will al-ways be serviced by normal interrupt processing.

Note: Priority level 0000b is the default level of the CPU.Therefore a request on level 0 will never be serv-iced, because it can never interrupt the CPU. How-ever, an enabled interrupt request on level 0000bwill terminate the ST10R163’s Idle mode and reac-tivate the CPU.

For interrupt requests which are to be serviced bythe PEC, the associated PEC channel number isderived from the respective ILVL (LSB) and GLVL(see figure below). So programming a source topriority level 15 (ILVL=1111b) selects the PECchannel group 7...4, programming a source to pri-ority level 14 (ILVL=1110b) selects the PEC chan-nel group 3...0. The actual PEC channel number isthen determined by the group priority field GLVL.

Simultaneous requests for PEC channels are pri-oritized according to the PEC channel number,where channel 0 has lowest and channel 7 hashighest priority.

Note: All sources that request PEC service must be pro-grammed to different PEC channels. Otherwise anincorrect PEC channel may be activated.

Figure 4-1. Priority Levels and PEC Channels

InterruptControl Register

PEC Control

58

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INTERRUPT SYSTEM STRUCTURE(Cont’d)The table below shows in a few examples, which action is executed with a given programming of an in-terrupt control register.

Note: All requests on levels 13...1 cannot initiate PEC transfers. They are always serviced by an interrupt service routine.No PECC register is associated and no COUNT field is checked.

Interrupt Control Functions in the PSW

The Processor Status Word (PSW) is functionallydivided into 2 parts: the lower byte of the PSW ba-sically represents the arithmetic status of theCPU, the upper byte of the PSW controls the inter-

rupt system of the ST10R163 and the arbitrationmechanism for the external bus interface.

Note: Pipeline effects have to be considered when ena-bling/disabling interrupt requests via modifications ofregister PSW (see chapter “The Central ProcessingUnit”).

Priority Level Type of Service

ILVL GLVL COUNT = 00h COUNT ≠ 00h

1 1 1 1 1 1 CPU interrupt,level 15, group priority 3

PEC service,

channel 7


PEC service,

channel 6


PEC service,

channel 2

1 1 0 1 1 0CPU interrupt,level 13, group priority 2

CPU interrupt,level 13, group priority 2





0 0 0 0 X X No service! No service!

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PSW (FF10h / 88h) SFR Reset Value: 0000h

CPU Priority ILVL defines the current level for theoperation of the CPU. This bit field reflects the pri-ority level of the routine that is currently executed.Upon the entry into an interrupt service routine thisbit field is updated with the priority level of the re-quest that is being serviced. The PSW is saved onthe system stack before. The CPU level deter-mines the minimum interrupt priority level that willbe serviced. Any request on the same or a lowerlevel will not be acknowledged.The current CPU priority level may be changed viasoftware to control which interrupt request sourc-es will be acknowledged.

PEC transfers do not really interrupt the CPU, butrather “steal” a single cycle, so PEC services donot influence the ILVL field in the PSW.

Hardware traps switch the CPU level to maximumpriority (ie. 15) so no interrupt or PEC requests willbe acknowledged while an exception trap serviceroutine is executed.Note: The TRAP instruction does not change the CPU

level, thus software invoked trap service routinesmay be interrupted by higher requests.

Interrupt Enable bit IEN globally enables or disa-bles PEC operation and the acceptance of inter-rupts by the CPU. When IEN is cleared, no inter-rupt requests are accepted by the CPU. When IENis set to ’1’, all interrupt sources, which have beenindividually enabled by the interrupt enable bits intheir associated control registers, are globally en-abled.Note: Traps are non-maskable and are therefore not af-

fected by the IEN bit.

Bit Function

N, C, V, Z, E,MULIP, USR0

CPU status flags (Described in section “The Central Processing Unit”)

Define the current status of the CPU (ALU, multiplication unit).

HLDENHOLD Enable (Enables External Bus Arbitration)

0: Bus arbitration disabled, P6.7...P6.5 may be used for general purpose IO1: Bus arbitration enabled, P6.7...P6.5 serve as BREQ, HLDA, HOLD, resp.

ILVL

CPU Priority Level

Defines the current priority level for the CPUFh: Highest priority level0h: Lowest priority level

IEN

Interrupt Enable Control Bit (globally enables/disables interrupt requests)

‘0’: Interrupt requests are disabled

‘1’: Interrupt requests are enabled

HLDEN -

MULIPUSR0 NZ CVE

5 4 3 2 1 011 10 9 8 7 615 14 13 12

rw rw rw rwrw rw rw-rw -rw

IEN --ILVL

rw

60

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4.2 OPERATION OF THE PEC CHANNELS

The ST10R163’s Peripheral Event Controller(PEC) provides 8 PEC service channels, whichmove a single byte or word between two locationsin segment 0 (data pages 3...0). This is the fastestpossible interrupt response and in many cases issufficient to service the respective peripheral re-quest (eg. serial channels, etc.). Each channel is

controlled by a dedicated PEC Channel Coun-ter/Control register (PECCx) and a pair of pointersfor source (SRCPx) and destination (DSTPx) ofthe data transfer.

The PECC registers control the action that is per-formed by the respective PEC channel.

PECCx (FECyh / 6zh, see table) SFR Reset Value: 0000h

PEC Control Register Addresses

Byte/Word Transfer bit BWT controls, if a byte ora word is moved during a PEC service cycle. This

selection controls the transferred data size andthe increment step for the modified pointer.

Bit Function

COUNTPEC Transfer CountCounts PEC transfers and influences the channel’s action (see table below)

BWTByte / Word Transfer Selection0: Transfer a Word1: Transfer a Byte

INC

Increment Control (Modification of SRCPx or DSTPx)0 0: Pointers are not modified0 1: Increment DSTPx by 1 or 2 (BWT)1 0: Increment SRCPx by 1 or 2 (BWT)1 1: Reserved. Do not use this combination. (changed to 10 by hardware)

Register Address Reg. Space Register Address Reg. Space

PECC0 FEC0h / 60h SFR PECC4 FEC8h / 64h SFR

PECC1 FEC2h / 61h SFR PECC5 FECAh / 65h SFR

PECC2 FEC4h / 62h SFR PECC6 FECCh / 66h SFR

PECC3 FEC6h / 63h SFR PECC7 FECEh / 67h SFR

--

5 4 3 2 1 011 10 9 8 7 615 14 13 12

rwrwrw

- BWT

-----

-- INC COUNT

61

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OPERATION OF THE PEC CHANNELS (Cont’d)Increment Control Field INC specifies if one ofthe PEC pointers is incremented after the PECtransfer. It is not possible to increment both point-ers, however. If the pointers are not modified(INC=00), the respective channel will alwaysmove data from the same source to the same des-tination.

Note: The reserved combination 11 is changed to 10 byhardware. However, it is not recommended to usethis combination.

The PEC Transfer Count Field COUNT controlsthe action of a respective PEC channel, where thecontent of bit field COUNT at the time the requestis activated selects the action. COUNT may allow

a specified number of PEC transfers, unlimitedtransfers or no PEC service at all.The table below summarizes, how the COUNTfield itself, the interrupt requests flag IR and thePEC channel action depends on the previous con-tent of COUNT.The PEC transfer counter allows to service aspecified number of requests by the respectivePEC channel, and then (when COUNT reaches00h) activate the interrupt service routine, which isassociated with the priority level. After each PECtransfer the COUNT field is decremented and therequest flag is cleared to indicate that the requesthas been serviced.

Note: After PEC Service

Continuous transfers are selected by the valueFFh in bit field COUNT. In this case COUNT is notmodified and the respective PEC channel servicesany request until it is disabled again.

When COUNT is decremented from 01h to 00h af-ter a transfer, the request flag is not cleared, whichgenerates another request from the same source.When COUNT already contains the value 00h, therespective PEC channel remains idle and the as-sociated interrupt service routine is activated in-stead. This allows to choose, if a level 15 or 14 re-

quest is to be serviced by the PEC or by the inter-rupt service routine.

Note: PEC transfers are only executed, if their priority lev-el is higher than the CPU level, ie. only PEC chan-nels 7...4 are processed, while the CPU executeson level 14.All interrupt request sources that are enabled andprogrammed for PEC service should use differentchannels. Otherwise only one transfer will be per-formed for all simultaneous requests. WhenCOUNT is decremented to 00h, and the CPU is tobe interrupted, an incorrect interrupt vector will begenerated.

COUNT COUNT(1) IR after PECservice

Action of PEC Channel and Comments

FFh FFh ‘0’Move a Byte / WordContinuous transfer mode, ie. COUNT is not modified

FEh..02h FDh..01h ‘0’ Move a Byte / Word and decrement COUNT

01h 00h ‘1’Move a Byte / WordLeave request flag set, which triggers another request

00h 00h ‘1’No action!Activate interrupt service routine rather than PEC channel.

62

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OPERATION OF THE PEC CHANNELS (Cont’d)The source and destination pointers specifiythe locations between which the data is to bemoved. A pair of pointers (SRCPx and DSTPx) isassociated with each of the 8 PEC channels.These pointers do not reside in specific SFRs, butare mapped into the internal RAM of theST10R163 just below the bit-addressable area(see figure below).

PEC data transfers do not use the data pagepointers DPP3...DPP0. The PEC source and des-tination pointers are used as 16-bit intra-segmentaddresses within segment 0, so that data can be

transferred between any two locations within thefirst four data pages 3...0.The pointer locations for inactive PEC channelsmay be used for general data storage. Only the re-quired pointers occupy RAM locations.

Note: If word data transfer is selected for a specific PECchannel (ie. BWT=’0’), the respective source anddestination pointers must both contain a valid wordaddress which points to an even byte boundary.Otherwise the Illegal Word Access trap will be in-voked, when this channel is used.

Figure 1-2. Mapping of PEC Pointers into the Internal RAM

DSTP7 00’FCFEh

SRCP7 00’FCFCh

DSTP6 00’FCFAh

SRCP6 00’FCF8h

DSTP5 00’FCF6h

SRCP5 00’FCF4h

DSTP4 00’FCF2h

SRCP4 00’FCF0h

DSTP3 00’FCEEh

SRCP3 00’FCECh

DSTP2 00’FCEAh

SRCP2 00’FCE8h

DSTP1 00’FCE6h

SRCP1 00’FCE4h

DSTP0 00’FCE2h

SRCP0 00’FCE0h

RAM RAM

AddressAddress

63

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4.3 PRIORITIZATION OF INTERRUPT AND PEC SERVICE REQUESTS

Interrupt and PEC service requests from all sourc-es can be enabled, so they are arbitrated andserviced (if chosen), or they may be disabled, sotheir requests are disregarded and not serviced.

Enabling and disabling interrupt requests maybe done via three mechanisms:

Control Bits allow to switch each individualsource “ON” or “OFF”, so it may generate a re-quest or not. The control bits (xxIE) are located inthe respective interrupt control registers. All inter-rupt requests may be enabled or disabled general-ly via bit IEN in register PSW. This control bit is the“main switch” that selects, if requests from anysource are accepted or not.For a specific request to be arbitrated the respec-tive source’s enable bit and the global enable bitmust both be set.

The Priority Level automatically selects a certaingroup of interrupt requests that will be acknowl-edged, disclosing all other requests. The prioritylevel of the source that won the arbitration is com-pared against the CPU’s current level and thesource is only serviced, if its level is higher thanthe current CPU level. Changing the CPU level toa specific value via software blocks all requests onthe same or a lower level. An interrupt source thatis assigned to level 0 will be disabled and never beserviced.

The ATOMIC and EXTend instructions auto-matically disable all interrupt requests for the du-ration of the following 1...4 instructions. This isuseful eg. for semaphore handling and does notrequire to re-enable the interrupt system after the

unseparable instruction sequence (see chapter“System Programming”).Interrupt Class ManagementAn interrupt class covers a set of interrupt sourceswith the same importance, ie. the same priorityfrom the system’s viewpoint. Interrupts of thesame class must not interrupt each other. TheST10R163 supports this function with two fea-tures:Classes with up to 4 members can be establishedby using the same interrupt priority (ILVL) and as-signing a dedicated group level (GLVL) to eachmember. This functionality is built-in and handledautomatically by the interrupt controller.Classes with more than 4 members can be estab-lished by using a number of adjacent interrupt pri-orities (ILVL) and the respective group levels (4per ILVL). Each interrupt service routine within thisclass sets the CPU level to the highest interruptpriority within the class. All requests from thesame or any lower level are blocked now, ie. norequest of this class will be accepted.The example below establishes 3 interrupt class-es which cover 2 or 3 interrupt priorities, depend-ing on the number of members in a class. A level 6interrupt disables all other sources in class 2 bychanging the current CPU level to 8, which is thehighest priority (ILVL) in class 2. Class 1 requestsor PEC requests are still serviced in this case.The 24 interrupt sources (excluding PEC re-quests) are so assigned to 3 classes of priorityrather than to 7 different levels, as the hardwaresupport would do.

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PRIORITIZATION OF INTERRUPT AND PEC SERVICE REQUESTS(Cont’d)Software controlled Interrupt Classes (Example)

ILVL(Priority)

GLVLInterpretation

3 2 1 0

15PEC service on up to 8 channels

14

13

12 X X X X Interrupt Class 18 sources on 2 levels11 X X X X

10

9

8 X X X XInterrupt Class 210 sources on 3 levels

7 X X X X

6 X X

5 X X X X Interrupt Class 36 sources on 2 levels4 X X

3

2

1

0 No service!

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4.4 SAVING THE STATUS DURING INTERRUPT SERVICE

Before an interrupt request that has been arbitrat-ed is actually serviced, the status of the currenttask is automatically saved on the system stack.The CPU status (PSW) is saved along with the lo-cation, where the execution of the interrupted taskis to be resumed after returning from the serviceroutine. This return location is specified throughthe Instruction Pointer (IP) and, in case of a seg-mented memory model, the Code Segment Point-er (CSP). Bit SGTDIS in register SYSCON con-trols, how the return location is stored.The system stack receives the PSW first, followedby the IP (unsegmented) or followed by CSP andthen IP (segmented mode). This optimizes the us-age of the system stack, if segmentation is disa-bled.The CPU priority field (ILVL in PSW) is updatedwith the priority of the interrupt request that is to beserviced, so the CPU now executes on the newlevel. If a multiplication or division was in progressat the time the interrupt request was acknowl-edged, bit MULIP in register PSW is set to ‘1’. In

this case the return location that is saved on thestack is not the next instruction in the instructionflow, but rather the multiply or divide instruction it-self, as this instruction has been interrupted andwill be completed after returning from the serviceroutine.

The interrupt request flag of the source that is be-ing serviced is cleared. The IP is loaded with thevector associated with the requesting source (theCSP is cleared in case of segmentation) and thefirst instruction of the service routine is fetchedfrom the respective vector location, which is ex-pected to branch to the service routine itself. Thedata page pointers and the context pointer are notaffected.

When the interrupt service routine is left (RETI isexecuted), the status information is popped fromthe system stack in the reverse order, taking intoaccount the value of bit SGTDIS.

Figure 1-3. Task Status saved on the System Stack

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4.5 SAVING THE STATUS DURING INTERRUPTSERVICE

Context Switching

An interrupt service routine usually saves all theregisters it uses on the stack, and restores thembefore returning. The more registers a routine us-es, the more time is wasted with saving and re-storing. The ST10R163 allows to switch the com-plete bank of CPU registers (GPRs) with a singleinstruction, so the service routine executes withinits own, separate context.The instruction “SCXT CP, #New_Bank” pushesthe content of the context pointer (CP) on the sys-tem stack and loads CP with the immediate value“New_Bank”, which selects a new register bank.The service routine may now use its “own regis-ters”. This register bank is preserved, when theservice routine terminates, ie. its contents areavailable on the next call.Before returning (RETI) the previous CP is simplyPOPped from the system stack, which returns theregisters to the original bank.Note: The first instruction following the SCXT instruction

must not use a GPR.

Resources that are used by the interrupting pro-gram must eventually be saved and restored, eg.the DPPs and the registers of the MUL/DIV unit.

4.6 INTERRUPT RESPONSE TIMES

The interrupt response time defines the time froman interrupt request flag of an enabled interruptsource being set until the first instruction (I1) beingfetched from the interrupt vector location. The ba-sic interrupt response time for the ST10R163 is 3instruction cycles.All instructions in the pipeline including instructionN (during which the interrupt request flag is set)are completed before entering the service routine.The actual execution time for these instructions(eg. waitstates) therefore influences the interruptresponse time.In the figure below the respective interrupt requestflag is set in cycle 1 (fetching of instruction N). Theindicated source wins the prioritization round (dur-ing cycle 2). In cycle 3 a TRAP instruction is inject-ed into the decode stage of the pipeline, replacinginstruction N+1 and clearing the source’s interruptrequest flag to ’0’. Cycle 4 completes the injectedTRAP instruction (save PSW, IP and CSP, if seg-mented mode) and fetches the first instruction (I1)from the respective vector location.All instructions that entered the pipeline after set-ting of the interrupt request flag (N+1, N+2) will beexecuted after returning from the interrupt serviceroutine.The minimum interrupt response time is 5 states(250 ns @ 20 MHz CPU clock). This requires pro-gram execution with the fastest bus configuration(16-bit, demultiplexed, no wait states), no externaloperand read requests and setting the interrupt re-quest flag during the last state of an instruction cy-cle. When the interrupt request flag is set duringthe first state of an instruction cycle, the minimuminterrupt response time under these conditions is6 state times (300 ns @ 20 MHz CPU clock).The interrupt response time is increased by all de-lays of the instructions in the pipeline that are exe-cuted before entering the service routine (includ-ing N).

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4.7 INTERRUPT RESPONSE TIMES

Figure 1-4. Pipeline Diagram for Interrupt Response Time

• When internal hold conditions between instruc-tion pairs N-2/N-1 or N-1/N occur, or instruction Nexplicitly writes to the PSW or the SP, the mini-mum interrupt response time may be extended by1 state time for each of these conditions.• In case instruction N reads the PSW and instruc-tion N-1 has an effect on the condition flags, theinterrupt response time may additionally be ex-tended by 2 state times.Any reference to external locations increases theinterrupt response time due to pipeline related ac-cess priorities. The following conditions have to beconsidered:• Instruction fetch from an external location• Operand read from an external location• Result write-back to an external locationDepending on where the instructions, source anddestination operands are located, there are anumber of combinations. Note, however, that onlyaccess conflicts contribute to the delay.A few examples illustrate these delays:• The worst case interrupt response time includingexternal accesses will occur, when instructions N,N+1 and N+2 are executed out of external memo-ry, instructions N-1 and N require external oper-and read accesses, instructions N-3 through N

write back external operands, and the interruptvector also points to an external location. In thiscase the interrupt response time is the time to per-form 9 word bus accesses, because instruction I1cannot be fetched via the external bus until allwrite, fetch and read requests of preceding in-structions in the pipeline are terminated.

• When instructions N, N+1 and N+2 are executedout of external memory and the interrupt vectoralso points to an external location, but all oper-ands for instructions N-3 through N are in internalmemory, then the interrupt response time is thetime to perform 3 word bus accesses.

After an interrupt service routine has been termi-nated by executing the RETI instruction, and if fur-ther interrupts are pending, the next interrupt serv-ice routine will not be entered until at least two in-struction cycles have been executed of the pro-gram that was interrupted. In most cases two in-structions will be executed during this time. Onlyone instruction will typically be executed, if the firstinstruction following the RETI instruction is abranch instruction (without cache hit) or if it is exe-cuted out of the internal RAM.Note: A bus access in this context also includes delays

caused by an external READY signal or by bus ar-bitration (HOLD mode).

Pipeline Stage Cycle 1 Cycle 2 Cycle 3 Cycle 4

FETCH N N + 1 N + 2 I1

DECODE N - 1 N TRAP (1) TRAP (2)

EXECUTE N - 2 N - 1 N TRAP

WRITEBACK N - 3 N - 2 N - 1 N

Interrupt Response Time

10

IR-Flag

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INTERRUPT RESPONSE TIMES (Cont’d)

4.7.1 PEC Response Times

The PEC response time defines the time from aninterrupt request flag of an enabled interruptsource being set until the PEC data transfer beingstarted. The basic PEC response time for theST10R163 is 2 instruction cycles.

In the figure below the respective interrupt requestflag is set in cycle 1 (fetching of instruction N). Theindicated source wins the prioritization round (dur-ing cycle 2). In cycle 3 a PEC transfer “instruction”is injected into the decode stage of the pipeline,suspending instruction N+1 and clearing thesource’s interrupt request flag to ’0’. Cycle 4 com-pletes the injected PEC transfer and resumes theexecution of instruction N+1.

All instructions that entered the pipeline after set-ting of the interrupt request flag (N+1, N+2) will beexecuted after the PEC data transfer.Note: When instruction N reads any of the PEC control

registers PECC7...PECC0, while a PEC requestwins the current round of prioritization, this round isrepeated and the PEC data transfer is started onecycle later.

The minimum PEC response time is 3 states (150ns @ 20 MHz CPU clock). This requires programexecution with the fastest bus configuration (16-bit, demultiplexed, no wait states), no external op-erand read requests and setting the interrupt re-quest flag during the last state of an instruction cy-cle. When the interrupt request flag is set duringthe first state of an instruction cycle, the minimumPEC response time under these conditions is 4state times (200 ns @ 20 MHz CPU clock).

Figure 1-5. Pipeline Diagram for PEC Response Time

Pipeline Stage Cycle 1 Cycle 2 Cycle 3 Cycle 4

FETCH N N + 1 N + 2 N + 2

DECODE N - 1 N PEC N + 1

EXECUTE N - 2 N - 1 N PEC

WRITEBACK N - 3 N - 2 N - 1 N

PEC Response Time

10

IR-Flag

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INTERRUPT RESPONSE TIMES (Cont’d)The PEC response time is increased by all delaysof the instructions in the pipeline that are executedbefore starting the data transfer (including N).

• When internal hold conditions between instruc-tion pairs N-2/N-1 or N-1/N occur, the minimumPEC response time may be extended by 1 statetime for each of these conditions.

• In case instruction N reads the PSW and instruc-tion N-1 has an effect on the condition flags, thePEC response time may additionally be extendedby 2 state times.

Any reference to external locations increases thePEC response time due to pipeline related accesspriorities. The following conditions have to be con-sidered:

• Instruction fetch from an external location• Operand read from an external location• Result write-back to an external location

Depending on where the instructions, source anddestination operands are located, there are anumber of combinations. Note, however, that onlyaccess conflicts contribute to the delay.

A few examples illustrate these delays:• The worst case interrupt response time includingexternal accesses will occur, when instructions Nand N+1 are executed out of external memory, in-structions N-1 and N require external operandread accesses and instructions N-3, N-2 and N-1write back external operands. In this case the PECresponse time is the time to perform 7 word busaccesses.• When instructions N and N+1 are executed outof external memory, but all operands for instruc-tions N-3 through N-1 are in internal memory, thenthe PEC response time is the time to perform 1word bus access plus 2 state times.Once a request for PEC service has been ac-knowledged by the CPU, the execution of the nextinstruction is delayed by 2 state times plus the ad-ditional time it might take to fetch the source oper-and from external memory and to write the desti-nation operand over the external bus in an exter-nal program environment.Note: A bus access in this context also includes delays

caused by an external READY signal or by bus ar-bitration (HOLD mode).

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4.8 EXTERNAL INTERRUPTS

Although the ST10R163 has no dedicated INTRinput pins, it provides many possibilities to reacton external asynchronous events by using anumber of IO lines for interrupt input. The interruptfunction may either be combined with the pin’smain function or may be used instead of it, ie. if themain pin function is not required.Interrupt signals may be connected to:• T4IN, T2IN, the timer input pins,• CAPIN, the capture input of GPT2For each of these pins either a positive, a nega-tive, or both a positive and a negative externaltransition can be selected to cause an interrupt orPEC service request. The edge selection is per-formed in the control register of the peripheral de-vice associated with the respective port pin. Theperipheral must be programmed to a specific op-erating mode to allow generation of an interrupt bythe external signal. The priority of the interrupt re-quest is determined by the interrupt control regis-ter of the respective peripheral interrupt source,and the interrupt vector of this source will be usedto service the external interrupt request.Note: In order to use any of the listed pins as external in-

terrupt input, it must be switched to input mode viaits direction control bit DPx.y in the respective portdirection control register DPx.

Pins T2IN or T4IN can be used as external inter-rupt input pins when the associated auxiliary timerT2 or T4 in block GPT1 is configured for capturemode. This mode is selected by programming themode control fields T2M or T4M in control regis-ters T2CON or T4CON to 101b. The active edgeof the external input signal is determined by bitfields T2I or T4I. When these fields are pro-grammed to X01b, interrupt request flags T2IR orT4IR in registers T2IC or T4IC will be set on a pos-

itive external transition at pins T2IN or T4IN, re-spectively. When T2I or T4I are programmed toX10b, then a negative external transition will setthe corresponding request flag. When T2I or T4Iare programmed to X11b, both a positive and anegative transition will set the request flag. In allthree cases, the contents of the core timer T3 willbe captured into the auxiliary timer registers T2 orT4 based on the transition at pins T2IN or T4IN.When the interrupt enable bits T2IE or T4IE areset, a PEC request or an interrupt request for vec-tor T2INT or T4INT will be generated.

Pin CAPIN differs slightly from the timer input pinsas it can be used as external interrupt input pinwithout affecting peripheral functions. When thecapture mode enable bit T5SC in register T5CONis cleared to ’0’, signal transitions on pin CAPINwill only set the interrupt request flag CRIR in reg-ister CRIC, and the capture function of registerCAPREL is not activated.

So register CAPREL can still be used as reloadregister for GPT2 timer T5, while pin CAPINserves as external interrupt input. Bit field CI inregister T5CON selects the effective transition ofthe external interrupt input signal. When CI is pro-grammed to 01b, a positive external transition willset the interrupt request flag. CI=10b selects anegative transition to set the interrupt request flag,and with CI=11b, both a positive and a negativetransition will set the request flag. When the inter-rupt enable bit CRIE is set, an interrupt request forvector CRINT or a PEC request will be generated.Note: The non-maskable interrupt input pin NMI and the

reset input RSTIN provide another possibility for theCPU to react on an external input signal. NMI andRSTIN are dedicated input pins, which cause hard-ware traps.

Pins to be used as External Interrupt Inputs

Port Pin Original Function Control Register

P3.7/T2IN Auxiliary timer T2 input pin T2CON

P3.5/T4IN Auxiliary timer T4 input pin T4CON

P3.2/CAPIN GPT2 capture input pin T5CON

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EXTERNAL INTERRUPTS (Cont’d)Fast External InterruptsThe input pins that may be used for external inter-rupts are sampled every 400 ns (@ 20 MHz CPUclock), ie. external events are scanned and detect-ed in timeframes of 400 ns. The ST10R163 pro-vides 8 interrupt inputs that are sampled every 50ns (@ 20 MHz CPU clock), so external events arecaptured faster than with standard interrupt inputs.

The pins of Port 2 (EX0IN-EX7IN on P2.8-P2.15)can individually be programmed to this fast inter-rupt mode, where also the trigger transition (rising,falling or both) can be selected. The External In-terrupt Control register EXICON controls this fea-ture for all 8 pins.

EXICON (F1C0h / E0h) ESFR Reset Value: 0000h

CCxIC (See Table) SFR Reset Value: --00h

Note: The fast external interrupt inputs are sampled every50 ns. The interrupt request arbitration andprocessing, however, is executed every 200 ns(both @ 20 MHz CPU clock).

Note: Please refer to the general interrupt control registerdescription for an explanation of the control fields.

5 4 3 2 1 011 10 9 8 7 615 14 13 12

rwrwrw

EXI2ES EXI0ESEXI1ES

rwrwrw

EXI7ES EXI5ESEXI6ES

rwrw

EXI3ESEXI4ES

5 4 3 2 1 011 10 9 8 7 615 14 13 12

rwrwrw

CCxIE GLVL

--- rw-

CCxIR

- - --

ILVL

Bit Function

EXIxES

External Interrupt x Edge Selection Field

(x=7...0)

0 0: Fast external interrupts disabled:

standard mode

0 1: Interrupt on positive edge (rising)

1 0: Interrupt on negative edge (falling)

1 1: Interrupt on any edge (rising or falling)

External Interrupt Control Registers

Register Address Reg. Space

CC8IC FF88h/C4h SFR

CC9IC FF8Ah/C5h SFR

CC10IC FF8Ch/C6h SFR

CC11IC FF8Eh/C7h SFR

CC12IC FF90h/C8h SFR

CC13IC FF92h/C9h SFR

CC14IC FF94h/CAh SFR

CC15IC FF96h/CBh SFR

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4.9 TRAP FUNCTIONS

Traps interrupt the current execution similar tostandard interrupts. However, trap functions offerthe possibility to bypass the interrupt system’s pri-oritization process in cases where immediate sys-tem reaction is required. Trap functions are notmaskable and always have priority over interruptrequests on any priority level.The ST10R163 provides two different kinds oftrapping mechanisms. Hardware traps are trig-gered by events that occur during program execu-tion (eg. illegal access or undefined opcode),soft-ware traps are initiated via an instruction withinthe current execution flow.Software TrapsThe TRAP instruction is used to cause a softwarecall to an interrupt service routine. The trapnumber that is specified in the operand field of thetrap instruction determines which vector locationin the address range from 00’0000h through00’01FCh will be branched to.Executing a TRAP instruction causes a similar ef-fect as if an interrupt at the same vector had oc-curred. PSW, CSP (in segmentation mode), andIP are pushed on the internal system stack and ajump is taken to the specified vector location.When segmentation is enabled and a trap is exe-cuted, the CSP for the trap service routine is set tocode segment 0. No Interrupt Request flags areaffected by the TRAP instruction. The interruptservice routine called by a TRAP instruction mustbe terminated with a RETI (return from interrupt)instruction to ensure correct operation.Note: The CPU level in register PSW is not modified by

the TRAP instruction, so the service routine is exe-cuted on the same priority level from which it was in-voked. Therefore, the service routine entered by theTRAP instruction can be interrupted by other trapsor higher priority interrupts, other than when trig-gered by a hardware trap.

Hardware TrapsHardware traps are issued by faults or specificsystem states that occur during runtime of a pro-

gram (not identified at assembly time). A hardwaretrap may also be triggered intentionally, eg. to em-ulate additional instructions by generating an Ille-gal Opcode trap. The ST10R163 distinguisheseight different hardware trap functions. When ahardware trap condition has been detected, theCPU branches to the trap vector location for therespective trap condition. Depending on the trapcondition, the instruction which caused the trap iseither completed or cancelled (ie. it has no effecton the system state) before the trap handling rou-tine is entered.

Hardware traps are non-maskable and alwayshave priority over every other CPU activity. If sev-eral hardware trap conditions are detected withinthe same instruction cycle, the highest priority trapis serviced (see table in section “Interrupt SystemStructure”).

PSW, CSP (in segmentation mode), and IP arepushed on the internal system stack and the CPUlevel in register PSW is set to the highest possiblepriority level (ie. level 15), disabling all interrupts.The CSP is set to code segment zero, if segmen-tation is enabled. A trap service routine must beterminated with the RETI instruction.

The eight hardware trap functions of theST10R163 are divided into two classes:

Class A traps are• external Non-Maskable Interrupt (NMI)• Stack Overflow• Stack Underflow trapThese traps share the same trap priority, but havean individual vector address.

Class B traps are• Undefined Opcode• Protection Fault• Illegal Word Operand Access• Illegal Instruction Access• Illegal External Bus Access TrapThese traps share the same trap priority, and thesame vector address.

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T TRAP FUNCTIONS (Cont’d)he bit-addressable Trap Flag Register (TFR) al-lows a trap service routine to identify the kind oftrap which caused the exception. Each trap func-

tion is indicated by a separate request flag. Whena hardware trap occurs, the corresponding re-quest flag in register TFR is set to ’1’.

TFR (FFACh / D6h) SFR Reset Value: 0000h

Note: The trap service routine must clear the respective trap flag, otherwise a new trap will be requested after exiting theservice routine. Setting a trap request flag by software causes the same effects as if it had been set by hardware.

Bit Function

ILLBUSIllegal External Bus Access Flag

An external access has been attempted with no external bus defined.

ILLINAIllegal Instruction Access Flag

A branch to an odd address has been attempted.

ILLOPAIllegal Word Operand Access Flag

A word operand access (read or write) to an odd address has been attempted.

PRTFLTProtection Fault Flag

A protected instruction with an illegal format has been detected.

UNDOPCUndefined Opcode Flag

The currently decoded instruction has no valid ST10R163 opcode.

STKUFStack Underflow Flag

The current stack pointer value exceeds the content of register STKUN.

STKOFStack Overflow Flag

The current stack pointer value falls below the content of register STKOV.

NMINon Maskable Interrupt Flag

A negative transition (falling edge) has been detected on pin NMI.

NMI

5 4 3 2 1 011 10 9 8 7 615 14 13 12

rw rw rw rwrw - - --rw ---

STKUF

ILLBUS

ILLINA

ILLOPA

PRTFLT

UNDOPC

STKOF - - - - - - --

-rwrw

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T TRAP FUNCTIONS (Cont’d)

The reset functions (hardware, software, watch-dog) may be regarded as a type of trap. Resetfunctions have the highest system priority (trappriority III).

Class A traps have the second highest priority(trap priority II), on the 3rd rank are class B traps,so a class A trap can interrupt a class B trap. Ifmore than one class A trap occur at a time, theyare prioritized internally, with the NMI trap on thehighest and the stack underflow trap on the lowestpriority.

All class B traps have the same trap priority (trappriority I). When several class B traps get active ata time, the corresponding flags in the TFR registerare set and the trap service routine is entered.Since all class B traps have the same vector, thepriority of service of simultaneously occurringclass B traps is determined by software in the trapservice routine.

A class A trap occurring during the execution of aclass B trap service routine will be serviced imme-diately. During the execution of a class A trapservice routine, however, any class B trap occur-ring will not be serviced until the class A trap serv-ice routine is exited with a RETI instruction. In thiscase, the occurrence of the class B trap conditionis stored in the TFR register, but the IP value ofthe instruction which caused this trap is lost.

In the case where e.g. an Undefined Opcode trap(class B) occurs simultaneously with an NMI trap(class A), both the NMI and the UNDOPC flag isset, the IP of the instruction with the undefined op-code is pushed onto the system stack, but the NMItrap is executed. After return from the NMI serviceroutine, the IP is popped from the stack and imme-diately pushed again because of the pending UN-DOPC trap.

External NMI Trap

Whenever a high to low transition on the dedicat-ed external NMI pin (Non-Maskable Interrupt) isdetected, the NMI flag in register TFR is set andthe CPU will enter the NMI trap routine. The IP val-ue pushed on the system stack is the address ofthe instruction following the one after which nor-mal processing was interrupted by the NMI trap.

Stack Overflow Trap

Whenever the stack pointer is decremented to avalue which is less than the value in the stack

overflow register STKOV, the STKOF flag in regis-ter TFR is set and the CPU will enter the stackoverflow trap routine. Which IP value will bepushed onto the system stack depends on whichoperation caused the decrement of the SP. Whenan implicit decrement of the SP is made through aPUSH or CALL instruction, or upon interrupt ortrap entry, the IP value pushed is the address ofthe following instruction. When the SP is decre-mented by a subtract instruction, the IP valuepushed represents the address of the instructionafter the instruction following the subtract instruc-tion.

For recovery from stack overflow it must be en-sured that there is enough excess space on thestack for saving the current system state (PSW,IP, in segmented mode also CSP) twice. Other-wise, a system reset should be generated.

Stack Underflow Trap

Whenever the stack pointer is incremented to avalue which is greater than the value in the stackunderflow register STKUN, the STKUF flag is setin register TFR and the CPU will enter the stackunderflow trap routine. Again, which IP value willbe pushed onto the system stack depends onwhich operation caused the increment of the SP.When an implicit increment of the SP is madethrough a POP or return instruction, the IP valuepushed is the address of the following instruction.When the SP is incremented by an add instruc-tion, the pushed IP value represents the addressof the instruction after the instruction following theadd instruction.

Undefined Opcode Trap

When the instruction currently decoded by theCPU does not contain a valid ST10R163 opcode,the UNDOPC flag is set in register TFR and theCPU enters the undefined opcode trap routine.The IP value pushed onto the system stack is theaddress of the instruction that caused the trap.

This can be used to emulate unimplemented in-structions. The trap service routine can examinethe faulting instruction to decode operands for un-implemented opcodes based on the stacked IP. Inorder to resume processing, the stacked IP valuemust be incremented by the size of the undefinedinstruction, which is determined by the user, be-fore a RETI instruction is executed.

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T TRAP FUNCTIONS (Cont’d)Protection Fault TrapWhenever one of the special protected instruc-tions is executed where the opcode of that instruc-tion is not repeated twice in the second word of theinstruction and the byte following the opcode is notthe complement of the opcode, the PRTFLT flag inregister TFR is set and the CPU enters the protec-tion fault trap routine. The protected instructionsinclude DISWDT, EINIT, IDLE, PWRDN, SRST,and SRVWDT. The IP value pushed onto the sys-tem stack for the protection fault trap is the ad-dress of the instruction that caused the trap.Illegal Word Operand Access TrapWhenever a word operand read or write access isattempted to an odd byte address, the ILLOPAflag in register TFR is set and the CPU enters theillegal word operand access trap routine. The IPvalue pushed onto the system stack is the addressof the instruction following the one which causedthe trap.

Illegal Instruction Access Trap

Whenever a branch is made to an odd byte ad-dress, the ILLINA flag in register TFR is set andthe CPU enters the illegal instruction access traproutine. The IP value pushed onto the systemstack is the illegal odd target address of thebranch instruction.

Illegal External Bus Access Trap

Whenever the CPU requests an external instruc-tion fetch, data read or data write, and no externalbus configuration has been specified, the ILLBUSflag in register TFR is set and the CPU enters theillegal bus access trap routine. The IP valuepushed onto the system stack is the address ofthe instruction following the one which caused thetrap. However the ST10R165 being a romless mi-crocontroller, an external bus must be defined andsuch a trap should never occur.

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ST10R163User Manual

5 - PARALLEL PORTS

In order to accept or generate single external con-trol signals or parallel data, the ST10R163 pro-vides up to 77 parallel IO lines organized into sev-en 8-bit IO ports (PORT0 made of P0H and P0L,PORT1 made of P1H and P1L, Port 2, Port 6), one15-bit IO port (Port 3), one 8-bit IO port (Port 4)and one 6-bit input port (Port 5).

These port lines may be used for general purposeInput/Output controlled via software or may beused implicitly by ST10R163’s integrated periph-erals or the External Bus Controller.

Using part as General Purpose I/O lines.

All port lines are bit addressable, and all input/out-put lines are individually (bit-wise) programmableas inputs or outputs via direction registers (exceptPort 5). The IO ports are true bidirectional portswhich are switched to high impedance state whenconfigured as inputs. The output drivers of threeIO ports (2, 3, 6) can be configured (pin by pin) for

push/pull operation or open-drain operation viacontrol registers. The logic level of a pin is clockedinto the input latch once per state time, regardlesswhether the port is configured for input or output.

A write operation to a port pin configured as an in-put causes the value to be written into the port out-put latch, while a read operation returns thelatched state of the pin itself. A read-modify-writeoperation reads the value of the pin, modifies it,and writes it back to the output latch.

Writing to a pin configured as an output(DPx.y=‘1’) causes the output latch and the pin tohave the written value, since the output buffer isenabled. Reading this pin returns the value of theoutput latch. A read-modify-write operation readsthe value of the output latch, modifies it, and writesit back to the output latch, thus also modifying thelevel at the pin.

Figure 2-1. SFRs and Pins associated with the Parallel Ports

Note: E: ESFR located in the ESFR space

ODP2 EDP2

P5

P2

Data Input / OutputRegisters

Direction ControlRegisters

Open Drain ControlRegisters

P6 DP6 ODP6 E

P0L

P0H

DP0L E

DP0H E

P4

P1L

P1H

P3 DP3

DP4

DP1H E

DP1L E

ODP3 E

77

2/28

5 - PARALLEL PORTS (ST10R163)

In the ST10R163 certain ports provide Open DrainControl, which allows to switch the output driver ofa port pin from a push/pull configuration to anopen drain configuration. In push/pull mode a portoutput driver has an upper and a lower transistor,thus it can actively drive the line either to a high ora low level. In open drain mode the upper transis-tor is always switched off, and the output drivercan only actively drive the line to a low level. Whenwriting a ‘1’ to the port latch, the lower transistor isswitched off and the output enters a high-imped-ance state. The high level must then be providedby an external pullup device. With this feature, it ispossible to connect several port pins together to aWired-AND configuration, saving external gluelogic and/or additional software overhead for ena-bling/disabling output signals.This feature is implemented for ports P2, P3 andP6 (see respective sections), and is controlledthrough the respective Open Drain Control Regis-ters ODPx. These registers allow the individualbit-wise selection of the open drain mode for eachport line. If the respective control bit ODPx.y is ‘0’(default after reset), the output driver is in the

push/pull mode. If ODPx.y is ‘1’, the open drainconfiguration is selected. Note that all ODPx reg-isters are located in the ESFR space.

Each port line has one programmable alternate in-put or output function associated with it.

Each port line has one programmable alternate in-put or output function associated with it.

PORT0 and PORT1 may be used as the addressand data lines when accessing external memory.

Port 4 outputs the additional segment address bitsA23/19/17...A16 in systems where more than 64KBytes of memory are to be accessed directly.

Port 6 provides the optional chip select outputsand the bus arbitration lines.

Port 2 is used for fast external interrupt inputs.

Port 3 includes alternate input/output functions oftimers, serial interface, the optional bus controlsignal BHE and the system clock output (CLK-OUT).

Port 5 is used for timer control signals.

Figure 2-2. Output Drivers in Push/Pull Mode and in Open Drain Mode

78

3/28


Alternate Input or Output function of PortIf an alternate output function of a pin is to beused, the direction of this pin must be pro-grammed for output (DPx.y=‘1’), except for somesignals that are used directly after reset and areconfigured automatically. Otherwise the pin re-mains in the high-impedance state and is not af-fected by the alternate output function. The re-spective port latch should hold a ‘1’, because itsoutput is ANDed with the alternate output data.If an alternate input function of a pin is used, thedirection of the pin must be programmed for input(DPx.y=‘0’) if an external device is driving the pin.The input direction is the default after reset. If noexternal device is connected to the pin, however,one can also set the direction for this pin to output.In this case, the pin reflects the state of the portoutput latch. Thus, the alternate input functionreads the value stored in the port output latch.This can be used for testing purposes to allow asoftware trigger of an alternate input function bywriting to the port output latch.On most of the port lines, the user software is re-sponsible for setting the proper direction when us-ing an alternate input or output function of a pin.This is done by setting or clearing the directioncontrol bit DPx.y of the pin before enabling the al-ternate function. There are port lines, however,where the direction of the port line is switched au-tomatically. For instance, in the multiplexed exter-nal bus modes of PORT0, the direction must beswitched several times for an instruction fetch inorder to output the addresses and to input the da-ta. Obviously, this cannot be done through instruc-tions. In these cases, the direction of the port lineis switched automatically by hardware if the alter-nate function of such a pin is enabled.To determine the appropriate level of the port out-

put latches check how the alternate data output iscombined with the respective port latch output.There is one basic structure for all port lines withonly an alternate input function. Port lines withonly an alternate output function, however, havedifferent structures due to the way the direction ofthe pin is switched and depending on whether thepin is accessible by the user software or not in thealternate function mode.All port lines that are not used for these alternatefunctions may be used as general purpose IOlines. When using port pins for general purposeoutput, the initial output value should be written tothe port latch prior to enabling the output drivers,in order to avoid undesired transitions on the out-put pins. This applies to single pins as well as topin groups (see examples below).SINGLE_BIT: BSET P4.7; Initial output level is “high”

BSET DP4.7; Switch on the output driver

BIT_GROUP: BFLDH P4, #24h, #24h; Initial output level is “high”

BFLDH DP4, #24h, #24h; Switch on the output drivers

Note : When using several BSET pairs to controlmore pins of one port, these pairs must be sepa-rated by instructions, which do not reference therespective port (see “Particular Pipeline Effects” inchapter “The Central Processing Unit”).Each of these ports and the alternate input andoutput functions are described in detail in the fol-lowing subsections.

79

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5.1 PORT 0

The two 8-bit ports P0H and P0L represent thehigher and lower part of PORT0, respectively.Both halves of PORT0 can be written (eg. via aPEC transfer) without affecting the other half.

If this port is used for general purpose IO, the di-rection of each line can be configured via the cor-responding direction registers DP0H and DP0L.

P0L (FF00h / 80h) SFR Reset Value: - - 00h

P0h (FF02h / 81h) SFR Reset Value: - - 00h

DP0L (F100h / 80h) ESFR Reset Value: - - 00h

DP0h (F102h / 81h) ESFR Reset Value: - - 00h

Bit Function

P0X.y Port data register P0H or P0L bit y

Bit Function

DP0X.y Port direction register DP0H or DP0L bit y

DP0X.y = 0: Port line P0X.y is an input (high-impedance)

DP0X.y = 1: Port line P0X.y is an output

5 4 3 2 1 011 10 9 8 7 615 14 13 12

rw rw rw rw rw rw- - - - rw rw- - - -

P0L.0P0L.1P0L.2P0L.3P0L.4P0L.5P0L.6P0L.7

5 4 3 2 1 011 10 9 8 7 615 14 13 12


P0H.0P0H.1P0H.2P0H.3P0H.4P0H.5P0H.6P0H.7

5 4 3 2 1 011 10 9 8 7 615 14 13 12


DP0L.7

DP0L.6

DP0L.5

DP0L.4

DP0L.3

DP0L.2

DP0L.1

DP0L.0

5 4 3 2 1 011 10 9 8 7 615 14 13 12


DP0H.7

DP0H.6

DP0H.5

DP0H.4

DP0H.3

DP0H.2

DP0H.1

DP0H.0

80

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PORT 0 (Cont’d)

5.1.1 Alternate Functions of PORT0

When an external bus is enabled, PORT0 is usedas data bus or address/data bus.Note that an external 8-bit demultiplexed bus onlyuses P0L, while P0H is free for IO (provided thatno other bus mode is enabled).

PORT0 is also used to select the system startupconfiguration. During reset, PORT0 is configuredto input, and each line is held high through an in-ternal pullup device. Each line can then be individ-ually pulled to a low level (see DC-level specifica-tions in the respective Data Sheets) through anexternal pulldown device. A default configurationis selected when the respective PORT0 lines areat a high level. Through pulling individual lines to alow level, this default can be changed according tothe needs of the applications.The internal pullup devices are designed such thatan external pulldown resistors (see Data Sheetspecification) can be used to apply a correct lowlevel. These external pulldown resistors can re-main connected to the PORT0 pins also duringnormal operation, however, care has to be takensuch that they do not disturb the normal function ofPORT0 (this might be the case, for example, if the

external resistor is too strong).With the end of reset, the selected bus configura-tion will be written to the BUSCON0 register. Theconfiguration of the high byte of PORT0, will becopied into the special register RP0H. This read-only register holds the selection for the number ofchip selects and segment addresses. Softwarecan read this register in order to react according tothe selected configuration, if required.When the reset is terminated, the internal pullupdevices are switched off, and PORT0 will beswitched to the appropriate operating mode.

During external accesses in multiplexed busmodes PORT0 first outputs the 16-bit intra-seg-ment address as an alternate output function.PORT0 is then switched to high-impedance inputmode to read the incoming instruction or data. In8-bit data bus mode, two memory cycles are re-quired for word accesses, the first for the low byteand the second for the high byte of the word. Dur-ing write cycles PORT0 outputs the data byte orword after outputting the address.During external accesses in demultiplexed busmodes PORT0 reads the incoming instruction ordata word or outputs the data byte or word.

Figure 2-3. PORT0 IO and Alternate Functions

P0H.7P0H.6P0H.5P0H.4P0H.3P0H.2P0H.1P0H.0P0L.7P0L.6P0L.5P0L.4P0L.3P0L.2P0L.1P0L.0

PORT0 D7D6D5D4D3D2D1D0

P0H

P0L

D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0

AD15AD14AD13AD12AD11AD10AD9AD8AD7AD6AD5AD4AD3AD2AD1AD0

AD15AD14AD13AD12AD11AD10AD9AD8AD7AD6AD5AD4AD3AD2AD1AD0

Alternate Function a) b) c) d)

General PurposeInput/Output

8-bitDemux Bus

16-bitDemux Bus

8-bitMUX Bus

16-bitMUX Bus

81

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PORT 0 (Cont’d)When an external bus mode is enabled, the direc-tion of the port pin and the loading of data into theport output latch are controlled by the bus control-ler hardware. The input of the port output latch isdisconnected from the internal bus and isswitched to the line labeled “Alternate Data Out-put” via a multiplexer. The alternate data can bethe 16-bit intrasegment address or the 8/16-bitdata information. The incoming data on PORT0 isread on the line “Alternate Data Input”. While an

external bus mode is enabled, the user softwareshould not write to the port output latch, otherwiseunpredictable results may occur. When the exter-nal bus modes are disabled, the contents of the di-rection register last written by the user becomesactive.

The figure below shows the structure of a PORT0pin.

Figure 2-4. Block Diagram of a PORT0 Pin

y = 7...0

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5.2 PORT 1

The two 8-bit ports P1H and P1L represent thehigher and lower part of PORT1, respectively.Both halves of PORT1 can be written (eg. via aPEC transfer) without affecting the other half.

If this port is used for general purpose IO, the di-rection of each line can be configured via the cor-responding direction registers DP1H and DP1L.

P1L (FF04h / 82h) SFR Reset Value: - - 00h

P1h (FF06h / 83h) SFR Reset Value: - - 00h

DP1L (F104h / 82h) ESFR Reset Value: - - 00h

DP1H (F106h / 83h) ESFR Reset Value: - - 00h

Bit Function

P1X.y Port data register P1H or P1L bit y

Bit Function

DP1X.y Port direction register DP1H or DP1L bit y

DP1X.y = 0: Port line P1X.y is an input (high-impedance)

DP1X.y = 1: Port line P1X.y is an output

5 4 3 2 1 011 10 9 8 7 615 14 13 12


P1L.0P1L.1P1L.2P1L.3P1L.4P1L.5P1L.6P1L.7

5 4 3 2 1 011 10 9 8 7 615 14 13 12


P1H.0P1H.1P1H.2P1H.3P1H.4P1H.5P1H.6P1H.7

5 4 3 2 1 011 10 9 8 7 615 14 13 12


DP1L.7

DP1L.6

DP1L.5

DP1L.4

DP1L.3

DP1L.2

DP1L.1

DP1L.0

5 4 3 2 1 011 10 9 8 7 615 14 13 12


DP1H.7

DP1H.6

DP1H.5

DP1H.4

DP1H.3

DP1H.2

DP1H.1

DP1H.0

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PORT 1 (Cont’d)5.2.1 Alternate Functions of PORT1

When a demultiplexed external bus is enabled,PORT1 is used as address bus.Note that demultiplexed bus modes use PORT1as a 16-bit port. Otherwise all 16 port lines can beused for general purpose IO.

During external accesses in demultiplexed busmodes PORT1 outputs the 16-bit intra-segmentaddress as an alternate output function.

During external accesses in multiplexed busmodes, when no BUSCON register selects a de-multiplexed bus mode, PORT1 is not used and isavailable for general purpose IO.

When an external bus mode is enabled, the direc-tion of the port pin and the loading of data into theport output latch are controlled by the bus control-ler hardware. The input of the port output latch isdisconnected from the internal bus and isswitched to the line labeled “Alternate Data Out-put” via a multiplexer. The alternate data is the 16-bit intrasegment address. While an external busmode is enabled, the user software should notwrite to the port output latch, otherwise unpredict-able results may occur. When the external busmodes are disabled, the contents of the directionregister last written by the user becomes active.

Figure 2-5. PORT1 IO and Alternate Functions

P1H.7P1H.6P1H.5P1H.4P1H.3P1H.2P1H.1P1H.0P1L.7P1L.6P1L.5P1L.4P1L.3P1L.2P1L.1P1L.0

PORT1

P1H

P1L

A15A14A13A12A11A10A9A8A7A6A5A4A3A2A1A0

Alternate Function a)

General PurposeInput /Output

8/16-bitDemux Bus

84

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PORT 1 (Cont’d)The figure below shows the structure of a PORT1 pin.

Figure 2-6. Block Diagram of a PORT1 Pin

y = 7...0

85

10/28


5.3 PORT 2

In the ST10R163 Port 2 is an 8-bit port. If Port 2 isused for general purpose IO, the direction of eachline can be configured via the corresponding di-rection register DP2. Each port line can be

switched into push/pull or open drain mode via theopen drain control register ODP2.5.3.1 Alternate Functions of Port 2All Port 2 lines (P2.15...P2.8) can serve as FastExternal Interrupt inputs (EX7IN...EX0IN).

P2 (FFC0h / E0h) SFR Reset Value: 00 - -h

DP2 (FFC2h / E1h) SFR Reset Value: 00 - -h

ODP2 (F1C2h / E1h) ESFR Reset Value: 00 - -h

Bit Function

P2.y Port data register P2 bit y

Bit Function

DP2.y Port direction register DP2 bit y

DP2.y = 0: Port line P2.y is an input (high-impedance)

DP2.y = 1: Port line P2.y is an output

5 4 3 2 1 011 10 9 8 7 615 14 13 12

- - - - - -rw rw rw rw - -rw rw rw rw

P2.8P2.9P2.10P2.11P2.12P2.13P2.14P2.15

5 4 3 2 1 011 10 9 8 7 615 14 13 12


DP2.15

DP2.14

DP2.13

DP2.12

DP2.11

DP2.10

DP2.9

DP2.8

Bit Function

ODP2.y Port 2 Open Drain control register bit y

ODP2.y = 0: Port line P2.y output driver in push/pull mode

ODP2.y = 1: Port line P2.y output driver in open drain mode

5 4 3 2 1 011 10 9 8 7 615 14 13 12


ODP2.15

ODP2.14

ODP2.13

ODP2.12

ODP2.11

ODP2.10

ODP2.9

ODP2.8

86

11/28


PORT 2 (Cont’d)The table below summarizes the alternate functions of Port 2.

Figure 2-7. Port 2 IO and Alternate Functions

Port 2 Pin Alternate Function

P2.8

P2.9

P2.10

P2.11

P2.12

P2.13

P2.14

P2.15

EX0IN Fast External Interrupt 0 Input








P2.15P2.14P2.13P2.12P2.11P2.10P2.9P2.8--------

Port 2

EX7INEX6INEX5INEX4INEX3INEX2INEX1INEX0IN--------


General PurposeInput/Ou tput

Fast ExternalInterrupt Input

87

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PORT 2 (Cont’d)The pins of Port 2 combine internal bus data and alternate data output before the port latch input.

Figure 2-8. Block Diagram of a Port 2 Pin

y = 15...8

88

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5.4 PORT 3

If this 15-bit port is used for general purpose IO,the direction of each line can be configured via thecorresponding direction register DP3. Most portlines can be switched into push/pull or open drainmode via the open drain control register ODP3

(pins P3.15, P3.14 and P3.12 do not support opendrain mode!).

Due to pin limitations register bit P3.14 is not con-nected to an output pin.

P3 (FFC4h / E2h) SFR Reset Value: 0000h

Note: Register bit P3.14 is not connected to an IO pin.

DP3 (FFC6h / E3h) SFR Reset Value: 0000h

ODP3 (F1C6h / E3h) ESFR Reset Value: 0000h

Bit Function


Bit Function




Bit Function




5 4 3 2 1 011 10 9 8 7 615 14 13 12

rw rw rw rw rw rwrw rw rw rw rw rwrw - rw rw

P3.0P3.1P3.2P3.3P3.4P3.5P3.6P3.7P3.8P3.9P3.10P3.11P3.12P3.13-P3.15

- - -

5 4 3 2 1 011 10 9 8 7 615 14 13 12

rw rw rw rw rw rwrw rw rw rw rw rwrw - rw rw

DP3.13

DP3.11

DP3.10

DP3.9

DP3.8

DP3.7

DP3.6

DP3.5

DP3.4

DP3.3

DP3.2

DP3.1

DP3.0-

DP3.12

DP3.15

- - -

5 4 3 2 1 011 10 9 8 7 615 14 13 12

rw rw rw rw rw rwrw rw rw rw rw rw- - rw -

ODP3.13

ODP3.11

ODP3.10

ODP3.9

ODP3.8

ODP3.7

ODP3.6

ODP3.5

ODP3.4

ODP3.3

ODP3.2

ODP3.1

ODP3.0- - -

89

14/28


PORT3 (Cont’d)5.4.1 Alternate Functions of Port 3The pins of Port 3 serve for various functionswhich include external timer control lines, the two

serial interfaces and the control lines BHE andCLKOUT.The table below summarizes the alternate func-tions of Port 3.



P3.0

P3.1

P3.2

P3.3

P3.4

P3.5

P3.6

P3.7

P3.8

P3.9

P3.10

P3.11

P3.12

P3.13

P3.14

P3.15

-

T6OUT Timer 6 Toggle Output

CAPIN GPT2 Capture Input

T3OUT Timer 3 Toggle Output

T3EUD Timer 3 External Up/Down Control Input

T4IN Timer 4 Count Input



MRST SSC Master Receive / Slave Transmit

MTSR SSC Master Transmit / Slave Receive

TxD0 ASC0 Transmit Data Output

RxD0 ASC0 Receive Data Input

BHE/WRH Byte High Enable / Write High Output

SCLK SSC Shift Clock Input/Output

--- No pin assigned!

CLKOUT System Clock Output

P3.15

P3.13P3.12P3.11P3.10P3.9P3.8P3.7P3.6P3.5P3.4P3.3P3.2P3.1P3.0

Port 3

No PinCLKOUT

SCLKBHERxD0TxD0MTSRMRSTT2INT3INT4INT3EUDT3OUTCAPINT6OUT

WRH

Alternate Function a) b)


90

15/28


PORT3 (Cont’d)The port structure of the Port 3 pins depends ontheir alternate function (see figures below).

When the on-chip peripheral associated with aPort 3 pin is configured to use the alternate inputfunction, it reads the input latch, which representsthe state of the pin, via the line labeled “AlternateData Input”. Port 3 pins with alternate input func-tions are:T2IN, T3IN, T4IN, T3EUD and CAPIN.

When the on-chip peripheral associated with aPort 3 pin is configured to use the alternate outputfunction, its “Alternate Data Output” line is ANDedwith the port output latch line. When using thesealternate functions, the user must set the directionof the port line to output (DP3.y=1) and must setthe port output latch (P3.y=1). Otherwise the pin isin its high-impedance state (when configured asinput) or the pin is stuck at ’0’ (when the port out-

put latch is cleared). When the alternate outputfunctions are not used, the “Alternate Data Out-put” line is in its inactive state, which is a high level(’1’). Port 3 pins with alternate output functionsare:T6OUT, T3OUT, TxD0 and CLKOUT.

When the on-chip peripheral associated with aPort 3 pin is configured to use both the alternateinput and output function, the descriptions aboveapply to the respective current operating mode.The direction must be set accordingly. Port 3 pinswith alternate input/output functions are:MTSR, MRST, RxD0 and SCLK.

Note: Enabling the CLKOUT function automatical-ly enables the P3.15 output driver. Settingbit DP3.15=’1’ is not required.

91

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PORT3 (Cont’d)

Figure 2-10. Block Diagram of a Port 3 Pin with Alternate Input or Alternate Output Function

y = 13, 11...0

92

17/28


PORT3 (Cont’d)Pin P3.12 (BHE/WRH) is one more pin with an al-ternate output function. However, its structure isslightly different (see figure below), because afterreset the BHE or WRH function must be used de-pending on the system startup configuration. Inthese cases there is no possibility to program any

port latches before. Thus the appropriate alternatefunction is selected automatically. IfBHE/WRH isnot used in the system, this pin can be used forgeneral purpose IO by disabling the alternatefunction (BYTDIS = ‘1’ / WRCFG=’0’).

Figure 2-11. Block Diagram of Pins P3.15 (CLKOUT) and P3.12 ( BHE/WRH)

x = 15, 12

93

18/28


5.1 PORT 4

In the ST10R163, the Port 4 is an 8-bit port. If theSSP is disabled (bit SSPEN cleared in SYSCONregister), Port 4 is used for general purpose IO(the direction of each line can be configured viathe corresponding direction register DP4).If the SSP is enabled (bit SSPEN set), the 4 upper

pins are used for the Synchronous Serial Port(SSP) dedicated IO. The bits in the Port 4 DataRegister (P4) and the Port 4 Direction ControlRegister (DP4) that correspond to the pinsSSPCLK, SSPDATA, SSPDEN0 and SSPDEN1are no influence on these pins.

P4 (FFC8h / E4h) SFR Reset Value: - - 00h

DP4 (FFCAh / E5h) SFR Reset Value: - - 00h

Bit Function


Bit Function

DP4.y

Port direction register DP4 bit y



5 4 3 2 1 011 10 9 8 7 615 14 13 12


P4.0P4.1P4.2P4.3P4.4P4.5P4.6P4.7

5 4 3 2 1 011 10 9 8 7 615 14 13 12


DP4.0DP4.1DP4.2DP4.3DP4.4DP4.5DP4.6DP4.7

94

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PORT4 (Cont’d)

5.1.1 Alternate Functions of Port 4

During external bus cycles that use segmentation(ie. an address space above 64 KByte) a numberof Port 4 pins may output the segment addresslines. The number of pins that is used for segmentaddress output determines the external addressspace which is directly accessible. The other pinsof Port 4 (if any) may be used for general purposeIO. If segment address lines are selected, the al-ternate function of Port 4 may be necessary to ac-cess eg. external memory directly after reset. For

this reason Port 4 will be switched to its alternatefunction automatically.The number of segment address lines is selectedvia PORT0 during reset. The selected value canbe read from bitfield SALSEL in register RP0H(read only) eg. in order to check the configurationduring run time.The table below summarizes the alternate func-tions of Port 4 depending on the number of select-ed segment address lines (coded via bitfield SAL-SEL) and on the state of SSPEN control bit..

Figure 2-12. Port 4 I/O and Alternate Functions

Port 4 PinStd. Function

SALSEL=01 64 KB

Altern. Function

SALSEL=11 256KB

Altern. Function

SALSEL=00 1 MB

Altern. Function

SALSEL=10 16 MB

P4.0

P4.1

P4.2

P4.3

P4.4

P4.5

P4.6

P4.7

Gen. purpose IO

Gen. purpose IO

Gen. purpose IO

Gen. purpose IO

Gen. IO / SSPCE1

Gen. IO / SSPCE0

Gen. IO / SSPDAT

Gen. IO / SSPCLK

Seg. Address A16

Seg. Address A17

Gen. purpose IO

Gen. purpose IO

Gen. IO / SSPCE1

Gen. IO / SSPCE0

Gen. IO / SSPDAT

Gen. IO / SSPCLK

Seg. Address A16

Seg. Address A17

Seg. Address A18

Seg. Address A19

Gen. IO / SSPCE1

Gen. IO / SSPCE0

Gen. IO / SSPDAT

Gen. IO / SSPCLK

Seg. Address A16

Seg. Address A17

Seg. Address A18

Seg. Address A19

Seg. Address A20

Seg. Address A21

Seg. Address A22

Seg. Address A23

--------P4.7P4.6P4.5P4.4P4.3P4.2P4.1P4.0

Port 4

--------A23A22A21A20A19A18A17A16

General Purpose I/O Alternate Function

--------SSPCLKSSPDATSSPCE0SSPCE1

Port 4

Dedicated Function

95

20/28


PORT4 (Cont’d)

Figure 2-13. Block Diagram of Port 4 Pin P4.0 to P4.3

Figure 2-14. Block Diagram of Port 4 Pins SSPCE1/ A20, SSPCE0 / A21, SSPCLK / A2

VR02075B

OutputBuffer

MUX1

0

AlternateData

Output

LatchPort Output

0

1MUX

Write P4.y

Read P4.y

EnableFunctionAlternate

0

1MUX

Read DP4.y

Write DP4.y

Direction

’1’

InputLatch

Clock

Latch

suB

lanretnI

P4.y

y = 3...0

VR02075C

OutputBuffer

MUX1

0

AlternateData

Output

LatchPort Output

0

1MUX

Write P4.y

Read P4.y


0

1MUX

Read DP4.y

Write DP4.y

Direction

’1’

InputLatch

Clock

Latch

suB

lanretnI

P4.y

y = 4, 5, 7

SignalControl

SSP

0

1MUX

SignalSSP

SSPEnabled

96

21/28


PORT4 (Cont’d)

Figure 2-15. Block Diagram of Port 4 Pin SSPDAT/ A22

VR02075D

OutputBufferLatch

Port Output

0

1MUX

Write P4.y

Read P4.y


0

1MUX

Read DP4.y

Write DP4.y

Direction

’1’

InputLatch

Clock

Latch

suB

lanretnI

P4.6

SignalControl

SSP

DataOutput

SSP

SSPData In

MUX1

0

AlternateData

Output

0

1MUX

SSPEnabled

97

22/28


5.5 PORT 5

This 6-bit input port can only read data. There isno output latch and no direction register. Data writ-

ten to P5 will be lost.

P5 (FFA2h / D1h) SFR Reset Value: XX - -h

5.5.1 Alternate Functions of Port 5Each line of Port 5 serves as external timer controlline for GPT1 and GPT2.

The table below summarizes the alternate func-tions of Port 5.


Bit Function

P5.y Port data register P5 bit y (Read only)

5 4 3 2 1 011 10 9 8 7 615 14 13 12

- - - - - -r r - - - -r r r r

P5.11P5.12P5.13P5.14P5.15 P5.10


P5.10

P5.11

P5.12

P5.13

P5.14

P5.15

T6EUD Timer 6 external Up/Down Control Input






P5.15P5.14P5.13P5.12P5.11P5.10----------

Port 5

T2EUDT4EUDT5INT6INT5EUDT6EUD----------


General PurposeInput

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PORT 5 (Cont’d)Port 5 pins have a special port structure (see figure below), because it is an input only port.

Figure 2-17. Block Diagram of a Port 5 Pin

y = 15...10

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5.6 PORT 6

If this 8-bit port is used for general purpose IO, thedirection of each line can be configured via thecorresponding direction register DP6. Each port

line can be switched into push/pull or open drainmode via the open drain control register ODP6.

P6 (FFCCh / E6h) SFR Reset Value: - - 00h

DP6 (FFCEh / E7h) SFR Reset Value: - - 00h

ODP6 (F1CEh / E7h) ESFR Reset Value: - - 00h

Bit Function


Bit Function




5 4 3 2 1 011 10 9 8 7 615 14 13 12


P6.0P6.1P6.2P6.3P6.4P6.5P6.6P6.7

5 4 3 2 1 011 10 9 8 7 615 14 13 12


DP6.0DP6.1DP6.2DP6.3DP6.4DP6.5DP6.6DP6.7

Bit Function




5 4 3 2 1 011 10 9 8 7 615 14 13 12


ODP6.7

ODP6.6

ODP6.5

ODP6.4

ODP6.3

ODP6.2

ODP6.1

ODP6.0

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PORT 6 (Cont’d)5.6.1 Alternate Functions of Port 6A programmable number of chip select signals(CS4...CS0) derived from the bus control registers(BUSCON4...BUSCON0) can be output on 5 pinsof Port 6. The other 3 pins may be used for bus ar-bitration to accomodate additional masters in aST10R163 system.The number of chip select signals is selected viaPORT0 during reset. The selected value can be

read from bitfield CSSEL in register RP0H (readonly) eg. in order to check the configuration duringrun time.

The table below summarizes the alternate func-tions of Port 6 depending on the number of select-ed chip select lines (coded via bitfield CSSEL)

.


Port 6 Pin Altern. Function

CSSEL = 10

Altern. Function

CSSEL = 01

Altern. Function

CSSEL = 00

Altern. Function

CSSEL = 11

P6.0

P6.1

P6.2

P6.3

P6.4

Gen. purpose IO

Gen. purpose IO

Gen. purpose IO

Gen. purpose IO

Gen. purpose IO

Chip select CS0

Chip select CS1

Gen. purpose IO

Gen. purpose IO

Gen. purpose IO

Chip select CS0

Chip select CS1

Chip select CS2

Gen. purpose IO

Gen. purpose IO

Chip select CS0

Chip select CS1

Chip select CS2

Chip select CS3

Chip select CS4

P6.5

P6.6

P6.7

HOLDExternal hold request input

HLDAHold acknowledge output

BREQBus request output

--------P6.7P6.6P6.5P6.4P6.3P6.2P6.1P6.0

Port 6

--------BREQHLDAHOLDCS4CS3CS2CS1CS0



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PORT 6 (Cont’d)

The chip select lines of Port 6 additionally have aninternal weak pullup device. This device isswitched on under the following conditions:•always during reset•if the Port 6 line is used as a chip select output,and the ST10R163 is in Hold mode(invoked through HOLD), and the respective pindriver is in push/pull mode (ODP6.x = ‘0’).This feature is implemented to drive the chip se-lect lines high during reset in order to avoid multi-ple chip selection, and to allow another master toaccess the external memory via the same chip se-lect lines (Wired-AND), while the ST10R163 is inHold mode.With ODP6.x = ‘1’ (open drain output selected),the internal pullup device will not be active during

Hold mode; external pullup devices must be usedin this case.When entering Hold mode theCS lines are active-ly driven high for one clock phase, then the outputlevel is controlled by the pullup devices (if activat-ed).

After reset theCS function must be used, if select-ed so. In this case there is no possibility to pro-gram any port latches before. Thus the alternatefunction (CS) is selected automatically in thiscase.

Note: The open drain output option can only beselected via software earliest during the ini-tialization routine; at least signalCS0 will bein push/pull output driver mode directly afterreset.

Figure 2-19. Block Diagram of Port 6 Pins with an alternate output function

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PORT 6 (Cont’d)The bus arbitration signals HOLD, HLDA andBREQ are selected with bit HLDEN in registerPSW. When the bus arbitration signals are ena-bled via HLDEN, also these pins are switched au-tomatically to the appropriate direction. Note that

the pin drivers for HLDA and BREQ are automati-cally enabled, while the pin driver forHOLD is au-tomatically disabled.

Figure 2-20. Block Diagram of Pin P6.5 (HOLD)

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Notes:

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ST10R163User Manual

6 - DEDICATED PINS

Most of the input/output or control signals of thefunctional the ST10R163 are realized as alternatefunctions of pins of the parallel ports. There is,however, a number of signals that use separatepins, including the oscillator, special control sig-nals and, of course, the power supply.The table below summarizes the 23 dedicatedpins of the ST10R163.

The Address Latch Enable signal ALE controlsexternal address latches that provide a stable ad-dress in multiplexed bus modes. ALE is activated /not activated ...The External Read Strobe RD controls the out-put drivers of external memory or peripheralswhen the ST10R163 reads data from these exter-nal devices. During reset and during Hold modean internal pullup ensures an inactive (high) levelon the RD output.

The External Write StrobeWR/WRL controls thedata transfer from the ST10R163 to an externalmemory or peripheral device. This pin may eitherprovide an general WR signal activated for bothbyte and word write accesses, or specifically con-trol the low byte of an external 16-bit device (WRL)together with the signalWRH (alternate function ofP3.12/BHE). During reset and during Hold modean internal pullup ensures an inactive (high) levelon the WR/WRL output.The Ready Input READY receives a control sig-nal from an external memory or peripheral devicethat is used to terminate an external bus cycle,provided that this function is enabled for the cur-rent bus cycle. READY may be used as synchro-nous READY or may be evaluated asynchronous-ly.The External Access Enable Pin EA deter-mines, if the ST10R163 after reset starts fetchingcode from the internal ROM area (EA=’1’) or viathe external bus interface (EA=’0’).The Non-Maskable Interrupt Input NMI allows totrigger a high priority trap via an external signal(eg. a power-fail signal). It also serves to validatethe PWRDN instruction that switches theST10R163 into Power-Down mode.The Reset Input RSTIN allows to put theST10R163 into the well defined reset condition ei-ther at power-up or external events like a hard-ware failure or manual reset. The input voltagethreshold of the RSTIN pin is raised compared tothe standard pins in order to minimize the noisesensitivity of the reset input.

Pin(s) Function

ALE Address Latch Enable

RD External Read Strobe

WR/WRL External Write/Write Low Strobe

READY Ready Input

EA External Access Enable

NMI Non-Maskable Interrupt Input

RSTIN Reset Input

RSTOUT Reset Output

XTAL1, XTAL2 Oscillator Input/Output

VPPReserved for Flash ProgrammingVoltage

VCC, VSSDigital Power Supply and Ground(6 pins each)

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6 - DEDICATED PINS (ST10R163)

The Reset Output RSTOUT provides a specialreset signal for external circuitry.RSTOUT is acti-vated at the beginning of the reset sequence, trig-gered via RSTIN, a watchdog timer overflow or bythe SRST instruction. RSTOUT remains active(low) until the EINIT instruction is executed. Thisallows to initialize the controller before the exter-nal circuitry is activated.

The Oscillator Input XTAL1 and Output XTAL2connect the internal clock oscillator to the externalcrystal. An external clock signal may be fed to theinput XTAL1, leaving XTAL2 open.

The Flash Programming Voltage input VPPprovides the programming voltage that is requiredto erase and program the on-chip Flash memoryareas. On the ST10R163, the VPP pin is used toEnable/Disable the Oscillator Watchdog (See“System Clock Generation” section).The Power Supply pins VCC and VSS providethe power supply for the digital logic of theST10R163.Note : All VCC pins and all VSS pins must be con-nected to the power supply and ground, respec-tively.

Figure 3-21

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ST10R163User Manual

7 - EXTERNAL BUS INTERFACE

Although the ST10R163 provides a powerful set ofon-chip peripherals and on-chip RAM areas, theseinternal units only cover a small fraction of its ad-dress space of up to 16 MByte. The external businterface allows to access external peripheralsand additional volatile and non-volatile memory.The external bus interface provides a number ofconfigurations, so it can be taylored to fit perfectlyinto a given application system.Accesses to external memory or peripherals areexecuted by the integrated External Bus Control-ler (EBC). The function of the EBC is controlled viathe SYSCON register and the BUSCONx and AD-

DRSELx registers. The BUSCONx registers spec-ify the external bus cycles in terms of address(mux/demux), data (16-bit/8-bit), chip selects andlength (waitstates /READY control / ALE / RW de-lay). These parameters are used for accesseswithin a specific address area which is defined viathe corresponding register ADDRSELx.

The four pairs BUSCON1/ADDRSEL1...BUS-CON4/ADDRSEL4 allow to define four independ-ent “address windows”, while all external accessesoutside these windows are controlled via registerBUSCON0.

Figure 4-1. SFRs and Port Pins Associated with the External Bus Interface

BUSCON0

BUSCON1

BUSCON2

ADDRSEL4

P0L / P0H

P4

P6

ADDRSEL1

ODP6 E

P0L/P0H PORT0 Data RegistersP1L/P1H PORT1 Data RegistersDP3 Port 3 Direction Control RegisterP3 Port 3 Data RegisterP4 Port 4 Data RegisterODP6 Port 6 Open Drain Control RegisterDP6 Port 6 Direction Control RegisterP6 Port 6 Data Register

PORT0 EAPORT1 RSTINALE READYRDWR/WRLBHE/WRH

SYSCON

Control Registers

ADDRSELx Address Range Select Register 1...4BUSCONx Bus Mode Control Register 0...4SYSCON System Control RegisterRP0H Port P0H Reset Configuration Register

Ports & Direction ControlAlternate Functions

Address Registers Mode Registers Control Registers

BUSCON3

P1L / P1H

BUSCON4

ADDRSEL2

RP0H

DP6

DP3

P3 ADDRSEL3

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7 - EXTERNAL BUS INTERFACE (ST10R163)

7.1 SINGLE CHIP MODE

Single chip mode is entered, when pinEA is highduring reset. In this case register BUSCON0 iscleared (except bit ALECTL0 and bits BTYP0[1:0]= P0L.[7:6]), which also resets bit BUSACT0 ofBUSCON0 register, so no external bus is enabled.

In single chip mode the ST10R163 operates onlywith and out of internal resources. No external busis configured and no external peripherals and/ormemory can be accessed. Also no port lines areoccupied for the bus interface. The ST10R165 be-ing a Romless device, it cannot operate in singlechip mode. Hence, theEA pin must be forced at 0during reset.

7.2 EXTERNAL BUS MODES

When the external bus interface is enabled (bitBUSACTx=’1’) and configured (bitfield BTYP), theST10R163 uses a subset of its port lines togetherwith some control lines to build the external bus.

The bus configuration (BTYP) for the address win-dows (BUSCON4...BUSCON1) is selected viasoftware typically during the initialization of thesystem.

The bus configuration (BTYP) for the default ad-dress range (BUSCON0) is selected via PORT0during reset, provided that pinEA is low during re-set. Afterwards, BUSCON0 may be modified viasoftware just like the other BUSCON registers.

The 16 MByte address space of the ST10R163 isdivided into 256 segments of 64 KByte each. The16-bit intra-segment address is output on PORT0for multiplexed bus modes or on PORT1 for de-multiplexed bus modes. When segmentation isdisabled, only one 64 KByte segment can be usedand accessed. Otherwise additional address linesmay be output on Port 4, and/or several chip se-lect lines may be used to select different memorybanks or peripherals. These functions are select-ed during reset via bitfields SALSEL and CSSELof register RP0H, respectively.

Note : Bit SGTDIS of register SYSCON defines, ifthe CSP register is saved during interrupt entry(segmentation active) or not (segmentation disa-bled).

Multiplexed Bus Modes

In the multiplexed bus modes the 16-bit intra-seg-ment address as well as the data use PORT0. Theaddress is time-multiplexed with the data and hasto be latched externally. The width of the requiredlatch depends on the selected data bus width, ie.an 8-bit data bus requires a byte latch (the ad-dress bits A15...A8 on P0H do not change, whileP0L multiplexes address and data), a 16-bit databus requires a word latch (the least significant ad-dress line A0 is not relevant for word accesses).The upper address lines (An...A16) are perma-nently output on Port 4 (if segmentation is ena-bled) and do not require latches.

The EBC initiates an external access by generat-ing the Address Latch Enable signal (ALE) andthen placing an address on the bus. The fallingedge of ALE triggers an external latch to capturethe address. After a period of time during whichthe address must have been latched externally,the address is removed from the bus. The EBCnow activates the respective command signal(RD, WR, WRL, WRH). Data is driven onto thebus either by the EBC (for write cycles) or by theexternal memory/peripheral (for read cycles). Af-ter a period of time, which is determined by the ac-cess time of the memory/peripheral, data becomevalid.

Read cycles: Input data is latched and the com-mand signal is now deactivated. This causes theaccessed device to remove its data from the buswhich is then tri-stated again.

Write cycles: The command signal is now deacti-vated. The data remain valid on the bus until thenext external bus cycle is started.

BTYP Encoding External Data Bus Width External Address Bus Mode

0 0 8-bit Data Demultiplexed Addresses

0 1 8-bit Data Multiplexed Addresses

1 0 16-bit Data Demultiplexed Addresses

1 1 16-bit Data Multiplexed Addresses

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EXTERNAL BUS MODES (Cont’d)

Figure 4-2. Multiplexed Bus Cycle

Demultiplexed Bus Modes

In the demultiplexed bus modes the 16-bit intra-segment address is permanently output onPORT1, while the data uses PORT0 (16-bit data)or P0L (8-bit data).The upper address lines are permanently outputon Port 4 (if selected via SALSEL during reset).No address latches are required.The EBC initiates an external access by placingan address on the address bus. After a program-mable period of time the EBC activates the re-spective command signal (RD, WR, WRL, WRH).Data is driven onto the data bus either by the EBC

(for write cycles) or by the external memory/pe-ripheral (for read cycles). After a period of time,which is determined by the access time of thememory/peripheral, data become valid.

Read cycles: Input data is latched and the com-mand signal is now deactivated. This causes theaccessed device to remove its data from the databus which is then tri-stated again.

Write cycles: The command signal is now deacti-vated. If a subsequent external bus cycle is re-quired, the EBC places the respective address onthe address bus. The data remain valid on the busuntil the next external bus cycle is started.

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Figure 4-3. Demultiplexed Bus Cycle

Switching between the Bus Modes

The EBC allows to switch between different busmodes dynamically, ie. subsequent external buscycles may be executed in different ways. Certainaddress areas may use multiplexed or demulti-plexed buses or useREADY control or predefinedwaitstates.A change of the external bus characteristics canbe initiated in two different ways:Reprogramming the BUSCON and/or ADDR-SEL registers allows to either change the busmode for a given address window, or change thesize of an address window that uses a certain busmode. Reprogramming allows to use a greatnumber of different address windows (more thanBUSCONs are available) on the expense of theoverhead for changing the registers and keepingappropriate tables.

Switching between predefined address win-dows automatically selects the bus mode that isassociated with the respective window. Prede-fined address windows allow to use different busmodes without any overhead, but restrict theirnumber to the number of BUSCONs. However, asBUSCON0 controls all address areas, which arenot covered by the other BUSCONs, this allows tohave gaps between these windows, which use thebus mode of BUSCON0.

PORT1 will output the intra-segment address,when any of the BUSCON registers selects a de-multiplexed bus mode, even if the current bus cy-cle uses a multiplexed bus mode. This allows tohave an external address decoder connected toPORT1 only, while using it for all kinds of bus cy-cles.

Note : Never change the configuration for an ad-dress area that currently supplies the instructionstream. Due to the internal pipelining it is very dif-ficult to determine the first instruction fetch that willuse the new configuration. Only change the con-figuration for address areas that are not currentlyaccessed. This applies to BUSCON registers aswell as to ADDRSEL registers.

The usage of the BUSCON/ADDRSEL registers iscontrolled via the issued addresses. When an ac-cess (code fetch or data) is initiated, the respec-tive generated physical address defines, if the ac-cess is made internally, uses one of the addresswindows defined by ADDRSEL4...1, or uses thedefault configuration in BUSCON0. After initializ-ing the active registers, they are selected andevaluated automatically by interpreting the physi-cal address. No additional switching or selecting isnecessary during run time, except when morethan the four address windows plus the default isto be used.

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EXTERNAL BUS MODES (Cont’d)Switching from demultiplexed to multiplexedbus mode represents a special case. The bus cy-cle is started by activating ALE and driving the ad-dress to Port 4 and PORT1 as usual, if anotherBUSCON register selects a demultiplexed bus.However, in the multiplexed bus modes the ad-dress is also required on PORT0. In this specialcase the address on PORT0 is delayed by oneCPU clock cycle, which delays the complete (mul-tiplexed) bus cycle and extends the correspondingALE signal (see figure below).

This extra time is required to allow the previouslyselected device (via demultiplexed bus) to releasethe data bus, which would be available in a demul-tiplexed bus cycle.

External Data Bus WidthThe EBC can operate on 8-bit or 16-bit wide exter-nal memory/peripherals. A 16-bit data bus usesPORT0, while an 8-bit data bus only uses P0L, thelower byte of PORT0. This saves on addresslatches, bus transceivers, bus routing and memo-ry cost on the expense of transfer time. The EBCcan control word accesses on an 8-bit data bus aswell as byte accesses on a 16-bit data bus.Word accesses on an 8-bit data bus are auto-matically split into two subsequent byte accesses,where the low byte is accessed first, then the highbyte. The assembly of bytes to words and the dis-assembly of words into bytes is handled by theEBC and is transparent to the CPU and the pro-grammer.

Figure 4-4. Switching from demultiplexed to Multiplexed Bus Mode

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EXTERNAL BUS MODES (Cont’d)Byte accesses on a 16-bit data bus require thatthe upper and lower half of the memory can be ac-cessed individually. In this case the upper byte isselected with theBHE signal, while the lower byteis selected with the A0 signal. So the two bytes ofthe memory can be enabled independent fromeach other, or together when accessing words.When writing bytes to an external 16-bit device,which has a single CS input, but two WR enableinputs (for the two bytes), the EBC can directlygenerate these two write control signals. Thissaves the external combination of theWR signalwith A0 or BHE. In this case pin WR serves asWRL (write low byte) and pinBHE serves as WRH(write high byte). Bit WRCFG in register SYSCONselects the operating mode for pinsWR and BHE.The respective byte will be written on both databus halves.When reading bytes from an external 16-bit de-vice, whole words may be read and the ST10R163automatically selects the byte to be input and dis-cards the other. However, care must be taken

when reading devices that change state when be-ing read, like FIFOs, interrupt status registers, etc.In this case individual bytes should be selectedusing BHE and A0.PORT1 gets available for general purpose IO,when none of the BUSCON registers selects a de-multiplexed bus mode.Disable/Enable Control for PinBHE (BYTDIS)Bit BYTDIS of SYSCON register is provided forcontrolling the active low Byte High Enable (BHE)pin. The function of the BHE pin is enabled, if theBYTDIS bit contains a ’0’. Otherwise, it is disabledand the pin can be used as standard IO pin. TheBHE pin is implicitly used by the External BusController to select one of two byte-organizedmemory chips, which are connected to theST10R163 via a word-wide external data bus. Af-ter reset the BHE function is automatically ena-bled (BYTDIS = ’0’), if a 16-bit data bus is selectedduring reset, otherwise it is disabled (BYTDIS=’1’).It may be disabled, if byte access to 16-bit memo-ry is not required, and theBHE signal is not used.

Segment Address GenerationDuring external accesses the EBC generates a(programmable) number of address lines on Port4, which extend the 16-bit address output onPORT0 or PORT1, and so increase the accessibleaddress space. The number of segment address

lines is selected during reset and coded in bit fieldSALSEL in register RP0H (see table below).

Note : The total accessible address space may beincreased by accessing several banks which aredistinguished by individual chip select signals.

Bus Mode Transfer Rate ( Speed factor forbyte/word/dword access)

System Requirements Free IO Lines

8-bit Multiplexed Very low ( 1.5 / 3 / 6 ) Low (8-bit latch, byte bus) P1H, P1L

8-bit Demultipl. Low ( 1 / 2 / 4 ) Very low (no latch, byte bus) P0H

16-bit Multiplexed High ( 1.5 / 1.5 / 3 ) High (16-bit latch, word bus) P1H, P1L

16-bit Demultipl. Very high ( 1 / 1 / 2 ) Low (no latch, word bus) ---

SALSEL Segment Address Lines Directly accessible Address Space

1 1 Two:A17...A16 256KByte (Default without pull-downs)

1 0 Eight:A23...A16 16MByte (Maximum)

0 1 None 64KByte (Minimum)

0 0 Four:A19...A16 1MByte

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CS Signal Generation

During external accesses the EBC can generate a(programmable) number of CS lines on Port 6,which allow to directly select external peripheralsor memory banks without requiring an external de-coder. The number of CS lines is selected duringreset and coded in bit field CSSEL in registerRP0H (see table below).

The CSx outputs are associated with the BUS-CONx registers and are driven active (low) for anyaccess within the address area defined for the re-spective BUSCON register. For any access out-side this defined address area the respectiveCSxsignal will go inactive (high).

Note: No CSx signal will be generated for an ac-cess to any internal address area, even if this areais covered by the respective ADDRSELx register.

The chip select signals allow to be operated in fourdifferent modes, which are selected via bits CS-WENx and CSRENx in the respective BUSCONxregister.

Address Chip Select signals remain active forthe whole external bus cycle. An address chip se-lect becomes active with the falling edge of ALEand becomes inactive with the falling edge of ALEof an external bus cycle that accesses a differentaddress area. No spikes will be generated on thechip select lines.

Read or Write Chip Select signals remain activeonly as long as the associated control signal (RDor WR) is active. This also includes the program-mable read/write delay. Read chip select is onlyactivated for read cycles, write chip select is onlyactivated for write cycles, read/write chip select isactivated for both read and write cycles (write cy-cles are assumed, if any of the signals WRH orWRL gets active). These modes save externalglue logic, when accessing external devices likelatches or drivers that only provide a single enableinput.

CS0 provides an address chip select directly afterreset (except for single chip mode) when the firstinstruction is fetched.

Internal pullup devices hold the selectedCS lineshigh during reset. After the end of a reset se-quence the pullup devices are switched off andthe pin drivers control the pin levels on the select-ed CS lines. Not selected CS lines will enter thehigh-impedance state and are available for gener-al purpose IO.

The pullup devices are also active during bushold, while HLDA is active and the respective pinis switched to push/pull mode. Open drain outputswill float during bus hold. In this case external pul-lup devices are required or the new bus master isresponsible for driving appropriate levels on theCS lines.

Segment Address versus Chip Select

The external bus interface of the ST10R163 sup-ports many configurations for the external memo-ry. By increasing the number of segment addresslines the ST10R163 can address a linear addressspace of 256 KByte, 1 MByte or 16 MByte. This al-lows to implement a large sequential memory ar-ea, and also allows to access a great number ofexternal devices, using an external decoder. Byincreasing the number ofCS lines the ST10R163can access memory banks or peripherals withoutexternal glue logic. These two features may becombined to optimize the overall system perform-ance. Enabling 4 segment address lines and 5chip select lines eg. allows to access five memorybanks of 1 MByte each. So the available addressspace is 5 MByte (without glue logic).

Note : Bit SGTDIS of register SYSCON defines, ifthe CSP register is saved during interrupt entry(segmentation active) or not (segmentation disa-bled).

CSSEL Chip Select Lines Note

1 1 Five:CS4...CS0 Default without pull-downs

1 0 None Port 6 pins free for IO

0 1 Two:CS1...CS0

0 0 Three:CS2...CS0

CSWENx CSRENx Chip Select Mode

0 0Address Chip Select (Defaultafter Reset)

0 1 Read Chip Select

1 0 Write Chip Select

1 1 Read/Write Chip Select

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7.3 PROGRAMMABLE BUS CHARACTERISTICS

Important timing characteristics of the externalbus interface have been made user programma-ble to allow to adapt it to a wide range of differentexternal bus and memory configurations with dif-ferent types of memories and/or peripherals.The following parameters of an external bus cycleare programmable:• ALE Control defines the ALE signal length andthe address hold time after its falling edge• Memory Cycle Time (extendable with 1...15waitstates) defines the allowable access time

• Memory Tri-State Time (extendable with 1 wait-state) defines the time for a data driver to float• Read/Write Delay Time defines when a com-mand is activated after the falling edge of ALE• READY Control defines, if a bus cycle is termi-nated internally or externally

Note : Internal accesses are executed with maxi-mum speed and therefore are not programmable.External acceses use the slowest possible bus cy-cle after reset. The bus cycle timing may then beoptimized by the initialization software.

Figure 4-5. Programmable External Bus Cycle

ALECTL MCTC MTTC

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PROGRAMMABLE BUS CHARACTERISTICS (Cont’d)ALE Length ControlThe length of the ALE signal and the address holdtime after its falling edge are controlled by theALECTLx bits in the BUSCON registers. When bitALECTL is set to ‘1’, external bus cycles access-ing the respective address window will have theirALE signal prolonged by half a CPU clock (25 nsat fCPU = 20 MHz). Also the address hold time af-ter the falling edge of ALE (on a multiplexed bus)

will be prolonged by half a CPU clock, so the datatransfer within a bus cycle refers to the same CLK-OUT edges as usual (ie. the data transfer is de-layed by one CPU clock). This allows more timefor the address to be latched.

Note : ALECTL0 is ‘1’ after reset to select the slow-est possible bus cycle, the other ALECTLx are ‘0’after reset.

Figure 4-6. ALE Length Control

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PROGRAMMABLE BUS CHARACTERISTICS (Cont’d)Programmable Memory Cycle TimeThe ST10R163 allows the user to adjust the con-troller’s external bus cycles to the access time ofthe respective memory or peripheral. This accesstime is the total time required to move the data tothe destination. It represents the period of timeduring which the controller’s signals do notchange.The external bus cycles of the ST10R163 can beextended for a memory or peripheral, which can-not keep pace with the controller’s maximum

speed, by introducing wait states during the ac-cess (see figure above). During these memory cy-cle time wait states, the CPU is idle, if this accessis required for the execution of the current instruc-tion.

The memory cycle time wait states can be pro-grammed in increments of one CPU clock (50 nsat fCPU = 20 MHz) within a range from 0 to 15 (de-fault after reset) via the MCTC fields of the BUS-CON registers. 15-<MCTC> waitstates will be in-serted.

Figure 4-7. Memory Cycle Time

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PROGRAMMABLE BUS CHARACTERISTICS (Cont’d)Programmable Memory Tri-State TimeThe ST10R163 allows the user to adjust the timebetween two subsequent external accesses to ac-count for the tri-state time of the external device.The tri-state time defines, when the external devicehas released the bus after deactivation of theread command (RD).The output of the next address on the external buscan be delayed for a memory or peripheral, whichneeds more time to switch off its bus drivers, by in-troducing a waitstate after the previous bus cycle(see figure above). During this memory tri-state

time wait state, the CPU is not idle, so CPU oper-ations will only be slowed down if a subsequentexternal instruction or data fetch operation is re-quired during the next instruction cycle.The memory tri-state time waitstate requires oneCPU clock (50 ns at fCPU = 20 MHz) and is con-trolled via the MTTCx bits of the BUSCON regis-ters. A waitstate will be inserted, if bit MTTCx is ‘0’(default after reset).Note : External bus cycles in multiplexed busmodes implicitly add one tri-state time waitstate inaddition to the programmable MTTC waitstate.

Figure 4-8. Memory Tri-State Time

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PROGRAMMABLE BUS CHARACTERISTICS (Cont’d)Read/Write Signal DelayThe ST10R163 allows the user to adjust the timingof the read and write commands to account fortiming requirements of external peripherals. Theread/write delay controls the time between the fall-ing edge of ALE and the falling edge of the com-mand. Without read/write delay the falling edgesof ALE and command(s) are coincident (except forpropagation delays). With the delay enabled, thecommand(s) become active half a CPU clock (25ns at fCPU = 20 MHz) after the falling edge ofALE.

The read/write delay does not extend the memorycycle time, and does not slow down the controllerin general. In multiplexed bus modes, however,the data drivers of an external device may conflictwith the ST10R163’s address, when the earlyRDsignal is used. Therefore multiplexed bus cyclesshould always be programmed with read/write de-lay.The read/write delay is controlled via the RWDCxbits in the BUSCON registers. The command(s)will be delayed, if bit RWDCx is ‘0’ (default after re-set).

Figure 4-9. Read/Write Delay

1) The data drivers from the previous bus cycle should be disabled when the RD signal becomes active.

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7.4 READY CONTROLLED BUS CYCLES

For situations, where the programmable wait-states are not enough, or where the response (ac-cess) time of a peripheral is not constant, theST10R163 provides external bus cycles that areterminated via a READY input signal (synchro-nous or asynchronous). In this case theST10R163 first inserts a programmable number ofwaitstates (0...7) and then monitors the READYline to determine the actual end of the current buscycle. The external device drives READY low inorder to indicate that data have been latched(write cycle) or are available (read cycle).The READY function is enabled via the RDYENxbits in the BUSCON registers. When this functionis selected (RDYENx = ‘1’), only the lower 3 bits ofthe respective MCTC bit field define the number ofinserted waitstates (0...7), while the MSB of bitfield MCTC selects theREADY operation:

MCTC.3 = ‘0’: Synchronous READY, ie. theREADY signal must meet setup and hold times.MCTC.3 = ‘1’: Asynchronous READY, ie. theREADY signal is synchronized internally.

The synchronous READY provides the fastestbus cycles, but requires setup and hold times tobe met. The CLKOUT signal must be enabledand may be used by the peripheral logic to controlthe READY timing in this case.

The asynchronousREADY is less restrictive, butrequires additional waitstates caused by the inter-nal synchronization. As the asynchronousREADYis sampled earlier (see figure above) programmedwaitstates may be necessary to provide properbus cycles (see also notes on “normally-ready”peripherals below).

Figure 4-10. READY Controlled Bus Cycles

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READY CONTROLLED BUS CYCLES (Cont’d)A READY signal (especially asynchronousREADY) that has been activated by an externaldevice may be deactivated in response to the trail-ing (rising) edge of the respective command (RDor WR).Note: When the READY function is enabled for aspecific address window, each bus cycle withinthis window must be terminated with an activeREADY signal. Otherwise the controller hangs un-til the next reset. A timeout function is only provid-ed by the watchdog timer.Combining the READY function with prede-fined waitstates is advantageous in two cases:Memory components with a fixed access time andperipherals operating with READY may begrouped into the same address window. The (ex-ternal) waitstate control logic in this case wouldactivate READY either upon the memory’s chipselect or with the peripheral’s READY output. Af-ter the predefined number of waitstates theST10R163 will check itsREADY line to determinethe end of the bus cycle. For a memory access itwill be low already (see example a) in the figureabove), for a peripheral access it may be delayed(see example b) in the figure above). As memoriestend to be faster than peripherals, there should beno impact on system performance.When using the READY function with “normally-ready” peripherals, it may lead to erroneous buscycles, if the READY line is sampled too early.These peripherals pull their READY output low,while they are idle. When they are accessed, they

deactivate READY until the bus cycle is complete,then drive it low again. If, however, the peripheraldeactivates READY after the first sample point ofthe ST10R163, the controller samples an activeREADY and terminates the current bus cycle,which, of course, is too early. By inserting prede-fined waitstates the firstREADY sample point canbe shifted to a time, where the peripheral hassafely controlled theREADY line (eg. after 2 wait-states in the figure above).

7.5 CONTROLLING THE EXTERNAL BUSCONTROLLER

A set of registers controls the functions of theEBC. General features like the usage of interfacepins (WR, BHE), segmentation and internal ROMmapping are controlled via register SYSCON. Theproperties of a bus cycle like chip select mode, us-age of READY, length of ALE, external bus mode,read/write delay and waitstates are controlled viaregisters BUSCON4...BUSCON0. Four of theseregisters (BUSCON4...BUSCON1) have an ad-dress select register (ADDRSEL4...ADDRSEL1)associated with them, which allows to specify upto four address areas and the individual bus char-acteristics within these areas. All accesses thatare not covered by these four areas are then con-trolled via BUSCON0. This allows to use memorycomponents or peripherals with different interfac-es within the same system, while optimizing ac-cesses to each of them.

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CONTROLLING THE EXTERNAL BUS CONTROLLER (Cont’d)

SYSCON (FF12h / 89h) SFR Reset Value:0XX0h

Note: Register SYSCON cannot be changed after execution of the EINIT instruction.Bit SGTDIS controls the correct stack operation (push/pop of CSP or not) during traps and interrupts. Bits markedwith “-” must be kept at 0.

Bit Function

XPER-SHAREXBUS Peripheral Share Mode Control

‘0’: External accesses to XBUS peripherals are disbled‘1’: XBUS peripherals are accessible via the external bus during hold mode.

VISIBLEVisible Mode Control

‘0’: Accesses to XBUS peripherals are done internally‘1’: XBUS peripheral accesses are made visible on the external pins.

SSPENXperipheral SSP Enable Control‘0’: SSP is disabled. Pins P4.[7..4] are general purpose IOs or segment address lines‘1’: SSP is enabled. Pins P4.[7..4] are SSP IOs or segment address lines

WRCFGWrite Configuration Control (Set according to pin P0H.0 during reset)

‘0’: Pins WR and BHE retain their normal function‘1’: Pin WR acts as WRL, pin BHE acts as WRH

CLKENSystem Clock Output Enable (CLKOUT)

‘0’: CLKOUT disabled: pin may be used for general purpose IO‘1’: CLKOUT enabled: pin outputs the system clock signal

BYTDISDisable/Enable Control for Pin BHE (Set according to data bus width)

‘0’: Pin BHE enabled‘1’: Pin BHE disabled, pin may be used for general purpose IO

ROMEN

Internal ROM Enable (Set according to pin EA during reset)

‘0’: Internal ROM disabled: accesses to the ROM area use the external bus‘1’: Internal ROM enabled

This bit is not relevant on the ST10R165, since it does not include internal ROM. It should bekept at 0

SGTDISSegmentation Disable/Enable Control

‘0’: Segmentation enabled (CSP is saved/restored during interrupt entry/exit)‘1’: Segmentation disabled (Only IP is saved/restored)

ROMS1Internal ROM mapping

This bit is not relevant on the ST10R165, since it does not include internal ROM. It should bekept at 0.

STKSZSystem Stack Size

Selects the size of the system stack (in the internal RAM) from 32 to 1024 words

XPER-SHARE

VISIBLE- - - -

SSPEN

ROMS1

WRCFG

5 4 3 2 1 011 10 9 8 7 615 14 13 12

- - rwrw rw rwrw rw

STKSZSGTDIS

ROMEN

-

BYTDIS

CLKEN

rw - rw rw-

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CONTROLLING THE EXTERNAL BUS CONTROLLER (Cont’d)The layout of the five BUSCON registers is identi-cal. Registers BUSCON4...BUSCON1, which con-trol the selected address windows, are completelyunder software control, while register BUSCON0,which eg. is also used for the very first code ac-

cess after reset, is partly controlled by hardware,ie. it is initialized via PORT0 during the reset se-quence. This hardware control allows to define anappropriate external bus for systems, where no in-ternal program memory is provided.

BUSCON0 (FF0Ch / 86h) SFR Reset Value: 0XX0h

BUSCON1 (FF14h / 8Ah) SFR Reset Value: 0000h

BUSCON2 (FF16h / 8Bh) SFR Reset Value: 0000h

BUSCON3 (FF18h / 8Ch) SFR Reset Value: 0000h

BUSCON4 (FF1Ah / 8Dh) SFR Reset Value: 0000h

Note: BUSACT0 is initialized with 0, if pin EA is high during reset. If pin EA is low during reset, bit BUSACT0 is set.ALECTL0 is set (‘1’) and bit field BTYP is loaded with the bus configuration selected via PORT0.

-CSREN0

CSWEN0 -

MTTC0

RWDC0

RDYEN0

5 4 3 2 1 011 10 9 8 7 615 14 13 12

rw rwrw rw rwrw rwrw - -

-BUSACT0

rw

ALECTL0

- rw

BTYP0 MCTC0

- --MTTC1

RWDC1

RDYEN1

5 4 3 2 1 011 10 9 8 7 615 14 13 12

rw rwrw rw rwrw rw

BTYP1 MCTC1

rw - -

BUSACT1

rw

ALECTL1

- rw

CSWEN1

CSREN1

- --MTTC2

RWDC2

RDYEN2

5 4 3 2 1 011 10 9 8 7 615 14 13 12

rw rwrw rw rwrw rw

BTYP2 MCTC2

rw - -

BUSACT2

rw

ALECTL2

- rw

CSWEN2

CSREN2

- --MTTC3

RWDC3

RDYEN3

5 4 3 2 1 011 10 9 8 7 615 14 13 12

rw rwrw rw rwrw rw

BTYP3 MCTC3

rw - -

BUSACT3

rw

ALECTL3

- rw

CSWEN3

CSREN3

- --MTTC4

RWDC4

RDYEN4

5 4 3 2 1 011 10 9 8 7 615 14 13 12

rw rwrw rw rwrw rw

BTYP4 MCTC4

rw - -

BUSACT4

rw

ALECTL4

- rw

CSWEN4

CSREN4

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Note: BUSACT0 is initialized with 0, if pin EA is high during reset. If pin EA is low during reset, bit BUSACT0 is set.ALECTL0 is set (‘1’) and bit field BTYP is loaded with the bus configuration selected via PORT0.

Bit Function

MCTCx

Memory Cycle Time Control (Number of memory cycle time wait states)

0 0 0 0 : 15 waitstates (Number = 15 - <MCTC>). . .1 1 1 1 : No waitstates

RWDCx

Read/Write Delay Control for BUSCONx

‘0’: With read/write delay: activate command 1 TCL after falling edge of ALE

‘1’: No read/write delay: activate command with falling edge of ALE

MTTCxMemory Tristate Time Control

‘0’: 1 waitstate‘1’: No waitstate

BTYPx

External Bus Configuration

0 0 : 8-bit Demultiplexed Bus0 1 : 8-bit Multiplexed Bus1 0 : 16-bit Demultiplexed Bus1 1 : 16-bit Multiplexed Bus

Note: For BUSCON0 BTYP is defined via PORT0 during reset.

ALECTLxALE Lengthening Control

‘0’: Normal ALE signal‘1’: Lengthened ALE signal

BUSACTxBus Active Control

‘0’: External bus disabled‘1’: External bus enabled (within the respective address window, see ADDRSEL)

RDYENxREADY Input Enable

‘0’: External bus cycle is controlled by bit field MCTC only‘1’: External bus cycle is controlled by the READY input signal

CSRENxRead Chip Select Enable

‘0’: The CS signal is independent of the read command (RD)‘1’: The CS signal is generated for the duration of the read command

CSWENxWrite Chip Select Enable

‘0’: The CS signal is independent of the write command (WR,WRL,WRH)‘1’: The CS signal is generated for the duration of the write command

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ADDRSEL1 (FE18h / 0Ch) SFR Reset Value: 0000h

ADDRSEL2 (FE1Ah / 0Dh) SFR Reset Value: 0000h

ADDRSEL3(FE1Ch / 0Eh) SFR Reset Value: 0000h

ADDRSEL4 (FE1Eh / 0Fh) SFR Reset Value: 0000h

Note: There is no register ADDRSEL0, as register BUSCON0 controls all external accesses outside the four addresswindows of BUSCON4...BUSCON1 within the complete address space.

5 4 3 2 1 011 10 9 8 7 615 14 13 12

rw

RGSAD RGSZ

rw

5 4 3 2 1 011 10 9 8 7 615 14 13 12

rw

RGSAD RGSZ

rw

5 4 3 2 1 011 10 9 8 7 615 14 13 12

rw

RGSAD RGSZ

rw

5 4 3 2 1 011 10 9 8 7 615 14 13 12

rw

RGSAD RGSZ

rw

Bit Function

RGSZRange Size Selection

Defines the size of the address area controlled by the respective BUSCONx/ADDRSELx registerpair. See table below.

RGSADRange Start Address

Defines the upper bits of the start address (A23...) of the respective address area. See table be-low.

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CONTROLLING THE EXTERNAL BUS CONTROLLER (Cont’d)Definition of Address AreasThe four register pairs BUSCON4/AD-DRSEL4...BUSCON1/ADDRSEL1 allow to define4 separate address areas within the addressspace of the ST10R163. Within each of these ad-dress areas external accesses can be controlledby one of the four different bus modes, independ-ent of each other and of the bus mode specified inregister BUSCON0. Each ADDRSELx register in away cuts out an address window, within which the

parameters in register BUSCONx are used to con-trol external accesses. The range start address ofsuch a window defines the upper address bits,which are not used within the address window ofthe specified size (see table below). For a givenwindow size only those upper address bits of thestart address are used (marked “R”), which are notimplicitly used for addresses inside the window.The lower bits of the start address (marked “x”)are disregarded.

Prioritizing of Address AreasTo allow a flexible use of ADDRSELs registers, acertain overlapping among address areas is pos-sible due to a prioritizing scheme.The ADDRSELs registers are split into twogroups:The first group with ADDRSEL1 and ADDRSEL2,gives to ADDRSEL2 a higher priority thanADDRSEL1. Thus, an overlapping among ad-dress areas defined via registers ADDRSEL1 and2 is alowed.

The other group with ADDRSEL3 andADDRSEL4, gives to ADDRSEL4 a higher prioritythan ADDRSEL3. Thus, an overlapping amongaddress areas defined via registers ADDRSEL3and 4 is alowed.

The BUSCON0 register always has the lowest pri-ority, and its address area can be overlapped byany of the other ADDRSELs.

The Xperipheral address areas defined viaXADRs registers always have higher priority thanaddress areas defined via ADDRSELs registers.

Bit field RGSZ Resulting Window Size Relevant Bits (R) of Start Address ( A23...A12)

0 0 0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 x x

4 KByte8 KByte

16 KByte32 KByte64 KByte

128 KByte256 KByte512 KByte1 MByte2 MByte4 MByte8 MByte

Reserved.

R R R R R R R R R R R RR R R R R R R R R R R xR R R R R R R R R R x xR R R R R R R R R x x xR R R R R R R R x x x xR R R R R R R x x x x xR R R R R R x x x x x xR R R R R x x x x x x xR R R R x x x x x x x xR R R x x x x x x x x xR R x x x x x x x x x xR x x x x x x x x x x x

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RP0h (F108h / 84h) SFR Reset Value: - - XXh

Note: RP0H cannot be changed via software, but rather allows to check the current configuration.

Precautions and Hints

• The external bus interface is enabled as long asat least one of the BUSCON registers has its BUS-ACT bit set.

• PORT1 will output the intra-segment address aslong as at least one of the BUSCON registers se-lects a demultiplexed external bus, even for multi-plexed bus cycles.

• The address areas defined via registersADDRSEL1 and ADDRSEL2 may not overlapad-dress areas defined via registers ADDRSEL3 andADDRESEL4. The operation of the EBC will beunpredictable in such a case.• The address areas defined via registers AD-DRSELx may overlap internal address areas. In-ternal accesses will be executed in this case.• For any access to an internal address area theEBC will remain inactive (see EBC Idle State).

Bit Function

WRCFG

Write Configuration Control

‘0’: Pins WR and BHE retain their normal function

‘1’: Pins WR acts as WRL, pin BHE acts as WRH

CSSEL

Chip Select Line Selection (Number of active CS outputs)

0 0: 3 CS lines: CS2...CS00 1: 2 CS lines: CS1...CS01 0: No CS lines at all1 1: 5 CS lines: CS4...CS0 (Default without pulldowns)

SALSEL

Segment Address Line Selection (Number of active segment address outputs)

0 0: 4-bit segment address: A19...A160 1: No segment address lines at all1 0: 8-bit segment address: A23...A161 1: 2-bit segment address: A17...A16 (Default without pulldowns)

CLKSEL

System Clock Selection

000: fCPU = 2.5 * fOSC001: fCPU = 0.5 * fOSC010: fCPU = 1.5 * fOSC011: fCPU = fOSC100: fCPU = 5 * fOSC101: fCPU = 2 * fOSC110: fCPU = 3 * fOSC111: fCPU = 4 * fOSC

WRCFGCLKSEL

5 4 3 2 1 011 10 9 8 7 615 14 13 12

r r- - - - r- - - -

CSSELSALSEL

r

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7.6 EBC IDLE STATE

When the external bus interface is enabled, but noexternal access is currently executed, the EBC isidle. During this idle state the external interfaceappears in the following way:

– PORT0 goes into high impedance (floating)

– PORT1 (if used for the bus interface) drives theaddress used last

– Port 4 (the activated pins) drives the segmentaddress used last

– Port 6 drives theCS signal corresponding to theaddress (see above), if enabled

– ALE remains inactive (low)

– RD/WR remain inactive (high)

7.7 EXTERNAL BUS ARBITRATION

In high performance systems it may be efficient toshare external resources like memory banks orperipheral devices among more than one control-ler. The ST10R163 supports this approach withthe possibility to arbitrate the access to its externalbus, ie. to the external devices.

This bus arbitration allows an external master torequest the ST10R163’s bus via theHOLD input.The ST10R163 acknowledges this request via theHLDA output and will float its bus lines in thiscase. The CS outputs may provide internal pullupdevices. The new master may now access the pe-ripheral devices or memory banks via the same in-terface lines as the ST10R163. During this timethe ST10R163 can keep on executing, as long asit does not need access to the external bus. All ac-tions that just require internal resources like in-struction or data memory and on-chip peripherals,may be executed in parallel.

When the ST10R163 needs access to its externalbus while it is occupied by another bus master, itdemands it via the BREQ output.The external bus arbitration is enabled by settingbit HLDEN in register PSW to ‘1’. This bit may becleared during the execution of program sequenc-es, where the external resources are required butcannot be shared with other bus masters. In thiscase the ST10R163 will not answer toHOLD re-quests from other external masters.The pins HOLD, HLDA and BREQ keep their alter-nate function (bus arbitration) even after the arbi-tration mechanism has been switched off by clear-ing HLDEN.All three pins are used for bus arbitration after bitHLDEN was set once.

Entering the Hold StateAccess to the ST10R163’s external bus is re-quested by driving its HOLD input low. After syn-chronizing this signal the ST10R163 will completea current external bus cycle (if any is active), re-lease the external bus and grant access to it bydriving the HLDA output low. During hold state theST10R163 treats the external bus interface as fol-lows:• Address and data bus(es) float to tri-state• ALE is pulled low by an internal pulldown device• Command lines are pulled high by internal pullupdevices (RD, WR/WRL, BHE/WRH)• CSx outputs are pulled high (push/pull mode) orfloat to tri-state (open drain mode)Should the ST10R163 require access to its exter-nal bus during hold mode, it activates its bus re-quest output BREQ to notify the arbitration circuit-ry. BREQ is activated only during hold mode. It willbe inactive during normal operation.

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EXTERNAL BUS ARBITRATION (Cont’d)

Figure 4-11. External Bus Arbitration, Releasing the Bus

Note: The ST10R163 will complete the currently running bus cycle before granting bus access as indicated by the brokenlines. This may delay hold acknowledge compared to this figure.The figure above shows the first possibility for BREQ to get active.

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EXTERNAL BUS ARBITRATION (Cont’d)Exiting the Hold StateThe external bus master returns the access rightsto the ST10R163 by driving theHOLD input high.After synchronizing this signal the ST10R163 willdrive the HLDA output high, actively drive the con-trol signals and resume executing external bus cy-cles if required.Depending on the arbitration logic, the externalbus can be returned to the ST10R163 under twocircumstances:

• The external master does no more require ac-cess to the shared resources and gives up its ownaccess rights, or• The ST10R163 needs access to the shared re-sources and demands this by activating itsBREQoutput. The arbitration logic may then deactivatethe other master’s HLDA and so free the externalbus for the ST10R163, depending on the priorityof the different masters.

Figure 4-12. External Bu s Arbitration, (Regaining the Bus)

Note: The falling BREQ edge shows the last chance for BREQ to trigger the indicated regain-sequence. Even if BREQis activated earlier the regain-sequence is initiated by HOLD going high. BREQ and HOLD are connected via anexternal arbitration circuitry. Please note that HOLD may also be deactivated without the ST10R163 requesting thebus.

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7.8 THE XBUS INTERFACE

The ST10R163 provides an on-chip interface (theXBUS interface), which allows to connect integrat-ed customer/application specific peripherals to thestandard controller core. The XBUS is an internalrepresentation of the external bus interface, ie. it isoperated in the same way.The current XBUS interface is prepared to supportup to 3 X-Peripherals.For each peripheral on the XBUS (X-Peripheral)there is a separate address window controlled byan XBCON and an XADRS register. As an inter-face to a peripheral in many cases is representedby just a few registers, the XADRS registers selectsmaller address windows than the standard AD-DRSEL registers. As the register pairs control in-tegrated peripherals rather than externally con-nected ones, they are fixed by mask programmingrather than being user programmable.

X-Peripheral accesses provide the same choicesas external accesses, so these peripherals maybe bytewide or wordwide, with or without a sepa-rate address bus. Interrupt nodes and configura-tion pins (on PORT0) are provided for X-Peripher-als to be integrated.Note : If you plan to develop a peripheral of yourown to be integrated into a ST10R163 device tocreate a customer specific version, please ask forthe specification of the XBUS interface and for fur-ther support.

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ST10R163User Manual

8 - GENERAL PURPOSE TIMER UNITS

The General Purpose Timer Units GPT1 andGPT2 represent very flexible multifunctional timerstructures which may be used for timing, eventcounting, pulse width measurement, pulse gener-ation, frequency multiplication, and other purpos-es. They incorporate five 16-bit timers that aregrouped into the two timer blocks GPT1 andGPT2.Block GPT1 contains 3 timers/counters with amaximum resolution of 400 ns (@ 20 MHz CPUclock), while block GPT2 contains 2 tim-ers/counters with a maximum resolution of 200 ns(@ 20 MHz CPU clock) and a 16-bit Capture/Re-load register (CAPREL). Each timer in each blockmay operate independently in a number of differ-ent modes such as gated timer or counter mode,

or may be concatenated with another timer of thesame block. The auxiliary timers of GPT1 may op-tionally be configured as reload or capture regis-ters for the core timer. In the GPT2 block, the ad-ditional CAPREL register supports capture and re-load operation with extended functionality. Eachblock has alternate input/output functions andspecific interrupts associated with it.

8.1 TIMER BLOCK GPT1

From a programmer’s point of view, the GPT1block is composed of a set of SFRs as summa-rized below. Those portions of port and directionregisters which are used for alternate functions bythe GPT1 block are shaded.

Figure 5-1. SFRs and Port Pins Associated with Timer Block GPT1

T4IC

T2 GPT1 Timer 2 RegisterT3 GPT1 Timer 3 RegisterT4 GPT1 Timer 4 RegisterT2IC GPT1 Timer 2 Interrupt Control RegisterT3IC GPT1 Timer 3 Interrupt Control RegisterT4IC GPT1 Timer 4 Interrupt Control Register

T2IN/P3.7 T2EUD/P5.15T3IN/P3.6 T3EUD/P3.4T4IN/P3.5 T4EUD/P5.14T3OUT/P3.3

T2CON


Data Registers Control Registers Interrupt Control

T2 T2IC

DP3

P3

T3

T4

T3ICT3CON

T4CON

P5

ODP3

ODP3 Port 3 Open Drain Control RegisterDP3 Port 3 Direction Control RegisterP3 Port 3 Data RegisterT2CON GPT1 Timer 2 Control RegisterT3CON GPT1 Timer 3 Control RegisterT4CON GPT1 Timer 4 Control Register

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8 - GENERAL PURPOSE TIMER UNITS (ST10R163)

TIMER BLOCK GPT1 (Cont’d)All three timers of block GPT1 (T2, T3, T4) can runin 3 basic modes, which are timer, gated timer,and counter mode, and all timers can either countup or down. Each timer has an alternate inputfunction pin on Port 3 associated with it whichserves as the gate control in gated timer mode, oras the count input in counter mode. The count di-rection (Up / Down) may be programmed via soft-ware or may be dynamically altered by a signal atan external control input pin. Each overflow/under-flow of core timer T3 may be indicated on an alter-nate output function pin. The auxiliary timers T2and T4 may additionally be concatenated with the

core timer, or used as capture or reload registersfor the core timer.

The current contents of each timer can be read ormodified by the CPU by accessing the corre-sponding timer registers T2, T3, or T4, which arelocated in the non-bitaddressable SFR space.When any of the timer registers is written to by theCPU in the state immediately before a timer incre-ment, decrement, reload, or capture is to be per-formed, the CPU write operation has priority in or-der to guarantee correct results.

Figure 5-2. GPT1 Block Diagram

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TIMER BLOCK GPT1 (Cont’d)

8.1.1 GPT1 Core Timer T3The core timer T3 is configured and controlled via its bitaddressable control register T3CON.

T3CON (FF42h / A1h) SFR Reset Value: 0000h

*) For the effects of bits T3UD and T3UDE refer to the direction table below.

Bit Function

T3ITimer 3 Input Selection

Depends on the operating mode, see respective sections.

T3M

Timer 3 Mode Control (Basic Operating Mode)

0 0 0 :Timer Mode0 0 1 :Counter Mode0 1 0 :Gated Timer with Gate active low0 1 1 :Gated Timer with Gate active high1 X X :Reserved. Do not use this combination.

T3RTimer 3 Run Bit

T3R = ‘0’:Timer / Counter 3 stopsT3R = ‘1’:Timer / Counter 3 runs

T3UD Timer 3 Up / Down Control *)

T3UDE Timer 3 External Up/Down Enable *)

T3OEAlternate Output Function Enable

T3OE = ‘0’:Alternate Output Function DisabledT3OE = ‘1’:Alternate Output Function Enabled

T3OTLTimer 3 Output Toggle Latch

Toggles on each overflow / underflow of T3. Can be set or reset by software.

5 4 3 2 1 011 10 9 8 7 615 14 13 12

rw rwrw rw rw rw rw- - - -

T3RT3UDT3OE-----T3

OTLT3

UDE T3M T3I

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TIMER BLOCK GPT1 (Cont’d)Timer 3 Run Bit

The timer can be started or stopped by softwarethrough bit T3R (Timer T3 Run Bit). If T3R=‘0’, thetimer stops. Setting T3R to ‘1’ will start the timer.In gated timer mode, the timer will only run ifT3R=‘1’ and the gate is active (high or low, as pro-grammed).

Count Direction Control

The count direction of the core timer can be con-trolled either by software or by the external inputpin T3EUD (Timer T3 External Up/Down ControlInput), which is the alternate input function of portpin P3.4. These options are selected by bits T3UDand T3UDE in control register T3CON. When theup/down control is done by software (bitT3UDE=‘0’), the count direction can be altered bysetting or clearing bit T3UD. When T3UDE=‘1’, pinT3EUD is selected to be the controlling source ofthe count direction. However, bit T3UD can still beused to reverse the actual count direction, asshown in the table below. If T3UD=‘0’ and pinT3EUD shows a low level, the timer is countingup. With a high level at T3EUD the timer is count-ing down. If T3UD=‘1’, a high level at pin T3EUDspecifies counting up, and a low level specifiescounting down. The count direction can be

changed regardless of whether the timer is run-ning or not.When pin T3EUD/P3.4 is used as external countdirection control input, it must be configured as in-put, ie. its corresponding direction control bitDP3.4 must be set to ‘0’.Timer 3 Output Toggle LatchAn overflow or underflow of timer T3 will clock thetoggle bit T3OTL in control register T3CON.T3OTL can also be set or reset by software. BitT3OE (Alternate Output Function Enable) in regis-ter T3CON enables the state of T3OTL to be an al-ternate function of the external output pinT3OUT/P3.3. For that purpose, a ‘1’ must be writ-ten into port data latch P3.3 and pin T3OUT/P3.3must be configured as output by setting directioncontrol bit DP3.3 to ‘1’. If T3OE=‘1’, pin T3OUTthen outputs the state of T3OTL. If T3OE=‘0’, pinT3OUT can be used as general purpose IO pin.In addition, T3OTL can be used in conjunctionwith the timer over/underflows as an input for thecounter function or as a trigger source for the re-load function of the auxiliary timers T2 and T4. Forthis purpose, the state of T3OTL does not have tobe available at pin T3OUT, because an internalconnection is provided for this option.

GPT1 Core Timer T3 Count Direction Control

Note: The direction control works the same for core timer T3 and for auxiliary timers T2 and T4. Therefore the pins andbits are named Tx...

Pin TxEUD Bit TxUDE Bit TxUD Count Direction

X 0 0 Count Up

X 0 1 Count Down

0 1 0 Count Up

1 1 0 Count Down

0 1 1 Count Down

1 1 1 Count Up

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TIMER BLOCK GPT1 (Cont’d)Timer 3 in Timer ModeTimer mode for the core timer T3 is selected bysetting bit field T3M in register T3CON to ‘000b’. Inthis mode, T3 is clocked with the internal systemclock (CPU clock) divided by a programmableprescaler, which is selected by bit field T3I. The in-put frequency fT3 for timer T3 and its resolution rT3are scaled linearly with lower clock frequenciesfCPU, as can be seen from the following formula:The timer input frequencies, resolution and peri-ods which result from the selected prescaler op-

tion when using a 20 MHz CPU clock are listed inthe table below. This table also applies to the Gat-ed Timer Mode of T3 and to the auxiliary timers T2and T4 in timer and gated timer mode. Note thatsome numbers may be rounded to 3 significantdigits.

Figure 5-3. Block Diagram of Core Timer T3 in Timer Mode

GPT1 Timer Input Frequencies, Resolution and Periods

fT3 =fCPU

8 * 2<T3I>rT3 [µs] =

fCPU [MHz]

8 * 2<T3I>

T3EUD = P3.4T3OUT = P3.3

x = 3

fCPU = 20MHz Timer Input Selection T2I / T3I / T4I

000b 001b 010b 011b 100b 101b 110b 111b

Prescaler factor 8 16 32 64 128 256 512 1024

Input Frequency2.5MHz

1.25MHz

625kHz

312.5kHz

156.25kHz

78.125kHz

39.06kHz

19.53kHz

Resolution 400 ns 800 ns 1.6 µs 3.2 µs 6.4 µs 12.8 µs 25.6 µs 51.2 µs

Period 26 ms 52.5 ms 105 ms 210 ms 420 ms 840 ms 1.68 s 3.36 s

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TIMER BLOCK GPT1 (Cont’d)Timer 3 in Gated Timer ModeGated timer mode for the core timer T3 is selectedby setting bit field T3M in register T3CON to ‘010b’or ‘011b’. Bit T3M.0 (T3CON.3) selects the activelevel of the gate input. In gated timer mode thesame options for the input frequency as for thetimer mode are available. However, the inputclock to the timer in this mode is gated by the ex-ternal input pin T3IN (Timer T3 External Input),which is an alternate function of P3.6.To enable this operation pin T3IN/P3.6 must beconfigured as input, ie. direction control bit DP3.6must contain ‘0’.

If T3M.0=‘0’, the timer is enabled when T3INshows a low level. A high level at this pin stops thetimer. If T3M.0=‘1’, pin T3IN must have a high lev-el in order to enable the timer. In addition, the tim-er can be turned on or off by software using bitT3R. The timer will only run, if T3R=‘1’ and thegate is active. It will stop, if either T3R=‘0’ or thegate is inactive.

Note : A transition of the gate signal at pin T3INdoes not cause an interrupt request.

Figure 5-4. Block Diagram of Core Timer T3 in Gated Timer Mode

T3IN = P3.6T3EUD = P3.4T3OUT = P3.3

x = 3

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TIMER BLOCK GPT1 (Cont’d)Timer 3 in Counter ModeCounter mode for the core timer T3 is selected bysetting bit field T3M in register T3CON to ‘001b’. Incounter mode timer T3 is clocked by a transition atthe external input pin T3IN, which is an alternatefunction of P3.6. The event causing an incrementor decrement of the timer can be a positive, a neg-ative, or both a positive and a negative transitionat this pin. Bit field T3I in control register T3CONselects the triggering transition (see table below).

For counter operation, pin T3IN/P3.6 must be con-figured as input, ie. direction control bit DP3.6must be ‘0’. The maximum input frequency whichis allowed in counter mode is fCPU (1.25 MHz @fCPU = 20 MHz). To ensure that a transition of thecount input signal which is applied to T3IN is cor-rectly recognized, its level should be held high orlow for at least 8 fCPU cycles before it changes.

Figure 5-5. Block Diagram of Core Timer T3 in Counter Mode

GPT1 Core Timer T3 (Counter Mode) Input Edge Selection

T3IN = P3.6T3EUD = P3.4T3OUT = P3.3

x = 3

T3I Triggering Edge for Counter Increment / Decrement

0 0 0 None. Counter T3 is disabled

0 0 1 Positive transition (rising edge) on T3IN

0 1 0 Negative transition (falling edge) on T3IN

0 1 1 Any transition (rising or falling edge) on T3IN

1 X X Reserved. Do not use this combination

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8.1.2 GPT1 Auxiliary Timers T2 and T4Both auxiliary timers T2 and T4 have exactly thesame functionality. They can be configured fortimer, gated timer, or counter mode with the sameoptions for the timer frequencies and the countsignal as the core timer T3. In addition to these 3counting modes, the auxiliary timers can be con-catenated with the core timer, or they may be usedas reload or capture registers in conjunction withthe core timer.

Note : The auxiliary timers have no output togglelatch and no alternate output function.

The individual configuration for timers T2 and T4is determined by their bitaddressable control reg-isters T2CON and T4CON, which are both organ-ized identically. Note that functions which arepresent in all 3 timers of block GPT1 are controlledin the same bit positions and in the same mannerin each of the specific control registers.


T4CON (FF44h / A2h) SFR ResetValue:0000h

*) For the effects of bits TxUD and TxUDE refer to the direction table (see T3 section).

Bit Function

TxITimer x Input Selection

Depends on the Operating Mode, see respective sections.

TxM

Timer x Mode Control (Basic Operating Mode)

0 0 0 :Timer Mode0 0 1 :Counter Mode0 1 0 :Gated Timer with Gate active low0 1 1 :Gated Timer with Gate active high1 0 0 :Reload Mode1 0 1 :Capture Mode1 1 X :Reserved. Do not use this combination

TxRTimer x Run Bit

TxR = ‘0’:Timer / Counter x stopsTxR = ‘1’:Timer / Counter x runs

TxUD Timer x Up / Down Control *)

TxUDE Timer x External Up/Down Enable *)

5 4 3 2 1 011 10 9 8 7 615 14 13 12

rw rw- - - rw rw rw- - - -

T2RT2UD-----T2

UDE- - T2IT2M

5 4 3 2 1 011 10 9 8 7 615 14 13 12

rw rw- - - rw rw rw- - - -

T4RT4UD-----T4

UDE- - T4IT4M

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Count Direction Control for Auxiliary TimersThe count direction of the auxiliary timers can becontrolled in the same way as for the core timerT3. The description and the table apply according-ly.Timers T2 and T4 in Timer Mode or Gated Tim-er ModeWhen the auxiliary timers T2 and T4 are pro-grammed to timer mode or gated timer mode, theiroperation is the same as described for the coretimer T3. The descriptions, figures and tables ap-ply accordingly with one exception:

• There is no output toggle latch and no alternateoutput pin for T2 and T4.

Timers T2 and T4 in Counter Mode

Counter mode for the auxiliary timers T2 and T4 isselected by setting bit field TxM in the respectiveregister TxCON to ‘001b’. In counter mode timersT2 and T4 can be clocked either by a transition atthe respective external input pin TxIN, or by a tran-sition of timer T3’s output toggle latch T3OTL.

Figure 5-6. Block Diagram of an Auxiliary Timer in Counter Mode

The event causing an increment or decrement of atimer can be a positive, a negative, or both a pos-itive and a negative transition at either the respec-tive input pin, or at the toggle latch T3OTL.Bit field TxI in the respective control register Tx-CON selects the triggering transition (see tablebelow).

For counter operation, pin TxIN must be config-ured as input, ie. the respective direction controlbit must be ‘0’. The maximum input frequencywhich is allowed in counter mode is fCPU/8 (1.25MHz @ fCPU=20 MHz). To ensure that a transitionof the count input signal which is applied to TxIN iscorrectly recognized, its level should be held for atleast 8 fCPU cycles before it changes.

GPT1 Auxiliary Timer (Counter Mode) Input Edge Selection

Note: Only state transitions of T3OTL which are caused by the overflows/underflows of T3 will trigger the counter functionof T2/T4. Modifications of T3OTL via software will NOT trigger the counter function of T2/T4.

x = 2,4

T2I / T4I Triggering Edge for Counter Increment / DecrementX 0 0 None. Counter Tx is disabled0 0 1 Positive transition (rising edge) on TxIN0 1 0 Negative transition (falling edge) on TxIN0 1 1 Any transition (rising or falling edge) on TxIN1 0 1 Positive transition (rising edge) of output toggle latch T3OTL1 1 0 Negative transition (falling edge) of output toggle latch T3OTL1 1 1 Any transition (rising or falling edge) of output toggle latch T3OTL

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Timer ConcatenationUsing the toggle bit T3OTL as a clock source foran auxiliary timer in counter mode concatenatesthe core timer T3 with the respective auxiliary tim-er. Depending on which transition of T3OTL is se-lected to clock the auxiliary timer, this concatena-tion forms a 32-bit or a 33-bit timer / counter.• 32-bit Timer/Counter : If both a positive and anegative transition of T3OTL is used to clock theauxiliary timer, this timer is clocked on every over-flow/underflow of the core timer T3. Thus, the twotimers form a 32-bit timer.

• 33-bit Timer/Counter : If either a positive or anegative transition of T3OTL is selected to clockthe auxiliary timer, this timer is clocked on everysecond overflow/underflow of the core timer T3.This configuration forms a 33-bit timer (16-bit coretimer+T3OTL+16-bit auxiliary timer).

The count directions of the two concatenated tim-ers are not required to be the same. This offers awide variety of different configurations.T3 can operate in timer, gated timer or countermode in this case.

Figure 5-7. Concatenation of Core Timer T3 and an Auxiliary Timer

*) Note: Line only affected by over/underflows of T3, but NOT by software modifications of T3OTL.

T3OUT = P3.3 x = 2,4 y = 3

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TIMER BLOCK GPT1 (Cont’d)Auxiliary Timer in Reload ModeReload mode for the auxiliary timers T2 and T4 isselected by setting bit field TxM in the respectiveregister TxCON to ‘100b’. In reload mode the coretimer T3 is reloaded with the contents of an auxil-iary timer register, triggered by one of two differentsignals. The trigger signal is selected the sameway as the clock source for counter mode (see ta-ble above), ie. a transition of the auxiliary timer’sinput or the output toggle latch T3OTL may triggerthe reload.Note: When programmed for reload mode, the re-spective auxiliary timer (T2 or T4) stops independ-ent of its run flag T2R or T4R.Upon a trigger signal T3 is loaded with the con-tents of the respective timer register (T2 or T4)and the interrupt request flag (T2IR or T4IR) is set.Note: When a T3OTL transition is selected for thetrigger signal, also the interrupt request flag T3IR

will be set upon a trigger, indicating T3’s overflowor underflow.Modifications of T3OTL via software will NOT trig-ger the counter function of T2/T4.

The reload mode triggered by T3OTL can be usedin a number of different configurations. Dependingon the selected active transition the following func-tions can be performed:

• If both a positive and a negative transition ofT3OTL is selected to trigger a reload, the core tim-er will be reloaded with the contents of the auxilia-ry timer each time it overflows or underflows. Thisis the standard reload mode (reload on over-flow/underflow).

• If either a positive or a negative transition ofT3OTL is selected to trigger a reload, the core tim-er will be reloaded with the contents of the auxilia-ry timer on every second overflow or underflow.

Figure 5-8. GPT1 Auxiliary Timer in Reload Mode


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TIMER BLOCK GPT1 (Cont’d)• Using this “single-transition” mode for both auxil-iary timers allows to perform very flexible pulsewidth modulation (PWM). One of the auxiliary tim-ers is programmed to reload the core timer on apositive transition of T3OTL, the other is pro-grammed for a reload on a negative transition ofT3OTL. With this combination the core timer is al-ternately reloaded from the two auxiliary timers.The figure below shows an example for the gener-ation of a PWM signal using the alternate reloadmechanism. T2 defines the high time of the PWM

signal (reloaded on positive transitions) and T4defines the low time of the PWM signal (reloadedon negative transitions). The PWM signal can beoutput on T3OUT with T3OE=‘1’, P3.3=‘1’ andDP3.3=‘1’. With this method the high and low timeof the PWM signal can be varied in a wide range.

Note : The output toggle latch T3OTL is accessiblevia software and may be changed, if required, tomodify the PWM signal. However, this will NOTtrigger the reloading of T3.

Figure 5-9. GPT1 Timer Reload Configuration for PWM Generation

Note: Although it is possible, it should be avoided to select the same reload trigger event for both auxiliary timers. In thiscase both reload registers would try to load the core timer at the same time. If this combination is selected, T2 isdisregarded and the contents of T4 is reloaded.

*) Note: Lines only affected by over/underflows of T3, but NOT by software modifications of T3OTL.

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TIMER BLOCK GPT1 (Cont’d)Auxiliary Timer in Capture ModeCapture mode for the auxiliary timers T2 and T4 isselected by setting bit field TxM in the respectiveregister TxCON to ‘101b’. In capture mode thecontents of the core timer are latched into an aux-iliary timer register in response to a signal transi-tion at the respective auxiliary timer’s external in-put pin TxIN. The capture trigger signal can be apositive, a negative, or both a positive and a neg-ative transition.The two least significant bits of bit field TxI areused to select the active transition (see table in thecounter mode section), while the most significantbit TxI.2 is irrelevant for capture mode. It is recom-mended to keep this bit cleared (TxI.2 = ‘0’).

Note : When programmed for capture mode, therespective auxiliary timer (T2 or T4) stops inde-pendent of its run flag T2R or T4R.

Upon a trigger (selected transition) at the corre-sponding input pin TxIN the contents of the coretimer are loaded into the auxiliary timer registerand the associated interrupt request flag TxIR willbe set.

Note : The direction control bits DP3.7 (for T2IN)and DP3.5 (for T4IN) must be set to ’0’, and thelevel of the capture trigger signal should be heldhigh or low for at least 8 fCPU cycles before itchanges to ensure correct edge detection.

Figure 5-10. GPT1 Auxiliary Timer in Capture Mode

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8.1.3 Interrupt Control for GPT1 TimersWhen a timer overflows from FFFFh to 0000h(when counting up), or when it underflows from0000h to FFFFh (when counting down), its inter-rupt request flag (T2IR, T3IR or T4IR) in registerTxIC will be set. This will cause an interrupt to the

respective timer interrupt vector (T2INT, T3INT orT4INT) or trigger a PEC service, if the respectiveinterrupt enable bit (T2IE, T3IE or T4IE in registerTxIC) is set. There is an interrupt control registerfor each of the three timers.

T2IC (FF60h / B0h) SFR Reset Value: - - 00h



Note: Please refer to the general Interrupt Control Register description for an explanation of the control fields.

5 4 3 2 1 011 10 9 8 7 615 14 13 12

rw rw- - - - rw rw- - - -

T2IET2IR GLVLILVL

5 4 3 2 1 011 10 9 8 7 615 14 13 12

rw rw- - - - rw rw- - - -

T3IET3IR GLVLILVL

5 4 3 2 1 011 10 9 8 7 615 14 13 12

rw rw- - - - rw rw- - - -

T4IET4IR GLVLILVL

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8.2 TIMER BLOCK GPT2

From a programmer’s point of view, the GPT2block is represented by a set of SFRs as summa-rized below. Those portions of port and directionregisters which are used for alternate functions bythe GPT2 block are shaded.Timer block GPT2 supports high precision eventcontrol with a maximum resolution of 200 ns (@20 MHz CPU clock). It includes the two timers T5and T6, and the 16-bit capture/reload registerCAPREL. Timer T6 is referred to as the core timer,and T5 is referred to as the auxiliary timer ofGPT2.Each timer has an alternate input function pin as-sociated with it which serves as the gate control ingated timer mode, or as the count input in counter

mode. The count direction (Up / Down) may beprogrammed via software or may be dynamicallyaltered by a signal at an external control input pin.An overflow/underflow of T6 is indicated by theoutput toggle bit T6OTL whose state may be out-put on an alternate function port pin. In addition,T6 may be reloaded with the contents of CAPREL.

The toggle bit also supports the concatenation ofT6 with auxiliary timer T5. Triggered by an exter-nal signal, the contents of T5 can be captured intoregister CAPREL, and T5 may optionally becleared. Both timer T6 and T5 can count up ordown, and the current timer value can be read ormodified by the CPU in the non-bitaddressableSFRs T5 and T6.

Figure 5-11. SFRs and Port Pins Associated with Timer Block GPT2

ODP3 Port 3 Open Drain Control RegisterDP3 Port 3 Direction Control RegisterP3 Port 3 Data RegisterP5 Port 5 Data RegisterT5CON GPT2 Timer 5 Control RegisterT6CON GPT2 Timer 6 Control Register

T5IN/P5.13 T5EUD/P5.11T6IN/P5.12 T6EUD/P5.10CAPIN/P3.2 T6OUT/P3.1

T5CON

Control Registers

T5 GPT2 Timer 5 RegisterT6 GPT2 Timer 6 RegisterCAPREL GPT2 Capture/Reload RegisterT5IC GPT2 Timer 5 Interrupt Control RegisterT6IC GPT2 Timer 6 Interrupt Control RegisterCRIC GPT2 CAPREL Interrupt Control Register


Data Registers Control Registers Interrupt Control

T5 T5IC

DP3

P3

T6

CAPREL

T6IC

CRIC

T6CON

P5

ODP3

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Figure 5-12. GPT2 Block Diagram

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8.2.1 GPT2 Core Timer T6

The operation of the core timer T6 is controlled byits bitaddressable control register T6CON.

Timer 6 Run Bit

The timer can be started or stopped by softwarethrough bit T6R (Timer T6 Run Bit). If T6R=‘0’, thetimer stops. Setting T6R to ‘1’ will start the timer.In gated timer mode, the timer will only run ifT6R=‘1’ and the gate is active (high or low, as pro-grammed).


*) For the effects of bits T6UD and T6UDE refer to the direction table below.

Bit Function



T6M


0 0 0 :Timer Mode0 0 1 :Counter Mode0 1 0 :Gated Timer with Gate active low0 1 1 :Gated Timer with Gate active high1 X X :Reserved. Do not use this combination.

T6RTimer 6 Run Bit

T6R = ‘0’:Timer / Counter 6 stopsT6R = ‘1’:Timer / Counter 6 runs



T6OEAlternate Output Function Enable

T6OE = ‘0’:Alternate Output Function DisabledT6OE = ‘1’:Alternate Output Function Enabled

T6OTLTimer 6 Output Toggle Latch

Toggles on each overflow / underflow of T6. Can be set or reset by software.

T6SRTimer 6 Reload Mode Enable

T6SR = ‘0’:Reload from register CAPREL DisabledT6SR = ‘1’:Reload from register CAPREL Enabled

5 4 3 2 1 011 10 9 8 7 615 14 13 12

rw rwrw rw rw rw rwrw - - -

T6RT6UDT6OE----T6SRT6

OTLT6

UDE T6IT6M

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Count Direction ControlThe count direction of the core timer can be con-trolled either by software or by the external inputpin T6EUD (Timer T6 External Up/Down ControlInput), which is the alternate input function of portpin P5.10. These options are selected by bitsT6UD and T6UDE in control register T6CON.When the up/down control is done by software (bitT6UDE=‘0’), the count direction can be altered bysetting or clearing bit T6UD. When T6UDE=‘1’, pinT6EUD is selected to be the controlling source ofthe count direction. However, bit T6UD can still beused to reverse the actual count direction, asshown in the table below. If T6UD=‘0’ and pinT6EUD shows a low level, the timer is countingup. With a high level at T6EUD the timer is count-ing down. If T6UD=‘1’, a high level at pin T6EUDspecifies counting up, and a low level specifiescounting down. The count direction can bechanged regardless of whether the timer is run-ning or not.

Timer 6 Output Toggle Latch

An overflow or underflow of timer T6 will clock thetoggle bit T6OTL in control register T6CON.T6OTL can also be set or reset by software. BitT6OE (Alternate Output Function Enable) in regis-ter T6CON enables the state of T6OTL to be an al-ternate function of the external output pinT6OUT/P3.1. For that purpose, a ‘1’ must be writ-ten into port data latch P3.1 and pin T6OUT/P3.1must be configured as output by setting directioncontrol bit DP3.1 to ‘1’. If T6OE=‘1’, pin T6OUTthen outputs the state of T6OTL. If T6OE=‘0’, pinT6OUT can be used as general purpose IO pin.

In addition, T6OTL can be used in conjunctionwith the timer over/underflows as an input for thecounter function of the auxiliary timer T5. For thispurpose, the state of T6OTL does not have to beavailable at pin T6OUT, because an internal con-nection is provided for this option.

GPT2 Core Timer T6 Count Direction Control

Note: The direction control works the same for core timer T6 and for auxiliary timer T5. Therefore the pins and bits arenamed Tx...

Pin TxEUD Bit TxUDE Bit TxUD Count Direction

X 0 0 Count Up

X 0 1 Count Down

0 1 0 Count Up

1 1 0 Count Down

0 1 1 Count Down

1 1 1 Count Up

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TIMER BLOCK GPT1 (Cont’d)Timer 6 in Timer ModeTimer mode for the core timer T6 is selected bysetting bit field T6M in register T6CON to ‘000b’. Inthis mode, T6 is clocked with the internal systemclock divided by a programmable prescaler, whichis selected by bit field T6I. The input frequencyfT6for timer T6 and its resolution rT6 are scaled linear-ly with lower clock frequencies fCPU, as can beseen from the following formula:The timer input frequencies, resolution and peri-ods which result from the selected prescaler op-

tion when using a 20 MHz CPU clock are listed inthe table below. This table also applies to the Gat-ed Timer Mode of T6 and to the auxiliary timer T5in timer and gated timer mode. Note that somenumbers may be rounded to 3 significant digits.

Figure 5-13. Block Diagram of Core Timer T6 in Timer Mode

GPT2 Timer Input Frequencies, Resolution and Periods

fT6 =fCPU

4 * 2<T6I>rT6 [µs] =

fCPU [MHz]

4 * 2<T6I>

T6EUD = P5.10T6OUT = P3.1

x = 6

fCPU = 20MHz Timer Input Selection T5I / T6I

000b 001b 010b 011b 100b 101b 110b 111b

Prescaler factor 4 8 16 32 64 128 256 512

Input Frequency5MHz

2.5MHz

1.25MHz

625kHz

312.5kHz

156.25kHz

78.125kHz

39.06kHz

Resolution 200ns 400 ns 800 ns 1.6 µs 3.2 µs 6.4 µs 12.8 µs 25.6 µs

Period 13 ms 26 ms 52.5 ms 105 ms 210 ms 420 ms 840 ms 1.68 s

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TIMER BLOCK GPT1 (Cont’d)Timer 6 in Gated Timer ModeGated timer mode for the core timer T6 is selectedby setting bit field T6M in register T6CON to ‘010b’or ‘011b’. Bit T6M.0 (T6CON.3) selects the activelevel of the gate input. In gated timer mode thesame options for the input frequency as for thetimer mode are available. However, the inputclock to the timer in this mode is gated by the ex-ternal input pin T6IN (Timer T6 External Input),which is an alternate function of P5.12.

If T6M.0=‘0’, the timer is enabled when T6INshows a low level. A high level at this pin stops thetimer. If T6M.0=‘1’, pin T6IN must have a high lev-el in order to enable the timer. In addition, the tim-er can be turned on or off by software using bitT6R. The timer will only run, if T6R=‘1’ and thegate is active. It will stop, if either T6R=‘0’ or thegate is inactive.Note : A transition of the gate signal at pin T6INdoes not cause an interrupt request.

Figure 5-14 . Block Diagram of Core Timer T6 in Gated Timer Mode

T6IN = P5.12T6EUD = P5.10T6OUT = P3.1

x = 6

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Timer 6 in Counter Mode

Counter mode for the core timer T6 is selected bysetting bit field T6M in register T6CON to ‘001b’. Incounter mode timer T6 is clocked by a transition atthe external input pin T6IN, which is an alternatefunction of P5.12. The event causing an incrementor decrement of the timer can be a positive, a neg-ative, or both a positive and a negative transition

at this pin. Bit field T6I in control register T6CONselects the triggering transition (see table below).

The maximum input frequency which is allowed incounter mode is fCPU/4 (2.5 MHz @ fCPU=20 MHz).To ensure that a transition of the count input signalwhich is applied to T6IN is correctly recognized, itslevel should be held high or low for at least 4 fCPUcycles before it changes.

Figure 5-15. Block Diagram of Core Timer T6 in Counter Mode

GPT2 Core Timer T6 (Counter Mode) Input Edge Selection

T6IN = P5.12T6EUD = P5.10T6OUT = P3.1

x = 6


0 0 0 None. Counter T6 is disabled




1 X X Reserved. Do not use this combination

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8.2.2 GPT2 Auxiliary Timer T5

The auxiliary timer T5 can be configured for timer,gated timer, or counter mode with the same op-tions for the timer frequencies and the count signalas the core timer T6. In addition to these 3 count-ing modes, the auxiliary timer can be concatenat-ed with the core timer.

Note : The auxiliary timer has no output togglelatch and no alternate output function.The individual configuration for timer T5 is deter-mined by its bitaddressable control registerT5CON. Note that functions which are present inboth timers of block GPT2 are controlled in thesame bit positions and in the same manner ineach of the specific control registers.


*) For the effects of bits TxUD and TxUDE refer to the direction table (see T6 section).

Bit Function



T5M


0 0 : Timer Mode0 1 : Counter Mode1 0 : Gated Timer with Gate active low1 1 : Gated Timer with Gate active high

T5RTimer 5 Run Bit

T5R = ‘0’: Timer / Counter 5 stopsT5R = ‘1’: Timer / Counter 5 runs



CI

Register CAPREL Input Selection

0 0 : Capture disabled0 1 : Positive transition (rising edge) on CAPIN1 0 : Negative transition (falling edge) on CAPIN1 1 : Any transition (rising or falling edge) on CAPIN

T5CLRTimer 5 Clear Bit

T5CLR = ‘0’: Timer 5 not cleared on a captureT5CLR = ‘1’: Timer 5 is cleared on a capture

T5SCTimer 5 Capture Mode Enable

T5SC = ‘0’: Capture into register CAPREL DisabledT5SC = ‘1’: Capture into register CAPREL Enabled

5 4 3 2 1 011 10 9 8 7 615 14 13 12

- rw rw- - - rw rw rwrw rw rw

T5I-T5RT5UD-T5

UDE T5MT5

CLR CI - -T5SC

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TIMER BLOCK GPT1 (Cont’d)Count Direction Control for Auxiliary TimerThe count direction of the auxiliary timer can becontrolled in the same way as for the core timerT6. The description and the table apply according-ly.Timer T5 in Timer Mode or Gated Timer ModeWhen the auxiliary timer T5 is programmed to tim-er mode or gated timer mode, its operation is thesame as described for the core timer T6. The de-scriptions, figures and tables apply accordinglywith one exception:

• There is no output toggle latch and no alternateoutput pin for T5.

Timer T5 in Counter Mode

Counter mode for the auxiliary timer T5 is selectedby setting bit field T5M in register T5CON to‘001b’. In counter mode timer T5 can be clockedeither by a transition at the external input pin T5IN,or by a transition of timer T6’s output toggle latchT6OTL.

Figure 5-16. Block Diagram of Auxiliary Timer T5 in Counter Mode

The event causing an increment or decrement ofthe timer can be a positive, a negative, or both apositive and a negative transition at either the in-put pin, or at the toggle latch T6OTL.Bit field T5I in control register T5CON selects thetriggering transition (see table below).Note: Only state transitions of T6OTL which arecaused by the overflows/underflows of T6 will trig-ger the counter function of T5. Modifications of

T6OTL via software will NOT trigger the counterfunction of T5.

The maximum input frequency which is allowed incounter mode is fCPU/4 (2.5 MHz @ fCPU=20 MHz).To ensure that a transition of the count input signalwhich is applied to T5IN is correctly recognized, itslevel should be held high or low for at least 4 fCPUcycles before it changes.

x = 5

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Timer ConcatenationUsing the toggle bit T6OTL as a clock source forthe auxiliary timer in counter mode concatenatesthe core timer T6 with the auxiliary timer. Depend-ing on which transition of T6OTL is selected toclock the auxiliary timer, this concatenation formsa 32-bit or a 33-bit timer / counter.• 32-bit Timer/Counter: If both a positive and anegative transition of T6OTL is used to clock the

auxiliary timer, this timer is clocked on every over-flow/underflow of the core timer T6. Thus, the twotimers form a 32-bit timer.

• 33-bit Timer/Counter: If either a positive or anegative transition of T6OTL is selected to clockthe auxiliary timer, this timer is clocked on everysecond overflow/underflow of the core timer T6.This configuration forms a 33-bit timer (16-bit coretimer+T6OTL+16-bit auxiliary timer).

GPT2 Auxiliary Timer (Counter Mode) Input Edge Selection

The count directions of the two concatenated tim-ers are not required to be the same. This offers awide variety of different configurations.

T6 can operate in timer, gated timer or countermode in this case.

Figure 5-17. Concatenation of Core Timer T6 and Auxiliary Timer T5


X 0 0 None. Counter T5 is disabled




1 0 1 Positive transition (rising edge) of output toggle latch T6OTL

1 1 0 Negative transition (falling edge) of output toggle latch T6OTL

1 1 1 Any transition (rising or falling edge) of output toggle latch T6OTL


T6OUT = P3.1 x =5 y = 6

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TIMER BLOCK GPT1 (Cont’d)GPT2 Capture/Reload Register CAPREL inCapture Mode

This 16-bit register can be used as a capture reg-ister for the auxiliary timer T5. This mode is select-ed by setting bit T5SC=‘1’ in control registerT5CON. The source for a capture trigger is the ex-ternal input pin CAPIN, which is an alternate inputfunction of port pin P3.2. Either a positive, a nega-tive, or both a positive and a negative transition atthis pin can be selected to trigger the capture func-tion. The active edge is controlled by bit field CI inregister T5CON. The same coding is used as inthe two least significant bits of bit field T5I (see ta-ble in counter mode section).

The maximum input frequency for the capture trig-ger signal at CAPIN is fCPU/4 (2.5 MHz @ fCPU=20MHz). To ensure that a transition of the capturetrigger signal is correctly recognized, its level

should be held for at least 4 fCPU cycles before itchanges.When a selected transition at the external inputpin CAPIN is detected, the contents of the auxilia-ry timer T5 are latched into register CAPREL, andinterrupt request flag CRIR is set. With the sameevent, timer T5 can be cleared to 0000H. This op-tion is controlled by bit T5CLR in register T5CON.If T5CLR=‘0’, the contents of timer T5 are not af-fected by a capture. If T5CLR=‘1’, timer T5 iscleared after the current timer value has beenlatched into register CAPREL.Bit T5SC only controls whether a capture is per-formed or not. If T5SC=‘0’, the input pin CAPINcan still be used to clear timer T5 or as an externalinterrupt input. This interrupt is controlled by theCAPREL interrupt control register CRIC.

Figure 5-18. GPT2 Register CAPREL in Capture Mode

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TIMER BLOCK GPT1 (Cont’d)GPT2 Capture/Reload Register CAPREL in Re-load Mode

This 16-bit register can be used as a reload regis-ter for the core timer T6. This mode is selected bysetting bit T6SR=‘1’ in register T6CON. The eventcausing a reload in this mode is an overflow or un-derflow of the core timer T6.

When timer T6 overflows from FFFFh to 0000h(when counting up) or when it underflows from0000h to FFFFh (when counting down), the valuestored in register CAPREL is loaded into timer T6.This will not set the interrupt request flag CRIR as-sociated with the CAPREL register. However, in-terrupt request flag T6IR will be set indicating theoverflow/underflow of T6.

Figure 5-19. GPT2 Register CAPREL in Reload Mode

VR02045H

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GPT2 Capture/Reload Register CAPREL inCapture-And-Reload Mode

Since the reload function and the capture functionof register CAPREL can be enabled individually bybits T5SC and T6SR, the two functions can be en-abled simultaneously by setting both bits. Thisfeature can be used to generate an output fre-quency that is a multiple of the input frequency.

This combined mode can be used to detect con-secutive external events which may occur aperi-odically, but where a finer resolution, that means,more ’ticks’ within the time between two externalevents is required.

For this purpose, the time between the externalevents is measured using timer T5 and theCAPREL register. Timer T5 runs in timer modecounting up with a frequency of eg. fCPU/32. Theexternal events are applied to pin CAPIN. Whenan external event occurs, the timer T5 contents

are latched into register CAPREL, and timer T5 iscleared (T5CLR=‘1’). Thus, register CAPREL al-ways contains the correct time between twoevents, measured in timer T5 increments. TimerT6, which runs in timer mode counting down with afrequency of eg. fCPU/4, uses the value in registerCAPREL to perform a reload on underflow. Thismeans, the value in register CAPREL representsthe time between two underflows of timer T6, nowmeasured in timer T6 increments. Since timer T6runs 8 times faster than timer T5, it will underflow8 times within the time between two externalevents. Thus, the underflow signal of timer T6generates 8 ’ticks’. Upon each underflow, the in-terrupt request flag T6IR will be set and bit T6OTLwill be toggled. The state of T6OTL may be outputon pin T6OUT. This signal has 8 times more tran-sitions than the signal which is applied to pin CAP-IN.

Figure 5-20. GPT2 Register CAPREL in Capture-And-Reload Mode

VR02045G

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8.2.3 Interrupt Control for GPT2 Timers andCAPRELWhen a timer overflows from FFFFh to 0000h(when counting up), or when it underflows from0000h to FFFFh (when counting down), its inter-rupt request flag (T5IR or T6IR) in register TxICwill be set. Whenever a transition according to theselection in bit field CI is detected at pin CAPIN,

interrupt request flag CRIR in register CRIC is set.Setting any request flag will cause an interrupt tothe respective timer or CAPREL interrupt vector(T5INT, T6INT or CRINT) or trigger a PEC serv-ice, if the respective interrupt enable bit (T5IE orT6IE in register TxIC, CRIE in register CRIC) isset. There is an interrupt control register for eachof the two timers and for the CAPREL register.



CRIC (FF6Ah / B5h) SFR Reset Value: - - 00h


5 4 3 2 1 011 10 9 8 7 615 14 13 12

rw rw- - - - rw rw- - - -

T5IET5IR GLVLILVL

5 4 3 2 1 011 10 9 8 7 615 14 13 12

rw rw- - - - rw rw- - - -

T6IET6IR GLVLILVL

5 4 3 2 1 011 10 9 8 7 615 14 13 12

rw rw- - - - rw rw- - - -

CRIECRIR GLVLILVL

158

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ST10R163User Manual

9 - ASYNCHRONOUS/SYNCHRONOUS SERIAL INTERFACE

The Asynchronous/Synchronous Serial InterfaceASC0 provides serial communication between theST10R163 and other microcontrollers, microproc-essors or external peripherals.

The ASC0 supports full-duplex asynchronouscommunication up to 625 KBaud and half-duplexsynchronous communication up to 2.5 MBaud (@20 MHz CPU clock). In synchronous mode, dataare transmitted or received synchronous to a shiftclock which is generated by the ST10R163. Inasynchronous mode, 8- or 9-bit data transfer, pari-ty generation, and the number of stop bits can beselected. Parity, framing, and overrun error detec-tion is provided to increase the reliability of datatransfers. Transmission and reception of data isdouble-buffered. For multiprocessor communica-tion, a mechanism to distinguish address fromdata bytes is included. Testing is supported by aloop-back option. A 13-bit baud rate generatorprovides the ASC0 with a separate serial clocksignal.

The operating mode of the serial channel ASC0 iscontrolled by its bitaddressable control registerS0CON. This register contains control bits formode and error check selection, and status flagsfor error identification.

A transmission is started by writing to the (write-only) Transmit Buffer register S0TBUF (via an in-struction or a PEC data transfer). Only the numberof data bits which is determined by the selectedoperating mode will actually be transmitted, ie. bitswritten to positions 9 through 15 of registerS0TBUF are always insignificant. After a transmis-sion has been completed, the transmit buffer reg-ister is cleared to 0000h.Data transmission is double-buffered, so a newcharacter may be written to the transmit bufferregister, before the transmission of the previous

character is complete. This allows to send charac-ters back-to-back without gaps.

Data reception is enabled by the Receiver EnableBit S0REN. After reception of a character hasbeen completed, the received data and, if provid-ed by the selected operating mode, the receivedparity bit can be read from the (read-only) ReceiveBuffer register S0RBUF. Bits in the upper half ofS0RBUF which are not valid in the selected oper-ating mode will be read as zeros.Data reception is double-buffered, so that recep-tion of a second character may already begin be-fore the previously received character has beenread out of the receive buffer register. In allmodes, receive buffer overrun error detection canbe selected through bit S0OEN. When enabled,the overrun error status flag S0OE and the errorinterrupt request flag S0EIR will be set when thereceive buffer register has not been read by thetime reception of a second character is complete.The previously received character in the receivebuffer is overwritten.

The Loop-Back option (selected by bit S0LB) al-lows to simultaneously receive the data currentlybeing transmitted. This may be used to test serialcommunication routines at an early stage withouthaving to provide an external network. In loop-back mode the alternate input/output functions ofthe Port 3 pins are not necessary.

Note : Serial data transmission or reception is onlypossible when the Baud Rate Generator Run BitS0R is set to ‘1’. Otherwise the serial interface isidle.Do not program the mode control field S0M in reg-ister S0CON to one of the reserved combinationsto avoid unpredictable behaviour of the serial in-terface.

S0CON (FFB0h / D8h) SFR Reset Value: 0000h

S0FE

5 4 3 2 1 011 10 9 8 7 615 14 13 12

rw rw rw rwrw rw rwrw rw rw rw

-S0LBS0R S0PES0

STPS0

RENS0

PENS0

FENS0

OEN

rw rw

S0OES0

ODDS0

BRS S0M

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9 - ASYNCHRONOUS/SYNCHRONOUS SERIAL INTERFACE (ST10R163)

Table 1. SFRs and Port Pins associated with ASC0

Bit Function

S0M

ASC0 Mode Control

0 0 0 : 8-bit data synchronous operation0 0 1 : 8-bit data async. operation0 1 0 : Reserved. Do not use this combination!0 1 1 : 7-bit data + parity async. operation1 0 0 : 9-bit data async. operation1 0 1 : 8-bit data + wake up bit async. operation1 1 0 : Reserved. Do not use this combination!1 1 1 : 8-bit data + parity async. operation

S0STPNumber of Stop Bits Selection async. operation

0 : One stop bit1 : Two stop bits

S0REN

Receiver Enable Bit

0 : Receiver disabled1 : Receiver enabled

(Reset by hardware after reception of byte in synchronous mode)

S0PENParity Check Enable Bit async. operation

0 : Ignore parity1 : Check parity

S0FENFraming Check Enable Bit async. operation

0 : Ignore framing errors1 : Check framing errors

S0OENOverrun Check Enable Bit

0 : Ignore overrun errors1 : Check overrun errors

S0PEParity Error Flag

Set by hardware on a parity error (S0PEN=’1’). Must be reset by software.

S0FEFraming Error Flag

Set by hardware on a framing error (S0FEN=’1’). Must be reset by software.

S0OEOverrun Error Flag

Set by hardware on an overrun error (S0OEN=’1’). Must be reset by software.

S0ODDParity Selection Bit

0 : Even parity (parity bit set on odd number of ‘1’s in data)1 : Odd parity (parity bit set on even number of ‘1’s in data)

S0BRSBaudrate Selection Bit

0 : Divide clock by reload-value + constant (depending on mode)1 : Additionally reduce serial clock to 2/3rd

S0LBLoopBack Mode Enable Bit

0 : Standard transmit/receive mode1 : Loopback mode enabled

S0RBaudrate Generator Run Bit

0 : Baudrate generator disabled (ASC0 inactive)1 : Baudrate generator enabled

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9.1 ASYNCHRONOUS OPERATION

Asynchronous mode supports full-duplex commu-nication, where both transmitter and receiver usethe same data frame format and the same baud

rate. Data is transmitted on pin TXD0/P3.10 andreceived on pin RXD0/P3.11. These signals arealternate functions of Port 3 pins.

Figure 6-1. Asynchronous Mode of Serial Channel ASC0

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ASYNCHRONOUS OPERATION (Cont’d)

Asynchronous Data Frames

8-bit data frames either consist of 8 data bitsD7...D0 (S0M=’001b’), or of 7 data bits D6...D0plus an automatically generated parity bit(S0M=’011b’). Parity may be odd or even, de-pending on bit S0ODD in register S0CON. Aneven parity bit will be set, if the modulo-2-sum ofthe 7 data bits is ‘1’. An odd parity bit will becleared in this case. Parity checking is enabled viabit S0PEN (always OFF in 8-bit data mode). Theparity error flag S0PE will be set along with the er-ror interrupt request flag, if a wrong parity bit is re-ceived. The parity bit itself will be stored in bitS0RBUF.7.

9-bit data frames either consist of 9 data bitsD8...D0 (S0M=’100b’), of 8 data bits D7...D0 plusan automatically generated parity bit(S0M=’111b’) or of 8 data bits D7...D0 plus wake-up bit (S0M=’101b’). Parity may be odd or even,depending on bit S0ODD in register S0CON. Aneven parity bit will be set, if the modulo-2-sum ofthe 8 data bits is ‘1’. An odd parity bit will becleared in this case. Parity checking is enabled viabit S0PEN (always OFF in 9-bit data and wake-upmode). The parity error flag S0PE will be set alongwith the error interrupt request flag, if a wrong par-

ity bit is received. The parity bit itself will be storedin bit S0RBUF.8.

In wake-up mode received frames are only trans-ferred to the receive buffer register, if the 9th bit(the wake-up bit) is ‘1’. If this bit is ‘0’, no receiveinterrupt request will be activated and no data willbe transferred.

This feature may be used to control communica-tion in multi-processor system:When the master processor wants to transmit ablock of data to one of several slaves, it first sendsout an address byte which identifies the targetslave. An address byte differs from a data byte inthat the additional 9th bit is a ’1’ for an addressbyte and a ’0’ for a data byte, so no slave will be in-terrupted by a data ’byte’. An address ’byte’ will in-terrupt all slaves (operating in 8-bit data + wake-up bit mode), so each slave can examine the 8LSBs of the received character (the address). Theaddressed slave will switch to 9-bit data mode (eg.by clearing bit S0M.0), which enables it to also re-ceive the data bytes that will be coming (havingthe wake-up bit cleared). The slaves that were notbeing addressed remain in 8-bit data + wake-upbit mode, ignoring the following data bytes.

Figure 6-2. Asynchronous 8-bit Data Frames

Figure 6-3. Asynchronous 9-bit Data Frames

2ndStopBit

StartBit

D0(LSB)

D1 D2 D3 D4 D5 D6 D7 /Parity

(1st)StopBit

2ndStopBit

StartBit

D0(LSB)

D1 D2 D3 D4 D5 D6 9thBit

(1st)StopBit

D7

• Data Bit D8• Parity• Wake-up Bit

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ASYNCHRONOUS OPERATION (Cont’d)Asynchronous transmission begins at the nextoverflow of the divide-by-16 counter (see figureabove), provided that S0R is set and data hasbeen loaded into S0TBUF. The transmitted dataframe consists of three basic elements:– the start bit– the data field (8 or 9 bits, LSB first, including a

parity bit, if selected)– the delimiter (1 or 2 stop bits)Data transmission is double buffered. When thetransmitter is idle, the transmit data loaded intoS0TBUF is immediately moved to the transmitshift register thus freeing S0TBUF for the nextdata to be sent. This is indicated by the transmitbuffer interrupt request flag S0TBIR being set.S0TBUF may now be loaded with the next data,while transmission of the previous one is still goingon.The transmit interrupt request flag S0TIR will beset before the last bit of a frame is transmitted, ie.before the first or the second stop bit is shifted outof the transmit shift register.The transmitter output pin TXD0/P3.10 must beconfigured for alternate data output, ie. P3.10=’1’and DP3.10=’1’.Asynchronous reception is initiated by a fallingedge (1-to-0 transition) on pin RXD0, providedthat bits S0R and S0REN are set. The receivedata input pin RXD0 is sampled at 16 times therate of the selected baud rate. A majority decisionof the 7th, 8th and 9th sample determines the ef-

fective bit value. This avoids erroneous resultsthat may be caused by noise.

If the detected value is not a ’0’ when the start bit issampled, the receive circuit is reset and waits forthe next 1-to-0 transition at pin RXD0. If the startbit proves valid, the receive circuit continues sam-pling and shifts the incoming data frame into thereceive shift register.

When the last stop bit has been received, the con-tent of the receive shift register is transferred tothe receive data buffer register S0RBUF. Simulta-neously, the receive interrupt request flag S0RIRis set after the 9th sample in the last stop bit timeslot (as programmed), regardless whether validstop bits have been received or not. The receivecircuit then waits for the next start bit (1-to-0 tran-sition) at the receive data input pin.

The receiver input pin RXD0/P3.11 must be con-figured for input, ie. DP3.11=’0’.

Asynchronous reception is stopped by clearing bitS0REN. A currently received frame is completedincluding the generation of the receive interrupt re-quest and an error interrupt request, if appropri-ate. Start bits that follow this frame will not be rec-ognized.

Note : In wake-up mode received frames are onlytransferred to the receive buffer register, if the 9thbit (the wake-up bit) is ‘1’. If this bit is ‘0’, no re-ceive interrupt request will be activated and nodata will be transferred.

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9.2 SYNCHRONOUS OPERATION

Synchronous mode supports half-duplex commu-nication, basically for simple IO expansion via shiftregisters. Data is transmitted and received via pinRXD0/P3.11, while pin TXD0/P3.10 outputs theshift clock. These signals are alternate functions

of Port 3 pins. Synchronous mode is selected withS0M=’000b’.8 data bits are transmitted or received synchro-nous to a shift clock generated by the internalbaud rate generator. The shift clock is only activeas long as data bits are transmitted or received.

Figure 6-4. Synchronous Mode of Serial Channel ASC0

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SYNCHRONOUS OPERATION (Cont’d)Synchronous transmission begins within 4 statetimes after data has been loaded into S0TBUF,provided that S0R is set and S0REN=’0’ (half-du-plex, no reception). Data transmission is doublebuffered. When the transmitter is idle, the transmitdata loaded into S0TBUF is immediately moved tothe transmit shift register thus freeing S0TBUF forthe next data to be sent. This is indicated by thetransmit buffer interrupt request flag S0TBIR be-ing set. S0TBUF may now be loaded with the nextdata, while transmission of the previous one is stillgoing on. The data bits are transmitted synchro-nous with the shift clock. After the bit time for the8th data bit, both pins TXD0 and RXD0 will gohigh, the transmit interrupt request flag S0TIR isset, and serial data transmission stops.Pin TXD0/P3.10 must be configured for alternatedata output, ie. P3.10=’1’ and DP3.10=’1’, in orderto provide the shift clock. Pin RXD0/P3.11 mustalso be configured for output (P3.11=’1’ andDP3.11=’1’) during transmission.Synchronous reception is initiated by setting bitS0REN=’1’. If bit S0R=1, the data applied at pinRXD0 are clocked into the receive shift registersynchronous to the clock which is output at pinTXD0. After the 8th bit has been shifted in, thecontent of the receive shift register is transferredto the receive data buffer S0RBUF, the receive in-terrupt request flag S0RIR is set, the receiver en-able bit S0REN is reset, and serial data receptionstops.Pin TXD0/P3.10 must be configured for alternatedata output, ie. P3.10=’1’ and DP3.10=’1’, in orderto provide the shift clock. Pin RXD0/P3.11 must beconfigured as alternate data input (DP3.11=’0’).Synchronous reception is stopped by clearing bitS0REN. A currently received byte is completed in-cluding the generation of the receive interrupt re-quest and an error interrupt request, if appropri-ate. Writing to the transmit buffer register while areception is in progress has no effect on receptionand will not start a transmission.

If a previously received byte has not been read outof the receive buffer register at the time the recep-tion of the next byte is complete, both the error in-terrupt request flag S0EIR and the overrun errorstatus flag S0OE will be set, provided the overruncheck has been enabled by bit S0OEN.

9.3 HARDWARE ERROR DETECTIONCAPABILITIES

To improve the safety of serial data exchange, theserial channel ASC0 provides an error interrupt re-quest flag, which indicates the presence of an er-ror, and three (selectable) error status flags in reg-ister S0CON, which indicate which error has beendetected during reception. Upon completion of areception, the error interrupt request flag S0EIRwill be set simultaneously with the receive inter-rupt request flag S0RIR, if one or more of the fol-lowing conditions are met:

• If the framing error detection enable bit S0FENis set and any of the expected stop bits is nothigh, the framing error flag S0FE is set, indicat-ing that the error interrupt request is due to aframing error (Asynchronous mode only).

• If the parity error detection enable bit S0PEN isset in the modes where a parity bit is received,and the parity check on the received data bitsproves false, the parity error flag S0PE is set,indicating that the error interrupt request is dueto a parity error (Asynchronous mode only).

• If the overrun error detection enable bit S0OENis set and the last character received was notread out of the receive buffer by software orPEC transfer at the time the reception of a newframe is complete, the overrun error flag S0OEis set indicating that the error interrupt requestis due to an overrun error (Asynchronous andsynchronous mode).

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9.4 ASC0 BAUD RATE GENERATION

The serial channel ASC0 has its own dedicated13-bit baud rate generator with 13-bit reload capa-bility, allowing baud rate generation independentfrom the timers.

The baud rate generator is clocked with the CPUclock divided by 2 (10 MHz @ 20 MHz CPU clock).The timer is counting downwards and can be start-ed or stopped through the Baud Rate GeneratorRun Bit S0R in register S0CON. Each underflowof the timer provides one clock pulse to the serialchannel. The timer is reloaded with the valuestored in its 13-bit reload register each time it un-derflows. The resulting clock is again divided ac-cording to the operating mode and controlled bythe Baudrate Selection Bit S0BRS. If S0BRS=’1’,the clock signal is additionally divided to 2/3rd ofits frequency (see formulas and table). So thebaud rate of ASC0 is determined by the CPUclock, the reload value, the value of S0BRS andthe operating mode (asynchronous or synchro-nous).

Register S0BG is the dual-function Baud RateGenerator/Reload register. Reading S0BG returnsthe content of the timer (bits 15...13 return zero),while writing to S0BG always updates the reloadregister (bits 15...13 are insiginificant).

An auto-reload of the timer with the content of thereload register is performed each time S0BG iswritten to. However, if S0R=’0’ at the time the writeoperation to S0BG is performed, the timer will not

be reloaded until the first instruction cycle afterS0R=’1’.

Asynchronous Mode Baud Rates

For asynchronous operation, the baud rate gener-ator provides a clock with 16 times the rate of theestablished baud rate. Every received bit is sam-pled at the 7th, 8th and 9th cycle of this clock. Thebaud rate for asynchronous operation of serialchannel ASC0 and the required reload value for agiven baudrate can be determined by the followingformulas:

<S0BRL> represents the content of the reloadregister, taken as unsigned 13-bit integer,<S0BRS> represents the value of bit S0BRS (ie.‘0’ or ‘1’), taken as integer.

The maximum baud rate that can be achieved forthe asynchronous modes when using a CPU clockof 20 MHz is 625 KBaud. The table below lists var-ious commonly used baud rates together with therequired reload values and the deviation errorscompared to the intended baudrate.

BAsync =fCPU

(32 + 16*<S0BRS>) * (<S0BRL> + 1)

S0BRL = (

fCPU

(32 + 16*<S0BRS>) * BAsync) - 1

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ASC0 BAUD RATE GENERATION (Cont’d)

Synchronous Mode Baud Rates

For synchronous operation, the baud rate genera-tor provides a clock with 4 times the rate of the es-tablished baud rate. The baud rate for synchro-nous operation of serial channel ASC0 can be de-termined by the following formula:

<S0BRL> represents the content of the reloadregister, taken as unsigned 13-bit integers,<S0BRS> represents the value of bit S0BRS (ie.‘0’ or ‘1’), taken as integer.

The maximum baud rate that can be achieved insynchronous mode when using a CPU clock of20 MHz is 2.5 MBaud.

Note: The deviation errors given in the table above are rounded.Using a baudrate crystal (resulting in a CPU clock of eg. 18.432 MHz) provides correct baudrates without deviationerrors.

BSync =

S0BRL = (fCPU

(8 + 4*<S0BRS>) * BSync) - 1

fCPU

(8 + 4*<S0BRS>) * (<S0BRL> + 1)

Baud RateS0BRS = ‘0’, f CPU = 20 MHz S0BRS = ‘1’, f CPU = 20 MHz

Deviation Error Reload Value Deviation Error Reload Value

625 KBaud ±0.0 % 0000h --- ---

19.2 KBaud +1.7 % / -1.4 % 001Fh / 0020h +3.3 % / -1.4 % 0014h / 0015h

9600 Baud +0.2 % / -1.4 % 0040h / 0041h +1.0 % / -1.4 % 002Ah / 002Bh

4800 Baud +0.2 % / -0.6 % 0081h / 0082h +1.0 % / -0.2 % 0055h / 0056h

2400 Baud +0.2 % / -0.2 % 0103h / 0104h +0.4 % / -0.2 % 00ACh / 00ADh

1200 Baud +0.2 % / -0.4 % 0207h / 0208h +0.1 % / -0.2 % 015Ah / 015Bh

600 Baud +0.1 % / -0.0 % 0410h / 0411h +0.1 % / -0.1 % 02B5h / 02B6h

75 Baud +1.7 % 1FFFh +0.0 % / -0.0 % 15B2h / 15B3h

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9.5 ASC0 INTERRUPT CONTROL

Four bit addressable interrupt control registers areprovided for serial channel ASC0. Register S0TICcontrols the transmit interrupt, S0TBIC controlsthe transmit buffer interrupt, S0RIC controls thereceive interrupt and S0EIC controls the error in-terrupt of serial channel ASC0. Each interruptsource also has its own dedicated interrupt vector.S0TINT is the transmit interrupt vector, S0TBINTis the transmit interrupt vector, S0RINT is the re-ceive interrupt vector, and S0EINT is the error in-terrupt vector.

The cause of an error interrupt request (framing,parity, overrun error) can be identified by the errorstatus flags in control register S0CON.

Note : In contrary to the error interrupt request flagS0EIR, the error status flags S0FE/S0PE/S0OEare not reset automatically upon entry into the er-ror interrupt service routine, but must be clearedby software.

S0TIC (FF6Ch / B6h) SFR Reset Value: - - 00h

S0RIC (FF6Eh / B7h) SFR Reset Value: - - 00h

S0EIC (FF70h / B8h) SFR Reset Value: - - 00h

S0TBIC (F19Ch / CEh) ESFR Reset Value: - - 00h


5 4 3 2 1 011 10 9 8 7 615 14 13 12

rw rw- - - - rw rw- - - -

S0TIES0TIR GLVLILVL

5 4 3 2 1 011 10 9 8 7 615 14 13 12

rw rw- - - - rw rw- - - -

S0RIES0RIR GLVLILVL

5 4 3 2 1 011 10 9 8 7 615 14 13 12

rw rw- - - - rw rw- - - -

S0EIES0EIR GLVLILVL

S0TBIR

S0TBIE

5 4 3 2 1 011 10 9 8 7 615 14 13 12

rw rw- - - - rw rw- - - -

GLVLILVL

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ASC0 INTERRUPT CONTROL (Cont’d)Using the ASC0 InterruptsFor normal operation (ie. besides the error inter-rupt) the ASC0 provides three interrupt requeststo control data exchange via this serial channel:– S0TBIR is activated when data is moved

from S0TBUF to the transmit shift register.– S0TIR is activated before the last bit of an

asynchronous frame is transmitted, or– after the last bit of a synchronous

frame has been transmitted.– S0RIR is activated when the received

frame is moved to S0RBUF.While the task of the receive interrupt handler isquite clear, the transmitter is serviced by two inter-rupt handlers. This provides advantages for theservicing software.For single transfers it is sufficient to use thetransmitter interrupt (S0TIR), which indicates thatthe previously loaded data has been transmitted,except for the last bit of an asynchronous frame.

For multiple back-to-back transfers it is neces-sary to load the following data at least until thetime the last bit of the previous frame is beingtransmitted. In asynchronous mode this leavesjust one bit-time for the handler to respond to thetransmitter interrupt request, in synchronousmode it is not possible at all.Using the transmit buffer interrupt (S0TBIR) to re-load transmit data allows the time to transmit acomplete frame for the service routine, asS0TBUF may be reloaded while the previous datais still being transmitted.

As shown in the figure below, S0TBIR is an earlytrigger for the reload routine, while S0TIR indi-cates the completed transmission. Software usinghandshake therefore should rely on S0TIR at theend of a data block to make sure that all data hasreally been transmitted.

Figure 6-5. ASC0 Interrupt Generation

Idle IdleSta

rt

Sta

rt

Sta

rt

Sto

p

Sto

p

Sto

p

S0TBIR S0TBIR S0TBIR

S0TIR S0TIR S0TIR

S0RIR S0RIR S0RIR

Idle Idle

S0TBIR S0TBIR S0TBIR

S0TIR S0TIR S0TIR

S0RIR S0RIR S0RIR

Asynchronous Mode

Synchronous Mode

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Notes :

170

February 1996 1/16


ST10R163User Manual

10 - SYNCHRONOUS SERIAL PORT

The Synchronous Serial Port SSP provides high-speed serial communication with external slavedevices such as EEPROM via a three-wire inter-face similar to the SPI protocol. The interface linesare:

SSPCLK Serial clock output. Driven by theST10R163 (master) to the peripheral(slave) which is selected for transfer.

SSPDAT Bi-directional serial data line. Data istransferred between the ST10R163and the peripheral at up to 10 MBit/s.

SSPCE0,1 Serial peripheral chip enable signals 0and 1. These signals select one of heslaves connected to the SSP fortransfer.

The SSP can be programmed to send command,address or data information to a peripheral device(write operation) or receive data from a peripheral(read operation). For a write operation, the SSPcan send up to three bytes (24 bits) to a peripher-al. For a read operation, the SSP can first send upto three bytes to a peripheral before receiving onebyte from the peripheral. In addition, a continuousmode is provided which allows to continuouslysend data to the selected peripheral or continu-ously receive data from the selected peripheral,without deselecting the peripheral between thesingle transfers. With this feature, reading for ex-ample EEPROM devices is simplified such that af-ter the initial command and address transfer fromthe master to the peripheral, data bytes can beread from the peripheral one after the other.

Figure 7-1. Synchronous Serial Port SSP Block Diagram

VR02079B

Chip

Enable

Control

SSP Control

Block

Status

X BUS

Transmit Buffers

Registers SSPTBxReceive Buffers

Registers SSPRB

ControlPin

XP1INT

Clock RateDivider Control

Clock

ClockShift

ClockCPU

Receive/TransmitInt. Request

SSPLCK

SSPCE0

SSPCE1

SSPDAT

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10 - SYNCHRONOUS SERIAL PORT (ST10R163)

XBUS ImplementationThe SSP is implemented as an on-chip X-Periph-eral connected onto the XBUS. From a user’spoint of view, this XBUS can be regarded as an in-ternal representation of the external bus in the 16-bit demultiplexed mode, allowing fastest possibleword and byte accesses by the CPU or the PEC tothe registers of the SSP. These registers reside ina special SSP address area of 256 bytes, which ismapped into segment 0 and uses addressesEF00h through EFFFh (10 bytes addresses used).

SSP Registers

The registers of the SSP are organized as five 16-bit registers, located on word addresses. Howev-er, all registers may be accessed bytewise in or-der to select special actions without effecting othermechanisms. The figure below shows all controland data registers of the SSP.

Figure 7-2. Synchronous Serial Port SSP Registers

XP1IC

SSPTB0 SSP Transmit Byte 0 RegisterSSPTB1 SSP Transmit Byte 1 RegisterSSPTB2 SSP Transmit Byte 2 RegisterSSPRB0 SSP Receive Byte 0 Register (same locationthan SSPTB0)

SSPCON0SSP Control Register 0SSPCON1SSP Control Register 1XP1IC SSP Interrupt Control Register

Data Registers(8-bit registers)

Control Registers Interrupt Control

SSPTB0 SSPCON0

SSPTB1

SSPTB2

SSPRB0 SSPCON1

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SSP Control Register 0 - SSPCON0

This register contains all bits which are required tosetup a read or write operation for the SSP.

SSPCCON0 (00’EF00h) Reset Value: 0000h

Bit Function

SSPCKS

SSP Clock Rate Selection Baud Rate @ 20 MHz CPU clock

000: SSP clock = CPU clock divided by 2 10 MBit/s.001: SSP clock = CPU clock divided by 4 5 MBit/s.010: SSP clock = CPU clock divided by 8 2.5 MBit/s.011: SSP clock = CPU clock divided by 16 1.25 MBit/s.100: SSP clock = CPU clock divided by 32 625 KBit/s.101: SSP clock = CPU clock divided by 64 312.5 KBit/s.110: SSP clock = CPU clock divided by 128 156.25 KBit/s.111: SSP clock = CPU clock divided by 256 78.125 KBit/s.

SSPSEL

SSP Chip Enable Selection

00:No chip enable line selected.01:Chip enable line 0 (SSPCE0) selected.10:Chip enable line 1 (SSPCE1) selected.11:Both chip enable lines selected. Can be used for broadcast messages. Improperuse for read operations may cause line conflicts among several selected slaves.

SSPCMSSP Continuous Mode Selection

0:Single Transfer Mode. Chip enable line deactivated after end of transfer.1:Continuous Mode. Chip enable line remains active between transfers.

SSPHBSSP Heading Control Bit

0:Transmit/Receive LSB First1:Transmit/Receive MSB First

SSPRWSSP Read/Write Control Bit

0:Write Operation selected.1:Read Operation selected.

SSPCKESSP Clock Edge Control Bit

0:Shift transmit data on the leading clock edge, latch on trailing edge.1:Latch receive data on leading clock edge, shift on trailing edge.

SSPCKPSSP Clock Polarity Control Bit

0:Idle clock is high, leading clock edge is high-to-low transition.1:Idle clock is low, leading clock edge is low-to-high transition.

SSPBSY

SSP Busy Flag

0:SSP is idle.1:SSP is busy.

The Busy flag is set with the first write into one of the transmit buffers. It is automatically clearedafter the last bit has been transferred and selected chip select line is switched inactive.

5 4 3 2 1 011 10 9 8 7 615 14 13 12

rw rw rwrw rw rw- - - -

-SSPCM

SSPHB

- rw

SSPCKP

SSPCKE

SSPRW SSPCKS-

SSPBSY - - SSPSEL-

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The Clock Control allows to adapt transmit andreceive behaviour of the SSP to a variety of serialinterfaces. A specific clock edge (rising or falling)is used to shift out transmit data, while the otherclock edge is used to latch in receive data. Bit

SSPKE selects the leading edge or the trailingedge for each function. Bit SSPKP selects the lev-el of the clock line in the idle state. So for an idle-high clock the leading edge is a falling one, a 1-to-0 transition. The figure below is a summary.

Figure 7-3. Serial Clock Phase and Polarity Options

Serial ClockSSPCLK

Data driven by CPU Data driven by slaveLatch DataShift Data

SSP

0 0

0 1

1 0

1 1

CKE

SSPDAT

SSPCKP

SSPCEx

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SSP Control Register 1 - SSPCON1

This register contains all bits which are required toconfigure the output lines of the SSP. It contains

control bits which are normally written once duringthe initialization of the system.

SSPCON1 (00’EF02h) Reset Value: 0000h

SSP Transmit Buffer Registers - SSPTBx

Three 8-bit transmit registers are provided with the SSP, organized as follows. Note that the same registeris used for the transmit buffer byte 0 and the receive buffer.

Reserved Byte (00’EF07h) Reset Value: xxh SSPTB2 (00’EF06h) Reset Value: xxh

SSPTB1 (00’EF05h) Reset Value: xxh SSPTB0 (00’EF04h) Reset Value: xxh

Bit Function (Operating Mode, SSCEN = ‘1’)

SSPCEP0SSP Chip Enable Line 0 (SSPCEN0) Polarity Control Bit

0:Inactive Chip Enable line is low, active level is high.1:Inactive Chip Enable line is high, active level is low.

SSPCEP1SSP Chip Enable Line 1 (SSPCEN1) Polarity Control Bit

0:Inactive Chip Enable line is low, active level is high.1:Inactive Chip Enable line is high, active level is low.

SSPCKOSSP Clock Line Output (SSPCLK) Control Bit

0:Clock output pin state is high-impedance.1:Clock output pin is configured to push/pull output.

SSPCEO0SSP Chip Enable Line 0 (SSPCEN0) Output Control Bit

0:Chip Enable 0 output pin state is high-impedance.1:Chip Enable 0 output pin is configured to push/pull output.

SSPCEO1SSP Chip Enable Line 1 (SSPCEN1) Output Control Bit

0:Chip Enable 1 output pin state is high-impedance.1:Chip Enable 1 output pin is configured to push/pull output.

5 4 3 2 1 011 10 9 8 7 615 14 13 12

- rw- -

- - -SSP

CEO1SSP

CEP0

- -- -

- - - -

- -- -

- - - -SSP

CEP1SSPCKO

SSPCEO0

rw rw rwrw

5 4 3 2 1 011 10 9 8 7 615 14 13 12

rw-

TRANSMIT BYTE 2reserved

5 4 3 2 1 011 10 9 8 7 615 14 13 12

rwrw

RECEIVE/TRANSMIT BYTE 0TRANSMIT BYTE 1

175

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InitializationAfter reset, all SSP I/O lines are in high-imped-ance state. The SSPDAT line is controlled auto-matically by the SSP, according to the performedread or write operation. The SSPCLK, SSPCE0and SSPCE1 lines, however, have individual out-put control bits. This allows the user to first pro-gram the desired polarity of these lines beforeswitching them to output. With this, it is possible topull the lines to the desired initial polarity alreadyduring and after rest until they are switched topush/pull outputs by connecting external pullup orpulldown resistors to pins.While the polarity of the chip enables lines is pro-grammed via register SSPCON1, the polarity ofthe clock line is controlled through a bit in registerSSPCON0. The reason for this is that the chip en-able polarity normally only needs to be selectedduring initialization, while the clock line polarityand active edge might be switched between trans-fers to different peripheral slaves. This can behandled by a write to only one control register,SSPCON0, together with other necessary selec-tions for the transfer.Starting a transferPrior to any transfer, all required selections for thistransfer should be made. This is performedthrough programming the control bits inSSPCON0 register to the desired values. TheSSPCKS0..2 bits determine the baudrate of thetransfer. With the SSPCKS1..0 bits, the appropri-ate chip enable line(s) is (are) selected. If a contin-uous transfer is desired, bit SSPCM must be set.The heading control bit SSPHB selects whethereach byte is transferred with LSB or MSB first. Thetype of operation, a read or write operation, is con-

trolled through bit SSPRW. If set, a read operationwill take place. In order to communicate with sev-eral peripherals with different clocking require-ments, the control bits SSPCKP and SSPCKE al-low to set the polarity and relevant shift/latch edg-es of the clock.

When the programming of the control registerSSPCON0 is complete, the transfer is started witha write to transmit buffer SSPTB0, regardless ofthe type of operation (read or write operation).

Performing a Write Operation

If the SPRW bit in register SSPCON0 is reset, awrite operation is selected. During a write opera-tion, information is only transferred from the CPU(master) to the slave peripheral. The transmit buff-ers SSPTB2...SSPTB0 are written by the CPUwith the information data to be transferred. Writingto SSPTB0 will start the transfer. The following fig-ure shows the basic waveforms for a write opera-tion of the SSP.

The length of the transfer is determined throughwhich transmit buffers were written to prior to thetransfer. Internal flags, ‘TBx_Full’, are used for thispurpose. These flags are set through a write to thecorresponding transmit buffer register. SSPTB0must be written in any case in order to start thetransfer. Writing only to SSPTB0 will perform an 8-bit transfer of the content of SSPTB0. When thelast bit is shifted out completely, the TB0_Full flagis reset. To start the next transfer, SSPTB0 mustbe written through software again, even if thesame information data as for previous transfershould be transferred.

Note : Content of SSPTBx registers are undefinedafter a write operation.

Figure 7-4. Write Operation Waveforms

SSPCLK

SSPCEx

SSPDAT Bit 23/15/7 Bit 22/14/6 Bit 1 Bit 0

0.5 BT 1 Bit Time 1 BT 0.5 BT 0.5 BT

176

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Figure 7-5. Write Operation controlled through Transmit Buffer Full Signals

While SSPTB0 must be the last transmit bufferregister written, there is no special sequence re-quired for writing to the other two SSPTBx regis-ters. It has no influence on the operation if

SSPTB2 is written prior to SSPTB1 or vice versa.The following table shows the operation of theSSP depending on which of the transmit bufferregisters are written prior to a transfer.

SSPCLK

SSPDAT

SSPCE0, 1

TB2Full

23 22 17

VR02084C

Byte 0Byte 1Byte 2

16 15 14 9 8 7 6 1 0

TB1Full

TB0Full

WriteTB0

WriteTB1

WriteTB2

Transmit Buffers written Transfer length Transfer sequence

SSPTB2, SSPTB1, SSPTB0 24-bit (3 byte) transfer SSPTB2, SSPTB1, SSPTB0

SSPTB1, SSPTB2, SSPTB0 24-bit (3 Byte) transfer SSPTB2, SSPTB1, SSPTB0

SSPTB1, SSPTB0 16-bit (2 byte) transfer SSPTB1, SSPTB0

SSPTB2, SSPTB0 illegal option -

SSPTB0 8-bit (1 byte) transfer SSPTB0

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Performing a Read OperationIf the SPRW bit in register SSPCON0 is set, aread operation is selected. During a read opera-tion, first information (command or address infor-mation) is transferred from the CPU (master) tothe slave peripheral. Then the transfer direction isswitched, and information is transferred from theslave to the master. As for the write operation, thetransmit buffers SSPTB2...SSPTB0 are written bythe CPU with the information data to be first trans-ferred. Writing to SSPTB0 will start the transfer.The following figure shows the basic waveformsfor a read operation of the SSP.

For the first part of a read operation (transfer ofSSPTBx from master to slave), the same rules asfor the write operation are applied concerning therelation between the transfer length and writes inthe Transmit Buffers.After writing to SSPTB0, firstthe content of the transmit buffers are shifted out.Then the data line SSPDAT is switched to input(high-impedance). After a gap of one bit clock, thedata present at the SSPDAT pin is latched in withthe next 8 clock edges. When the last bit isclocked in, the chip enable line is deactivated onehalf bit time later.

Figure 7-6. Read Operation Waveforms

SSPCLK

SSPCEx

SSPDAT 23/15/7 6 0

0.5

01 7

BT0.5BT

0.5BT

1 BitTime

Data driven by master Data driven by slave

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Chip Enable LinesTwo chip enable lines are provided by the SSPwhich are automatically activated at the beginningof a transfer and deactivated again after the trans-fer is completed. As shown in the previous figures,activation of a chip enable line always begins onehalf bit time before the first data bit is output at theSSPDAT pin, and the deactivation (except for con-tinuous transfers) is performed one half bit time af-ter the last bit of the transfer has been completelytransmitted/received.The chip enable lines are selected through thecontrol bits SSPSEL0 and SSPSEL1. Note thatthese automatic chip enable lines can be extend-ed through normal IO pins, which, however, mustbe activated and deactivated through software. Toavoid conflicts with the automatic chip enablelines, the combination ‘00’ for SSPSEL1..0 disa-bles these lines, and should be programmed whenusing IO lines as additional chip enable signals.It is also possible to activate both chip enable lineswith the combination ‘11’ for SSPSEL1..0. Thiscan be used if the same information has to betransferred to several slaves simultaneously(message broadcast), providing that all slave pe-ripherals use the same clock configuration. Notethat this option should only be used for write oper-ation, since for read operations, a conflict on thedata line SSPDAT could occur if several slave pe-ripherals try to drive this line.

Using the SSP Chip Enable and Clock Linesfor Output FunctionsNote that the polarity and output control bits direct-ly influence the lines SSPCLK, SSPCE0 andSSPCE1, regardless whether a transfer is inprogress or not. It is recommended not to repro-gram these control bits while a transfer is inprogress to avoid false operation of the addressedslave peripheral(s).However, if no transfer is in progress or the SSP isnot used at all, the polarity and output control bitcan be used to perform general purpose outputfunctions on the pins SSPCLK, SSPCE0 andSSPCE1. The possible options are:

- output a low level,

- output a high level,

- high-impedance (tri-state). The pincan be used as a general purpose IOthrough Port 4 P4 register if this portline is configured as an input throughDP4 register.

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Continuous Transfer Modes

In order to simplify communication with somestandard slave devices such as EEPROMs, a con-tinuous transfer mode is implemented in the SSP.This mode is distinguished from the normal modein that the chip enable line is not deactivated auto-matically after a transfer is completed, but insteadremains active until the mode is switched backfrom continuous mode (SSPCM = ‘1’) to normalmode (SSPCM = ‘0’). Thus, consecutive transferscan be performed while holding the chip enableline active during the entire procedure. This condi-tion keeps most peripheral slave devices in theoperational mode initiated through the first com-mand transfer. EEPROMs, for instance, areplaced into a read mode through first transferringa read command to it. This command is followedby the start address of the location to be read. Af-ter this, the EEPROM transfers the data stored inthe specified address to the master. If now thechip enable line is deactivated, the EEPROM can-cels the read mode and returns to idle mode. Anew read operation must again start with the readcommand followed by an address, and then thedata byte at this address is returned to the master.

However, if the chip enable line is not deactivatedafter the EEPROM has transferred the first databyte, the EEPROM automatically increments tothe next address location. If now subsequent clockpulses are applied to the device, the content ofthis next location is transferred to the master, andso on. In this mode, the EEPROM can be continu-ously read without having to issue the read com-mand and the start address again.A similar operation is true for writing to such anEEPROM. These devices allow a certain numberof data bytes to be written after an initial write com-mand followed by a start address for the writes.The figure below shows the write operation in con-tinuous mode. The TB0_Full flag is again used tostart subsequent writes to the slave device. Thegap between the transfers is application depend-ent, since the CPU first has to react on the inter-rupt request at the end of one transfer and rewritethe transmit buffer registers before the next trans-fer will start. This procedure continues until themode is switched from continuous mode to normalmode. The chip enable line will then be deactivat-ed immediately if no transfer is in progress or afterthe current transfer is completed.

Figure 7-7. Write Operation Waveforms in Continuous Mode

SSPCLK

SSPDAT

SSPCE0, 1

TB0Full

SSPInterrupt

23,15,7

22,14,6

Data drivento Slave

Data drivento Slave

0 0 23,15,7

22,14,6

23,15,7

22,14,6 0

Data drivento Slave

DisableContinousMode

WriteTBO

WriteTBO

WriteTBO

ServiceInterrupt

ServiceInterrupt

ServiceInterrupt

VR02084A

180

11/16


The following figure shows the read operation incontinuous mode. Note that the diagram shownstarts at the point where the master has written theinitial information to the slave and switches thedata line SSPDAT from output to input. At the endof a transfer, the byte received from the slave isstored in register SSPRB0, and an internal flagRB0_Full is set. Reading SSPRB0 through soft-ware clears this flag, and issues the next 8 clockpulses to receive the next byte from the slave de-

vice. The time between the transfers dependsagain on the application; the CPU has to react onthe interrupt request and read register SSPRB0 inorder to start the next transfer. This procedurecontinues until the mode is switched from continu-ous mode back to normal mode. The chip enablelines will then be deactivated immediately if notransfer is in progress or after the current transferis completed.

Figure 7-8. Read Operation Waveforms in Continuous Mode

SSPCLK

SSPDAT

SSPCE0, 1

RB0Full

SSPInterrupt

7 6

Data drivento Slave

Data drivenfrom Slave

0 0 7 67 6 0


ReadRBO

ServiceInterrupt

ServiceInterrupt

ServiceInterrupt

VR02084B

0

Byte nByte 1Byte 0

ReadRBO

ReadRBO

ReadRBO


181

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Interrupt Control for the SSPAt the end of a transfer in a read or write opera-tion, the interrupt request flag XP1IR in registerXP1IC will be set. This will cause an interrupt tothe XP1INT interrupt vector or trigger a PEC serv-ice, if the interrupt enable bit XP1IE in registerXP1IC is set, or the software can poll the XP1IRflag. Note that when using polling technique, thesoftware must clear the XP1IR flag.

The timing for the interrupt request generation issuch that the request bit is set one half bit time af-ter completion of the last data bit time. In refer-ence to the normal mode, this is the same timepoint where the chip enable line is deactivated.Note that the distinction between a write or a readoperation interrupt must be performed throughsoftware.

XP1IC (F18Eh) ESFR Reset Value: - - 00h

Note : Please refer to the general Interrupt Control Register description for an explanation of the control fields.

SSP Input/Output Pins

The SSP is connected to the external world viafour signals on Port 4:

Note : These SSP signals are only available on the Port 4 pins, ifPort 4 is not programmed to output all 8 segment address lines. Se-lect 0, 2 or 4 segment address lines (at start-up configuration duringreset) if the SSP is to be used.

5 4 3 2 1 011 10 9 8 7 615 14 13 12

rwrw rw

XP1IR XP1IE

- -- -- -- -

ILVL

rw

GLVL

SSP Signal Port Pin Function

SSPCLK P4.7 Clock Line of the SSP.

SSPDAT P4.6 Data Input/Output Line of the SSP.

SSPCE0 P4.5 Chip Enable Line 0 of the SSP.

SSPCE1 P4.4 Chip Enable Line 1 of the SSP.

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Accessing the On-chip SSPThe SSP is accessed like an external memory orperipheral. That means that the registers of theSSP can be read and written using 16-bit or 8-bitdirect or indirect MEM addressing modes. Sincethe XBUS, to witch the SSP is connected, alsorepresents the external bus, SSP accesses followthe same rules and procedures as accesses to theexternal bus. SSP accesses cannot be executedin parallel to external instruction fetches or dataread/writes, but are arbitrated and inserted intothe external bus access stream.However, the on-chip SSP is accessed via the 16-bit demultiplexed bus mode exclusively. This pro-vides the user the fastest access to the SSP reg-isters.When accessing the on-chip SSP, the bus has tobe switched to the appropriate bus mode withinthe SSP address range. This is done via a specificregister-pair, XBCON1 and XADRS1, which issimilar to the BUSCONx/ADDRSELx register-pairs. With the XBCON1 register (XBUS Bus Con-figuration Register 1), the bus mode, number ofwaitstates, etc., for accessing the SSP are control-led. The XADRS1 register (XBUS Address SelectRegister 1) is used to specify the SSP address ar-ea. Contrary to the BUSCONx/ADDRSELx regis-ters, the XBCON1/XADRS1 registers are mask-programmed, i.e. they are not software program-mable.The mask-programming of these registers is:

XBCON1: 04BFh

XADRS1: 0EF0h

The XBCON1 register is organized like the BUS-CONx registers except that there is no option forread/write chip selects (bits 14 and 15). With themask-programmed value shown above, the fol-lowing options are selected:

XRDYEN:0 READY disabled

XBUSACT:1 XBUS active

XALECTL:0 No ALE Lengthening

XBTYP:10 16-bit DEMUX Bus

XMTTC:1 No Tri-State Wait-state

XRWDC:1 No Read/Write Delay

XMTRC:1101 0 Waitstate

Note : The XBUSACT bit of register XBCON1 onlyenables accesses to the SSP, it does not controlthe external bus (as the other BUSACT bits in theBUSCONs).The XADRS0 register is organized like the otherADDRSELx registers except that it uses the re-duced address ranges, which are defined forXBUS Peripherals. With the mask-programmedvalue shown above, the following options are se-lected:

ADDR: 00’EF00hSSP address areastarts at EF00h in segment 0

RGSZ: 0000 SSP address areacovers 256 bytes

Locating the SSP address area to address EF00hin segment 0 has the advantage that the SSP isaccessible via the data page 3, which is the ‘sys-tem’ data page, accessed usually through the‘system’ data page pointer DPP3. In this way, theinternal addresses, such like SFRs, internal RAM,and the SSP registers, are all located into thesame data page, and form a contiguous addressspace.

Visibility of Accesses to the SSPAn access to the SSP can be made fully visible ex-ternally or not. This option is controlled by the bitVISIBLE in register SYSCON. The grade of visibil-ity depends on several conditions described in thefollowing.

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Single Chip Mode

Since the ST10R163 is a ROMless device, it cannot be run in single chip mode. This description isonly intended for future version that could provideinternal Flash or ROM. The single chip mode isentered during reset with pin EA tied to a logichigh level. The chip will start running in single chipmode without an external bus.

When bit VISIBLE in register SYSCON is cleared,SSP accesses will be completely hidden. Al-though the SSP is connected to the XBUS, whichis an internal implementation of the external bus, itcan be accessed in single chip mode without anyrestriction. No external bus signal will be generat-ed for an access to the SSP address range, be-cause the XBUSACT bit in register XBCON1 onlycontrols accesses to the SSP via the XBUS, itdoes not control the external bus (i.e. PORT0,PORT1, Port 4 and Port 6 can be used for generalpurpose I/O).

When bit VISIBLE in register SYSCON is set, thenaccesses to the SSP can be made visible to theexternal world. To do so, one of the BUSCON reg-isters has to enable a 16-bit demultiplexed exter-nal bus (PORT0 and PORT1 cannot be used forgeneral purpose I/O in this case). All accesses tothe SSP can be monitored externally, andread/write strobes are generated. The visibility ofthe segment address depends on the number ofsegment address lines selected for Port 4.External Bus Mode

If an external bus is enabled through one or moreof the BUSCON registers, PORT0, PORT1, Port 4and Port 6 (or parts of them) may be used to con-trol the external bus.

When bit VISIBLE in register SYSCON is cleared,accesses to the SSP will be partly reflected on theexternal bus. Due to severe timing constraints, it isnot possible to hide SSP accesses completely,when an external bus is enabled. SSP accesseswill be reflected on the external bus in the follow-ing manner:

– The ALE signal will be generated in any case.

– No Read or Write Signals will be generated.

– The data of a read access cannot be seen.

– The visibility of the segment address dependson the number of segment address lines se-lected for Port 4.

– The SSP is connected to the bus controller viaa 16-bit demultiplexed bus. However, addressand data information of a SSP access will beonly on those ports operating in the currentlyselected bus mode, as shown in the table be-low.

When bit VISIBLE in register SYSCON is set, fullvisibility of all SSP accesses is provided, if a 16-bitdemultiplexed bus mode is enabled through oneof the BUSCON registers (PORT0 and PORT1cannot be used for general purpose I/O in thiscase). All SSP accesses can be monitored exter-nally and read/write strobes are generated. Thevisibility of the segment address depends on thenumber of segment address lines selected for Port4.

Currently Selected Bus Mode Port Visible Information of SSP Access

8-bit Multiplexed P0L Low Byte of SSP Write Data

P0H High Byte of SSP Write Data

8-bit Demultiplexed P0L Low Byte of SSP Write Data (High byte not visible)

PORT1 16-bit SSP Address

16-bit Multiplexed PORT0 16-bit SSP Write Data

16-bit Demultiplexed PORT0 16-bit SSP Write Data

PORT1 16-bit SSP Address

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Accessing the SSP in Hold ModeWhen the ST10R163 is placed into hold mode byan external HOLD request, accesses to externalmemory or peripherals have to wait until theHOLD request is deactivated. SSP accesses,however, can be executed in this mode, if bit VIS-IBLE in register SYSCON is cleared. In this case,an access to the SSP is completely invisible to theexternal world. If bit VISIBLE is set, then also SSPaccesses have to wait until the external HOLD re-quest is removed.Note: SSP accesses during HOLD mode areblocked after any attempt to access an external lo-

cation, even if the VISIBLE bit is cleared. The initi-ated external access must be finished first, whichrequires the HOLD condition to be removed.

Power Down Mode

If the ST10R163 enters the Power Down Mode,the XCLK (XBUS Clock) signal will be turned offwhich will stop the operation of the SSP. Anytransfer operation in progress will be interrupted.

After returning from Power Down Mode via hard-ware reset, the SSP has to be reconfigured.

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Notes:

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ST10R163User Manual

11 - WATCHDOG TIMER

To allow recovery from software or hardware fail-ure, the ST10R163 provides a Watchdog Timer. Ifthe software fails to service this timer before anoverflow occurs, an internal reset sequence will beinitiated. This internal reset will also pull theRSTOUT pin low, which also resets the peripheralhardware, which might be the cause for the mal-function. When the watchdog timer is enabled andthe software has been designed to service it regu-larly before it overflows, the watchdog timer willsupervise the program execution, as it only willoverflow if the program does not progress proper-ly. The watchdog timer will also time out, if a soft-ware error was due to hardware related failures.

This prevents the controller from malfunctioningfor longer than a user-specified time.

The watchdog timer provides two registers: aread-only timer register that contains the currentcount, and a control register for initialization.

The watchdog timer is a 16-bit up counter whichcan be clocked with the CPU clock (fCPU) eitherdivided by 2 or divided by 128. This 16-bit timer isrealized as two concatenated 8-bit timers (see fig-ure below). The upper 8 bits of the watchdog timercan be preset to a user-programmable value via awatchdog service access in order to vary thewatchdog expire time. The lower 8 bits are reseton each service access.

Figure 8-1. Watchdog Timer Block Diagram

Figure 8-2 . SFRs and Port Pins associated with the Watchdog Timer

WDTCONRSTOUT

Reset Indication Pin Data Registers Control Registers

WDT

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11 - WATCHDOG TIMER (ST10R163)

Operation of the Watchdog TimerThe current count value of the Watchdog Timer iscontained in the Watchdog Timer Register WDT,which is a non-bitaddressable read-only register.The operation of the Watchdog Timer is controlledby its bitaddressable Watchdog Timer ControlRegister WDTCON. This register specifies the re-load value for the high byte of the timer, selectsthe input clock prescaling factor and provides aflag that indicates a watchdog timer overflow.After any software reset, external hardware reset(see note), or watchdog timer reset, the watchdogtimer is enabled and starts counting up from0000h with the frequency fCPU/2. The input fre-quency may be switched to fCPU/128 by settingbit WDTIN. The watchdog timer can be disabledvia the instruction DISWDT (Disable WatchdogTimer). Instruction DISWDT is a protected 32-bitinstruction which will ONLY be executed duringthe time between a reset and execution of eitherthe EINIT (End of Initialization) or the SRVWDT(Service Watchdog Timer) instruction. Either oneof these instructions disables the execution ofDISWDT.When the watchdog timer is not disabled via in-struction DISWDT, it will continue counting up,even during Idle Mode. If it is not serviced via theinstruction SRVWDT by the time the count reach-es FFFFh the watchdog timer will overflow andcause an internal reset. This reset will pull the ex-ternal reset indication pin RSTOUT low. It differsfrom a software or external hardware reset in thatbit WDTR (Watchdog Timer Reset Indication Flag)of register WDTCON will be set. A hardware reset

or the SRVWDT instruction will clear this bit. BitWDTR can be examined by software in order todetermine the cause of the reset.

A watchdog reset will also complete a running ex-ternal bus cycle before starting the internal resetsequence if this bus cycle does not useREADY orsamples READY active (low) after the pro-grammed waitstates. Otherwise the external buscycle will be aborted.

Note : After a hardware reset that activates theBootstrap Loader the watchdog timer will be disa-bled

To prevent the watchdog timer from overflowing, itmust be serviced periodically by the user soft-ware. The watchdog timer is serviced with the in-struction SRVWDT, which is a protected 32-bit in-struction. Servicing the watchdog timer clears thelow byte and reloads the high byte of the watch-dog time register WDT with the preset value in bitfield WDTREL, which is the high byte of registerWDTCON. Servicing the watchdog timer will alsoreset bit WDTR. After being serviced the watch-dog timer continues counting up from the value(<WDTREL> * 28). Instruction SRVWDT has beenencoded in such a way that the chance of uninten-tionally servicing the watchdog timer (eg. by fetch-ing and executing a bit pattern from a wrong loca-tion) is minimized. When instruction SRVWDTdoes not match the format for protected instruc-tions, the Protection Fault Trap will be entered,rather than the instruction be executed.

WDTCON (FFAEh / D7h) SFR Reset Value: 000Xh

Note: The reset value will be 0002h, if the reset was triggered by the watchdog timer (overflow). It will be 0000h other-wise.

Bit Function

WDTINWatchdog Timer Input Frequency Selection‘0’: Input frequency is fCPU / 2

‘1’: Input frequency is fCPU / 128

WDTRWatchdog Timer Reset Indication FlagSet by the watchdog timer on an overflow.Cleared by a hardware reset or by the SRVWDT instruction.

WDTREL Watchdog Timer Reload Value (for the high byte)

-WDT

R-WDT

IN- ---

5 4 3 2 1 011 10 9 8 7 615 14 13 12

- - - rrw - -

WDTREL

- rw

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The time period for an overflow of the watchdogtimer is programmable in two ways:

• the input frequency to the watchdog timer canbe selected via bit WDTIN in register WDTCONto be either fCPU/2 or fCPU/128.• the reload value WDTREL for the high byte ofWDT can be programmed in register WDTCON.

The period PWDT between servicing the watchdogtimer and the next overflow can therefore be de-termined by the following formula:

The table below marks the possible ranges for thewatchdog time which can be achieved using aCPU clock of 20 MHz. Some numbers are round-ed to 3 significant digits.Note : For safety reasons, the user is advised torewrite WDTCON each time before the watchdogtimer is serviced.

PWDT =fCPU

2(1 + <WDTIN>*6) * (216 - <WDTREL> * 28)

Reload value

in WDTREL

Prescaler for f CPU

2 (WDTIN = ‘0’) 128 (WDTIN = ‘1’)

FFh 25.6 ms 1.6 ms

00h 6.55 ms 419 ms

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Note:

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ST10R163User Manual

12 - SYSTEM RESET

The internal system reset function provides initial-ization of the ST10R163 into a defined defaultstate and is invoked either by asserting a hard-ware reset signal on pin RSTIN (Hardware ResetInput), upon the execution of the SRST instruction(Software Reset) or by an overflow of the watch-dog timer

Whenever one of these conditions occurs, the mi-crocontroller is reset into its predefined defaultstate through an internal reset procedure. When areset is initiated, pending internal hold states arecancelled and the current internal access cycle (ifany) is completed. An external bus cycle is abort-ed, except for a watchdog reset (see description).After that the bus pin drivers and the IO pin driversare switched off (tristate). RSTOUT is activateddepending on the reset source.

The internal reset procedure requires 516 CPUclock cycles (25.8 µs @ 20 MHz CPU clock) in or-

der to perform a complete reset sequence. This516 cycle reset sequence is started upon a watch-dog timer overflow, a SRST instruction or whenthe reset input signal RSTIN is latched low (hard-ware reset). The internal reset condition is activeat least for the duration of the reset sequence andthen until the RSTIN input is inactive. When thisinternal reset condition is removed (reset se-quence complete and RSTIN inactive), the resetconfiguration is latched from PORT0, and pinsALE, RD and WR are driven to their inactive lev-els.

After the internal reset condition is removed, themicrocontroller will start program execution frommemory location 00’0000h in code segment zero.This start location will typically hold a branch in-struction to the start of a software initialization rou-tine for the application specific configuration of pe-ripherals and CPU Special Function Registers.

Figure 9-1. External Reset Circuitry

ST10R163

Reset

VCC

ExternalHardware

RSTOUT

&ExternalResetSources+

a) Generated Warm resetb) Automatic Power-on reset

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12 - SYSTEM RESET (ST10R163)

Hardware ResetA hardware reset is triggered when the reset inputsignal RSTIN is latched low. To ensure the recog-nition of the RSTIN signal (latching), it must beheld low for at least 2 CPU clock cycles. However,also shorter RSTIN pulses may trigger a hardwarereset, if they coincide with the latch’s samplepoint. RSTIN may go high during the reset se-quence. After the reset sequence has been com-pleted, the RSTIN input is sampled. When the re-set input signal is active at that time the internal re-set condition is prolonged untilRSTIN gets inac-tive.

The input RSTIN provides an internal pullup de-vice equalling a resistor of 50 KΩ to 150 KΩ (theminimum reset time must be determined by thelowest value). Simply connecting an external ca-pacitor is sufficient for an automatic power-on re-set (see a) in figure above). RSTIN may also beconnected to the output of other logic gates (seeb) in figure above).

Note: Driving RSTIN low for 2 CPU clock cycles isonly sufficient for a hardware triggered warm re-set. A power-on reset requires an active time oftwo reset sequences (1036 CPU clock cycles) af-ter a stable clock signal is available (about 10...50ms to allow the on-chip oscillator to stabilize).

Software ResetThe reset sequence can be triggered at any timevia the protected instruction SRST (Software Re-set). This instruction can be executed deliberatelywithin a program, eg. to leave bootstrap loadermode, or upon a hardware trap that reveals a sys-tem failure.

A software reset disregards the configuration ofP0L.5...P0L.0.Watchdog Timer ResetWhen the watchdog timer is not disabled duringthe initialization or serviced regularly during pro-gram execution is will overflow and trigger the re-set sequence. Other than hardware and softwarereset the watchdog reset completes a running ex-ternal bus cycle if this bus cycle either does notuse READY at all, or if READY is sampled active(low) after the programmed waitstates. WhenREADY is sampled inactive (high) after the pro-grammed waitstates the running external bus cy-cle is aborted. Then the internal reset sequence isstarted.

Note : A watchdog reset disregards the configura-tion of P0L.5...P0L.0.The watchdog reset cannot occur while theST10R163 is in bootstrap loader mode!

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12.1 THE ST10R163’S PINS AFTER RESET

After the reset sequence the different groups ofpins of the ST10R163 are activated in differentways depending on their function. Bus and controlsignals are activated immediately after the resetsequence according to the configuration latchedfrom PORT0, so either external accesses can

takes place or the external control signals are in-active. The general purpose IO pins remain in in-put mode (high impedance) until reprogrammedvia software (see figure below). TheRSTOUT pinremains active (low) until the end of the initializa-tion routine (see description).

Figure 9-2. Reset Input and Output Signals

RSTOUT

RSTIN

1)

1. Current bus cycle is completed or aborted.2. Switches asynchronously with RSTIN, synchronously upon software or watchdog reset.3. The reset condition ends here. The ST10R163 starts program execution.4. Activation of the IO pins is controlled by software.5. Execution of the EINIT instruction.6. The shaded area designates the internal reset sequence, which starts after synchronization of RSTIN.

Internal reset condition

3)

Initialization

6)

Bus

Internal reset condition Initialization

ALE

RD, WR

RSTIN

2)IO

2)

3)

5)

4)

6)

When the internal reset condition is prolongued by RSTIN, the activation of the output signals isdelayed until the end of the internal reset condition .

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12.2 RESET OUTPUT PIN

The RSTOUT pin is dedicated to generate a resetsignal for the system components besides thecontroller itself. RSTOUT will be driven active(low) at the begin of any reset sequence (triggeredby hardware, the SRST instruction or a watchdogtimer overflow). RSTOUT stays active (low) be-yond the end of the internal reset sequence untilthe protected EINIT (End of Initialization) instruc-tion is executed (see figure above). This allows tocompletely configure the controller including itson-chip peripheral units before releasing the resetsignal for the external peripherals of the system.

12.3 WATCHDOG TIMER OPERATION AFTERRESET

The watchdog timer starts running after the inter-nal reset has completed. It will be clocked with theinternal system clock divided by 2 (10 MHz @fCPU=20 MHz), and its default reload value is00h, so a watchdog timer overflow will occur131072 CPU clock cycles (6.55 ms @fCPU=20MHz) after completion of the internal reset, unlessit is disabled, serviced or reprogrammed mean-while. When the system reset was caused by awatchdog timer overflow, the WDTR (WatchdogTimer Reset Indication) flag in register WDTCONwill be set to ’1’. This indicates the cause of the in-ternal reset to the software initialization routine.WDTR is reset to ’0’ by an external hardware resetor by servicing the watchdog timer. After the inter-nal reset has completed, the operation of thewatchdog timer can be disabled by the DISWDT(Disable Watchdog Timer) instruction. This in-struction has been implemented as a protected in-struction. For further security, its execution is onlyenabled in the time period after a reset until eitherthe SRVWDT (Service Watchdog Timer) or theEINIT instruction has been executed. Thereafterthe DISWDT instruction will have no effect.

12.4 RESET VALUES FOR THE ST10R163REGISTERS

During the reset sequence the registers of theST10R163 are preset with a default value. MostSFRs, including system registers and peripheralcontrol and data registers, are cleared to zero, soall peripherals and the interrupt system are off oridle after reset. A few exceptions to this rule pro-vide a first pre-initialization, which is either fixed orcontrolled by input pins.

DPP1:0001h (points to data page 1)



CP: FC00h

STKUN:FC00h

STKOV:FA00h

SP: FC00h

WDTCON:0002h, if reset was triggered bya watchdog timer overflow, 0000h

otherwise

S0RBUF:XXh (undefined)

SSCRB:XXXXh (undefined)

SYSCON:0XX0h (set according to resetconfiguration)

BUSCON0:0XX0h (set according to resetconfiguration)

RP0H:XXh (reset levels of P0H)

ONES:FFFFh (fixed value)

12.5 THE INTERNAL RAM AFTER RESET

The contents of the internal RAM are not affectedby a system reset. However, after a power-on re-set, the contents of the internal RAM are unde-fined. This implies that the GPRs (R15...R0) andthe PEC source and destination pointers(SRCP7...SRCP0, DSTP7...DSTP0) which aremapped into the internal RAM are also unchangedafter a warm reset, software reset or watchdog re-set, but are undefined after a power-on reset.

12.6 PORTS AND EXTERNAL BUSCONFIGURATION DURING RESET

During the internal reset sequence all of theST10R163’s port pins are configured as inputs byclearing the associated direction registers, andtheir pin drivers are switched to the high imped-ance state. This ensures that the ST10R163 andexternal devices will not try to drive the same pinto different levels. Pin ALE is held low through aninternal pulldown, and pins RD and WR are heldhigh through internal pullups. Also the pins select-ed for CS output will be pulled high.

The registers SYSCON and BUSCON0 are initial-ized according to the configuration selected viaPORT0.

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PORTS AND EXTERNAL BUS CONFIGURATION DURING RESET (Cont’d)

Pin EA must be held at ‘0’ level.

• the Bus Type field (BTYP) in register BUSCON0is initialized according to P0L.7 and P0L.6

• bit BUSACT0 in register BUSCON0 is set to ‘1’

• bit ALECTL0 in register BUSCON0 is set to ‘1’

• bit ROMEN in register SYSCON will be clearedto ‘0’

• bit BYTDIS in register SYSCON is set accordingto the data bus width

The other bits of register BUSCON0, and the otherBUSCON registers are cleared. This default initial-ization selects the slowest possible external ac-cesses using the configured bus type. The Readyfunction is disabled at the end of the internal sys-tem reset.

When the internal reset has completed, the config-uration of PORT0, PORT1, Port 4, Port 6 and ofthe BHE signal (High Byte Enable, alternate func-tion of P3.12) depends on the bus type which wasselected during reset. When any of the externalbus modes was selected during reset, PORT0(and PORT1) will operate in the selected busmode. Port 4 will output the selected number ofsegment address lines (all zero after reset) andPort 6 will drive the selected number ofCS lines(CS0 will be ‘0’, while the other activeCS lines willbe ‘1’). When no memory accesses above 64 Kare to be performed, segmentation may be disa-bled.

All other pins remain in the high-impedance stateuntil they are changed by software or peripheraloperation.

12.7 APPLICATION-SPECIFIC INITIALIZATIONROUTINE

After the internal reset condition is removed theST10R163 fetches the first instruction from loca-tion 00’0000h, which is the first vector in thetrap/interrupt vector table, the reset vector. 4words (locations 00’0000h through 00’0007h) areprovided in this table to start the initialization afterreset. As a rule, this location holds a branch in-struction to the actual initialization routine thatmay be located anywhere in the address space.

After reset, it may be desirable to reconfigure theexternal bus characteristics, because the SY-SCON register is initialized during reset to theslowest possible memory configuration.

To decrease the number of instructions requiredto initialize the ST10R163, each peripheral is pro-grammed to a default configuration upon reset,but is disabled from operation. These default con-figurations can be found in the descriptions of theindividual peripherals.

During the software design phase, portions of theinternal memory space must be assigned to regis-ter banks and system stack. When initializatingthe stack pointer (SP) and the context pointer(CP), it must be ensured that these registers areinitialized before any GPR or stack operation isperformed. This includes interrupt processing,which is disabled upon completion of the internalreset, and should remain disabled until the SP isinitialized.

Note : Traps (incl. NMI) may occur, even thoughthe interrupt system is still disabled.

In addition, the stack overflow (STKOV) and thestack underflow (STKUN) registers should be ini-tialized. After reset, the CP, SP, and STKUN reg-isters all contain the same reset value 00’FC00h,while the STKOV register contains 00’FA00h.With the default reset initialization, 256 words ofsystem stack are available, where the systemstack selected by the SP grows downwards from00’FBFEh, while the register bank selected by theCP grows upwards from 00’FC00h.

Based on the application, the user may wish to in-itialize portions of the internal memory before nor-mal program operation. Once the register bankhas been selected by programming the CP regis-ter, the desired portions of the internal memorycan easily be initialized via indirect addressing.

At the end of the initialization, the interrupt systemmay be globally enabled by setting bit IEN in reg-ister PSW. Care must be taken not to enable theinterrupt system before the initialization is com-plete.

The software initialization routine should be termi-nated with the EINIT instruction. This instructionhas been implemented as a protected instruction.Execution of the EINIT instruction disables the ac-tion of the DISWDT instruction, disables write ac-cesses to register SYSCON (see note) and caus-es the RSTOUT pin to go high. This signal can beused to indicate the end of the initialization routineand the proper operation of the microcontroller toexternal hardware.

Note : All configurations regarding register SY-SCON (enable CLKOUT, stacksize, etc.) must beselected before the execution of EINIT.

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APPLICATION-SPECIFIC INITIALIZATION ROUTINE (Cont’d)System Startup Configuration

Although most of the programmable features ofthe ST10R163 are either selected during the ini-tialization phase or repeatedly during program ex-ecution, there are some features that must be se-lected earlier, because they are used for the firstaccess of the program execution (eg. external busconfiguration).

These selections are made during reset via thepins of PORT0, which are read during the internalreset sequence. During reset internal pullup devic-es are active on the PORT0 lines, so their inputlevel is high, if the respective pin is left open, or islow, if the respective pin is connected to an exter-nal pulldown device. The coding of the selections,as shown below, allows in many cases to use thedefault option, ie. high level.

The value on the upper byte of PORT0 (P0H) islatched into register RP0H upon reset, the valueon the lower byte (P0L) directly influences theBUSCON0 register (bus mode) or the internalcontrol logic of the ST10R163.

The pins that control the operation of the internalcontrol logic and the reserved pins are evaluatedonly during a hardware triggered reset sequence.The pins that influence the configuration of theST10R163 are evaluated during any reset se-quence, ie. also during software and watchdogtimer triggered resets.The configuration via P0H is latched in registerRP0H for subsequent evaluation by software.Register RP0H is described in chapter “The Exter-nal Bus Interface”.Note : The reserved pins (marked “R”) must re-main high during reset in order to ensure properoperation of the ST10R163. The load on thosepins must be small enough for the internal pullupdevice to keep their level high, or external pullupdevices must ensure the high level.The pins marked “X” should be left open forST10R163 devices that do not use them.The following describes the different selectionsthat are offered for reset configuration. The defaultmodes refer to pins at high level, ie. without exter-nal pulldown devices connected. Please also con-sider the note (above) on reserved pins.

Figure 9-3. PORT0 Configuration during Reset

RRR EMUADPRWRCFG

L.5 L.4 L.3 L.2 L.1 L.0H.3 H.2 H.1 H.0 L.7 L.6H.7 H.6 H.5 H.4

CSSELSALSEL BUSTYP

RP0H

System ClockLogic

Port 4Logic

Port 6Logic

SYSCON BUSCON0

Internal Control Logic(Only on hardware reset)

CLKSEL

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APPLICATION-SPECIFIC INITIALIZATION ROUTINE (Cont’d)Emulation ModePin P0L.0 (EMU) selects the Emulation Mode,when low during reset. This mode allows the ac-cess to integrated XBUS peripherals via the exter-nal bus interface pins in application specific ver-sions of the ST10R163.This mode is used for special emulator purposesand is of no use in basic ST10R163 devices, so inthis case P0L.0 should be held high.Default: Emulation Mode is off.

Adapt ModePin P0L.1 (ADP) selects the Adapt Mode, whenlow during reset. In this mode the ST10R163 goesinto a passive state, which is similar to its stateduring reset. The pins of the ST10R163 float totristate or are deactivated via internal pullup/pull-down devices, as described for the reset state. Inaddition also the RSTOUT pin floats to tristaterather than be driven low, and the on-chip oscilla-tor is switched off.

This mode allows to switch a ST10R163 that ismounted to a board virtually off, so an emulatormay control the board’s circuitry, even though theoriginal ST10R163 remains in its place. The origi-nal ST10R163 also may resume to control theboard after a reset sequence with P0L.1 high.Default: Adapt Mode is off.Note: When XTAL1 is fed by an external clockgenerator (while XTAL2 is left open), this clocksignal may also be used to drive the emulator de-vice.However, if a crystal is used, the emulator de-vice’s oscillator can use this crystal only, if at leastXTAL2 of the original device is disconnected fromthe circuitry (the output XTAL2 will still be active inAdapt Mode).

System Clock Configuration

Pins P0H.7 to P0H.5 (PLLSEL) selects the Sys-tem Clock Configuration at reset. The SystemClock (CPU Clock) can be selected to be 0.5, 1, 2,2.5, 3, 4 or 5 times the externally applied frequen-cy at the XTAL-pins. The required system config-uration setups are described in more details inchapter “System Clock Generator”.

External Bus Type

Pins P0L.7 and P0L.6 (BUSTYP) select the exter-nal bus type during reset. This allows to configurethe external bus interface of the ST10R163 evenfor the first code fetch after reset. The two bits arecopied into bit field BTYP of register BUSCON0.P0L.7 controls the data bus width, while P0L.6controls the address output (multiplexed or demul-tiplexed). This bit field may be changed via soft-ware after reset, if required.

PORT0 and PORT1 are automatically switched tothe selected bus mode. In multiplexed bus modesPORT0 drives both the 16-bit intra-segment ad-dress and the output data, while PORT1 remainsin high impedance state as long as no demulti-plexed bus is selected via one of the BUSCONregisters. In demultiplexed bus modes PORT1drives the 16-bit intra-segment address, whilePORT0 or P0L (according to the selected data buswidth) drives the output data.For a 16-bit data bus BHE is automatically ena-bled, for an 8-bit data bus BHE is disabled via bitBYTDIS in register SYSCON.

Default: 16-bit data bus with multiplexed address-es.

Note : ST10R165 being a ROMless device, pinEAmust be connected to ground (external start).

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APPLICATION-SPECIFIC INITIALIZATION ROUTINE (Cont’d)Chip Select LinesPins P0H.2 and P0H.1 (CSSEL) define thenumber of active chip select signals during reset.This allows to control which pins of Port 6 drive ex-ternal CS signals and which are used for generalpurpose IO. The two bits are latched in registerRP0H.Default: All 5 chip select lines active (CS4...CS0).Note: The selected number of CS signals cannotbe changed via software after reset.Segment Address LinesPins P0H.4 and P0H.3 (SALSEL) define thenumber of active segment address lines during re-set. This allows to control which pins of Port 4drive address lines and which are used for generalpurpose IO. The two bits are latched in registerRP0H. Depending on the system architecture therequired address space is chosen and accessibleright from the start, so the initialization routine candirectly access all locations without prior program-

ming. The required pins of Port 4 are automaticallyswitched to address output mode.Even if not all segment address lines are enabledon Port 4, the ST10R163 internally uses its com-plete 24-bit addressing mechanism. This allows torestrict the width of the effective address bus,while still deriving CS signals from the completeaddresses.

Default: 2-bit segment address (A17...A16) allow-ing access to 256 KByte.

Note : The selected number of segment addresslines cannot be changed via software after reset.BHE Pin ConfigurationPin P0H.0 defines the write configuration control(bit WRCFG of SYSCON register). If P0H.0 ispulled down during reset, the bit WRCFG is set to‘1’ and the pin BHE is configured as WRH (WriteHigh Byte) while pin WR is configured as WRL(Write Low Byte). Default: pins WR and BHE re-tain their normal functions.

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ST10R163User Manual

13 - POWER REDUCTION MODES

Two different power reduction modes with differ-ent levels of power reduction have been imple-mented in the ST10R163, which may be enteredunder software control.In Idle mode the CPU is stopped, while the pe-ripherals continue their operation. Idle mode canbe terminated by any reset or interrupt request.In Power Down mode both the CPU and the pe-ripherals are stopped. Power Down mode canonly be terminated by a hardware reset.Note: All external bus actions are completed be-fore Idle or Power Down mode is entered. Howev-er, Idle or Power Down mode is not entered ifREADY is enabled, but has not been activated(driven low) during the last bus access.

13.1 IDLE MODE

The power consumption of the ST10R163 micro-controller can be decreased by entering Idlemode. In this mode all peripherals, including thewatchdog timer, continue to operate normally,only the CPU operation is halted.

Idle mode is entered after the IDLE instruction hasbeen executed and the instruction before the IDLEinstruction has been completed. To prevent unin-tentional entry into Idle mode, the IDLE instructionhas been implemented as a protected 32-bit in-struction.

Idle mode is terminated by interrupt requests fromany enabled interrupt source whose individual In-terrupt Enable flag was set before the Idle modewas entered, regardless of bit IEN.

For a request selected for CPU interrupt servicethe associated interrupt service routine is enteredif the priority level of the requesting source is high-er than the current CPU priority and the interruptsystem is globally enabled. After the RETI (Returnfrom Interrupt) instruction of the interrupt serviceroutine is executed the CPU continues executingthe program with the instruction following the IDLEinstruction. Otherwise, if the interrupt request can-not be serviced because of a too low priority or aglobally disabled interrupt system the CPU imme-diately resumes normal program execution withthe instruction following the IDLE instruction.

Figure 10-1. Transitions between Idle mode and active mode

ActiveMode

IdleMode

IDLE instruction

CPU Interrupt Request

Denied PEC Request ExecutedPEC Request

denied

accepted

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13 - POWER REDUCTION MODES (ST10R163)

IDLE MODE (Cont’d)

For a request which was programmed for PECservice a PEC data transfer is performed if the pri-ority level of this request is higher than the currentCPU priority and the interrupt system is globallyenabled. After the PEC data transfer has beencompleted the CPU remains in Idle mode. Other-wise, if the PEC request cannot be serviced be-cause of a too low priority or a globally disabled in-terrupt system the CPU does not remain in Idlemode but continues program execution with theinstruction following the IDLE instruction.Idle mode can also be terminated by a Non-Mask-able Interrupt, ie. a high to low transition on theNMI pin. After Idle mode has been terminated byan interrupt or NMI request, the interrupt systemperforms a round of prioritization to determine thehighest priority request. In the case of an NMI re-quest, the NMI trap will always be entered.Any interrupt request whose individual InterruptEnable flag was set before Idle mode was enteredwill terminate Idle mode regardless of the currentCPU priority. The CPU will not go back into Idlemode when a CPU interrupt request is detected,even when the interrupt was not serviced becauseof a higher CPU priority or a globally disabled in-terrupt system (IEN=’0’). The CPU will only goback into Idle mode when the interrupt system isglobally enabled (IEN=’1’)and a PEC service on apriority level higher than the current CPU level isrequested and executed.Note: An interrupt request which is individually en-abled and assigned to priority level 0 will terminateIdle mode. The associated interrupt vector will notbe accessed, however.The watchdog timer may be used to monitor theIdle mode: an internal reset will be generated if nointerrupt or NMI request occurs before the watch-dog timer overflows. To prevent the watchdog tim-er from overflowing during Idle mode it must beprogrammed to a reasonable time interval beforeIdle mode is entered.

13.2 POWER DOWN MODE

To further reduce the power consumption the mi-crocontroller can be switched to Power Downmode. Clocking of all internal blocks is stopped,the contents of the internal RAM, however, arepreserved through the voltage supplied via theVCC pins. The watchdog timer is stopped in PowerDown mode. This mode can only be terminated byan external hardware reset, ie. by asserting a lowlevel on the RSTIN pin. This reset will initialize allSFRs and ports to their default state, but will notchange the contents of the internal RAM.

There are two levels of protection against uninten-tionally entering Power Down mode. First, thePWRDN (Power Down) instruction which is usedto enter this mode has been implemented as aprotected 32-bit instruction. Second, this instruc-tion is effective only if the NMI (Non Maskable In-terrupt) pin is externally pulled low while thePWRDN instruction is executed. The microcon-troller will enter Power Down mode after thePWRDN instruction has completed.

This feature can be used in conjunction with anexternal power failure signal which pulls theNMIpin low when a power failure is imminent. The mi-crocontroller will enter the NMI trap routine whichcan save the internal state into RAM. After the in-ternal state has been saved, the trap routine mayset a flag or write a certain bit pattern into specificRAM locations, and then execute the PWRDN in-struction. If the NMI pin is still low at this time,Power Down mode will be entered, otherwise pro-gram execution continues. During power down thevoltage at the VCC pins can be lowered to 2.5 Vwhile the contents of the internal RAM will still bepreserved.

The initialization routine (executed upon reset)can check the identification flag or bit pattern with-in RAM to determine whether the controller wasinitially switched on, or whether it was properly re-started from Power Down mode.

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13.3 STATUS OF OUTPUT PINS DURING IDLE AND POWER DOWN MODE

During Idle mode the CPU clocks are turned off,while all peripherals continue their operation in thenormal way. Therefore all ports pins, which areconfigured as general purpose output pins, outputthe last data value which was written to their portoutput latches. If the alternate output function of aport pin is used by a peripheral, the state of the pinis determined by the operation of the peripheral.

Port pins which are used for bus control functionsgo into that state which represents the inactivestate of the respective function (eg.WR), or to adefined state which is based on the last bus ac-cess (eg. BHE). Port pins which are used as exter-nal address/data bus hold the address/data whichwas output during the last external memory ac-cess before entry into Idle mode under the follow-ing conditions:

P0H outputs the high byte of the last address if amultiplexed bus mode with 8-bit data bus is used,otherwise P0H is floating. P0L is always floating inIdle mode.

PORT1 outputs the lower 16 bits of the last ad-dress if a demultiplexed bus mode is used, other-wise the output pins of PORT1 represent the portlatch data.Port 4 outputs the segment address for the last ac-cess on those pins that were selected during re-set, otherwise the output pins of Port 4 representthe port latch data.During Power Down mode the oscillator and theclocks to the CPU and to the peripherals areturned off. Like in Idle mode, all port pins whichare configured as general purpose output pinsoutput the last data value which was written totheir port output latches.When the alternate output function of a port pin isused by a peripheral the state of this pin is deter-mined by the last action of the peripheral beforethe clocks were switched off.The table below summarizes the state of allST10R163 output pins during Idle and PowerDown mode.

Note:

1. High if EINIT was executed before entering Idle or Power Down mode, Low otherwise.2. For multiplexed buses with 8-bit data bus.3. For demultiplexed buses.

4. The CS signal that corresponds to the last address remains active (low), all other enabledCS signalsremain inactive (high).

ST10R163Output Pin(s)

Idle Mode Power Down Mode

ALE Low Low

RD, WR High High

CLKOUT Active High

RSTOUT 1) 1)

P0L Floating Floating

P0H A15...A8 2) / Float A15...A8 2) / Float

PORT1Last Address 3) /Port Latch Data

Last Address 3) /Port Latch Data

Port 4 Port Latch Data/Last segment Port Latch Data/Last segment

BHE Last value Last value

HLDA Last value Last value

BREQ High High

CSx Last value 4) Last value 4)

Other Port Output Pins Port Latch Data / Alternate Function Port Latch Data / Alternate Function

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Notes :

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ST10R163User Manual

14 - SYSTEM CLOCK GENERATOR

The system clock generator includes an on-chipPLL circuit that allows to operate the ST10R163on a variety of external clock frequency. This PLLcan multiply the external clock frequency by afixed factor of 1.5, 2, 2.5, 3, 4 or 5, this factor is se-lected via pins P0H.7 through P0H.5 during reset.The PLL generates a CPU clock signal with 50%duty cycle. The PLL also provides fail safe mech-anisms which allow to detect frequency deviationsand to perform emergency actions in case of anexternal clock failure. The PLL may also be disa-bled via pins P0H.7..5 during reset in which casethe ST10R163 will directly run on the externalclock or on external clock divided by 2 (see figurebelow).

14.1 PLL Operation

The PLL is enabled when pin P0H.7 is latchedhigh or low if pin P0H.5 is latched low during reset.The multiply factor of the PLL is set via pins P0H.6and P0H.5 latched during reset (see table below).On power-up, the PLL provides a stable clock sig-nal on its basic frequency of 2..10 MHz within ca.0.5 ms after VCC has reached 5 V+/-10%, even ifthere is no external clock signal. The PLL startssynchronizing with the external clock signal assoon as it is available. Within 2 ms after stable os-cillations of the external clock within the specifiedfrequency range, the PLL will be synchronous withthis clock at the frequency (Multiply Factor) *fOSC,ie. the PLL locks to the external clock.

Figure 11-1. Block Diagram of System Clock Generator

VR02079A

Oscillator

Circuit

: 2

PLL CircuitfPLL= n * fOSC

n = 1/1.5/2/2.5/3/4/5

MUX fCPU

XTAL2

POH. (7..5)Reset

fPLL

PWRDN XP3INT

fOSC

XTAL1

Reset POH.(7..5)

Reset LocknSleep3

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14 - SYSTEM CLOCK GENERATOR (ST10R163)

System Clock Generator Configuration

Note: If the ST10R163 is required to operate on the desired CPU clock directly after reset, make sure that RSTIN remainsactive until the PLL has locked.

The PLL constantly synchronizes to the externalclock signal. Due to the fact that the external fre-quency is 1/(Multiply Factor)th of the PLL outputfrequency, the output frequency may be slightlyhigher or lower than the desired frequency. Thisjitter is irrelevant for longer time periods. For shortperiods (1..4 CPU clock cycles), it remains below5%.

The PLL detects frequency changes of the inputclock signal and generates an interrupt request inthis case. This warning interrupt indicates that thePLL frequency is no more locked, ie. no more sta-ble. This occurs when the input clock is unstableand especially when the input clock fails complet-ly, ie. due to a broken crystal. In this case, the syn-chronization mechanism will reduce the PLL out-put frequency down to the PLL’s basic frequency(2..10 MHz). The basic frequency is still generatedand allows the CPU to execute emergency actionsin case of a loss of external clock.

Note: The lock failure interrupt request (XP3IR)will be generated repeatedly as long as an unsta-ble (or missing) input clock is detected, eventhough XP3IR is cleared upon entry to the inter-rupt service handler. The software of the lock fail-ure interrupt service handler should take care ofthis fact.

14.2 Prescaler Operation

When pins P0.15-13 (P0H.7-5) equal ’001’ duringreset the CPU clock is derived from the internaloscillator (input clock signal) by a 2:1 prescaler.The frequency of fCPU is half the frequency of fX-TAL and the high and low time of fCPU (ie. the du-ration of an individual TCL) is defined by the peri-od of the input clock fXTAL.

Note that the PLL is internally running on its free-running frequency and delivers the clock signal forthe Oscillator Watchdog.

14.3 Direct Drive

When pins P0.15-13 (P0H.7-5) equal ’011’ duringreset the on-chip phase locked loop is disabledand the CPU clock is directly driven from the inter-nal oscillator with the input clock signal.The frequency of fCPU directly follows the frequen-cy of fXTAL so the high and low time of fCPU (i.e.the duration of an individual TCL) is defined by theduty cycle of the input clock fXTAL.Note that the PLL is internally running on its free-running frequency and delivers the clock signal forthe Oscillator Watchdog.

14.4 Oscillator Watchdog

When the clock option selected is direct drive ordirect drive with prescaler, in order to provide a failsafe mechanism in case of a loss of the externalclock, an oscillator watchdog is implemented asan additional functionality of the PLL circuitry. Thisoscillator watchdog operates as follows:After reset, the PLL is running on its free-runningfrequency, and increment the Oscillator Watchdogcounter. On each transition of XTAL1 pin, the Os-cillator Watchdog is cleared. If an external clockfailure occurs, then the Oscillator Watchdog coun-ter overflows (after 16 PLL clock cycles). The CPUclock signal will be switched to the PLL free-run-ning clock signal, and the Oscillator Watchdog In-terrupt Request (XP3INT) is flagged. The CPUclock will not switch back to the external clockeven if a valid external clock exits on XTAL1 pin.Only a hardware reset can switch the CPU clocksource back to direct clock input.

P0H.7 P0H.6 P0H.5 Multiply Factor

1 1 1 fCPU = 4 * fOSC (default configuration)

1 1 0 fCPU = 2 * fOSC

1 0 1 fCPU = 3 * fOSC

1 0 0 fCPU = 5 * fOSC

0 1 1 fCPU = fOSC (direct clock drive, PLL is bypassed)

0 1 0 fCPU = 1.5 * fOSC

0 0 1 fCPU = 0.5 * fOSC (clock prescaler (divider by 2) is enabled, PLL is bypassed)

0 0 0 fCPU = 2.5 * fOSC

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ST10R163User Manual

15 - SYSTEM PROGRAMMING

To aid in software development, a number of fea-tures has been incorporated into the instructionset of the ST10R163, including constructs formodularity, loops, and context switching. In manycases commonly used instruction sequenceshave been simplified while providing greater flexi-bility. The following programming features help tofully utilize this instruction set.

15.1 INSTRUCTIONS PROVIDED AS SUBSETSOF INSTRUCTIONS

In many cases, instructions found in other micro-controllers are provided as subsets of more pow-erful instructions in the ST10R163. This allows thesame functionality to be provided while decreas-ing the hardware required and decreasing decodecomplexity. In order to aid assembly program-ming, these instructions, familiar from other micro-

controllers, can be built in macros, thus providingthe same names.

Directly Substitutable Instructions are instruc-tions known from other microcontrollers that canbe replaced by the following instructions of theST10R163:

Modification of System Flags is performed us-ing bit set or bit clear instructions (BSET, BCLR ).All bit and word instructions can access the PSWregister, so no instructions like CLEAR CARRY orENABLE INTERRUPTS are required.

External Memory Data Access does not requirespecial instructions to load data pointers or explic-itly load and store external data. The ST10R163provides a Von-Neumann memory architectureand its on-chip hardware automatically detects ac-cesses to internal RAM, GPRs, and SFRs.

Substituted Instruction ST10R163 Instruction Function

CLR Rn AND Rn, #0h Clear register

CPLB Bit BMOVN Bit, Bit Complement bit

DEC Rn SUB Rn, #1h Decrement register

INC Rn ADD Rn, #1h Increment register

SWAPB Rn ROR Rn, #8h Swap bytes within word

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15 - SYSTEM PROGRAMMING (ST10R163)

15.2 MULTIPLICATION AND DIVISION

Multiplication and division of words and doublewords is provided through multiple cycle instruc-tions implementing a Booth algorithm. Each in-struction implicitly uses the 32-bit register MD(MDL = lower 16 bits, MDH = upper 16 bits). TheMDRIU flag (Multiply or Divide Register In Use) inregister MDC is set whenever either half of thisregister is written to or when a multiply/divide in-struction is started. It is cleared whenever theMDL register is read. Because an interrupt can beacknowledged before the contents of register MDare saved, this flag is required to alert interruptroutines, which require the use of the multiply/di-vide hardware, so they can preserve register MD.This register, however, only needs to be savedwhen an interrupt routine requires use of the MDregister and a previous task has not saved the cur-rent result. This flag is easily tested by the Jump-on-Bit instructions.

Multiplication or division is simply performed byspecifying the correct (signed or unsigned) ver-sion of the multiply or divide instruction. The resultis then stored in register MD. The overflow flag (V)is set if the result from a multiply or divide instruc-tion is greater than 16 bits. This flag can be usedto determine whether both word halves must betransferred from register MD. The high portion ofregister MD (MDH) must be moved into the regis-ter file or memory first, in order to ensure that theMDRIU flag reflects the correct state.

The following instruction sequence performs anunsigned 16 by 16-bit multiplication:

SAVE: JNB MDRIU, START

;Test if MD was in use.

SCXT MDC, #0010H

;Save and clear control;register leaving MDRIU set

;(only required for;interrupted multiply/divide ;in-structions)

BSET SAVED

;Indicate the save opera-tion

PUSH MDH

;Save previous MD con-tents...

PUSH MDL

;...on system stack

START: MULU R1, R2

;Multiply 16·16 unsigned,Sets MDRIU

JMPR cc_NV, COPYL

;Test for only 16-bit re-sult

MOV R3, MDH

;Move high portion of MD

COPYL: MOV R4, MDL

;Move low portion of MD,;Clears MDRIU

RESTORE: JNB SAVED, DONE

;Test if MD registerswere ;saved

POP MDL

;Restore registers

POP MDH

POP MDC

DONE: BCLR SAVED

;Multipl ication is com-pleted, ;program continues

The above save sequence and the restore se-quence after COPYL are only required if the cur-rent routine could have interrupted a previous rou-tine which contained a MUL or DIV instruction.Register MDC is also saved because it is possiblethat a previous routine’s Multiply or Divide instruc-tion was interrupted while in progress. In this casethe information about how to restart the instructionis contained in this register. Register MDC mustbe cleared to be correctly initialized for a subse-quent multiplication or division. The old MDC con-tents must be popped from the stack before theRETI instruction is executed.

For a division the user must first move the divi-dend into the MD register. If a 16/16-bit division isspecified, only the low portion of register MD mustbe loaded. The result is also stored into registerMD. The low portion (MDL) contains the integerresult of the division, while the high portion (MDH)contains the remainder.

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MULTIPLICATION AND DIVISION (Cont’d)

The following instruction sequence performs a 32by 16-bit division:

MOV MDH, R1

;Move dividend to MD register.;Sets MDRIU

MOV MDL, R2

;Move low portion to MD

DIV R3

;Divide 32/16 signed, R3 holds the;divisor

JMPR cc_V, ERROR

;Test for divide overflow

MOV R3, MDH

;Move remainder to R3

MOV R4, MDL

;Move integer result to R4. Clears;MDRIU

Whenever a multiply or divide instruction is inter-rupted while in progress, the address of the inter-rupted instruction is pushed onto the stack and theMULIP flag in the PSW of the interrupting routineis set. When the interrupt routine is exited with theRETI instruction, this bit is implicitly tested beforethe old PSW is popped from the stack. IfMULIP=’1’ the multiply/divide instruction is re-readfrom the location popped from the stack (returnaddress) and will be completed after the RETI in-struction has been executed.

Note: The MULIP flag is part of thecontext of theinterrupted task . When the interrupting routinedoes not return to the interrupted task (eg. sched-uler switches to another task) the MULIP flag mustbe set or cleared according to the context of thetask that is switched to.

15.3 BCD CALCULATIONS

No direct support for BCD calculations is providedin the ST10R163. BCD calculations are performedby converting BCD data to binary data, performingthe desired calculations using standard datatypes, and converting the result back to BCD data.Due to the enhanced performance of division in-structions binary data is quickly converted to BCDdata through division by 10d. Conversion fromBCD data to binary data is enhanced by multiplebit shift instructions. This provides similar perform-ance compared to instructions directly supportingBCD data types, while no additional hardware isrequired.

15.4 STACK OPERATIONS

The ST10R163 supports two types of stacks. Thesystem stack is used implicitly by the controllerand is located in the internal RAM. The user stackprovides stack access to the user in either the in-ternal or external memory. Both stack types growfrom high memory addresses to low memory ad-dresses.Internal System StackA system stack is provided to store return vectors,segment pointers, and processor status for proce-dures and interrupt routines. A system register,SP, points to the top of the stack. This pointer isdecremented when data is pushed onto the stack,and incremented when data is popped.The internal system stack can also be used totemporarily store data or pass it between subrou-tines or tasks. Instructions are provided to push orpop registers on/from the system stack. However,in most cases the register banking scheme pro-vides the best performance for passing data be-tween multiple tasks.Note : The system stack allows to store words on-ly. Bytes must either be converted to words or therespective other byte must be disregarded.Register SP can only be loaded with even byte ad-dresses (The LSB of SP is always ’0’).

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STACK OPERATIONS (Cont’d)

Detection of stack overflow/underflow is support-ed by two registers, STKOV (Stack OverflowPointer) and STKUN (Stack Underflow Pointer).Specific system traps (Stack Overflow trap, StackUnderflow trap) will be entered whenever the SPreaches either boundary specified in these regis-ters.The contents of the stack pointer are compared tothe contents of the overflow register, wheneverthe SP is DECREMENTED either by a CALL,PUSH or SUB instruction. An overflow trap will beentered, when the SP value is less than the valuein the stack overflow register.The contents of the stack pointer are compared tothe contents of the underflow register, wheneverthe SP is INCREMENTED either by a RET, POPor ADD instruction. An underflow trap will be en-tered, when the SP value is greater than the valuein the stack underflow register.Note: When a value is MOVED into the stackpointer, NO check against the overflow/underflowregisters is performed.In many cases the user will place a software resetinstruction (SRST) into the stack underflow andoverflow trap service routines. This is an easy ap-proach, which does not require special program-ming. However, this approach assumes that thedefined internal stack is sufficient for the currentsoftware and that exceeding its upper or lowerboundary represents a fatal error.It is also possible to use the stack underflow andstack overflow traps to cache portions of a largerexternal stack. Only the portion of the systemstack currently being used is placed into the inter-nal memory, thus allowing a greater portion of theinternal RAM to be used for program, data or reg-ister banking. This approach assumes no error butrequires a set of control routines (see below).

Circular (virtual) StackThis basic technique allows data to be pushed un-til the overflow boundary of the internal stack is

reached. At this point a portion of the stacked datamust be saved into external memory to createspace for further stack pushes. This is called“stack flushing”. When executing a number of re-turn or pop instructions, the upper boundary (sincethe stack empties upward to higher memory loca-tions) is reached. The entries that have been pre-viously saved in external memory must now be re-stored. This is called “stack filling”. Because pro-cedure call instructions do not continue to nest in-finitely and call and return instructions alternate,flushing and filling normally occurs very infre-quently. If this is not true for a given program envi-ronment, this technique should not be used be-cause of the overhead of flushing and filling.

The basic mechanism is the transformation ofthe addresses of a virtual stack area, controlledvia registers SP, STKOV and STKUN, to a definedphysical stack area within the internal RAM viahardware. This virtual stack area covers all possi-ble locations that SP can point to, ie. 00’F000hthrough 00’FFFEh. STKOV and STKUN acceptthe same 4 KByte address range.The size of the physical stack area within the inter-nal RAM that effectively is used for standard stackoperations is defined via bitfield STKSZ in registerSYSCON (see below).

The virtual stack addresses are transformed tophysical stack addresses by concatenating thesignificant bits of the stack pointer register SP(see table) with the complementary most signifi-cant bits of the upper limit of the physical stackarea (00’FBFEh). This transformation is done viahardware (see figure below).

The reset values (STKOV=FA00h,STKUN=FC00h, SP=FC00h, STKSZ=000b) mapthe virtual stack area directly to the physical stackarea and allow to use internal system stack with-out any changes, provided that the 256 word areais not exceeded.

<STKSZ>Stack Size(Words)

Internal RAM Addresses (Words)of Physical Stack

Significant Bits ofStack Pointer SP

0 0 0 b 256 00’FBFEh...00’FA00h (Default after Reset) SP.8...SP.0

0 0 1 b 128 00’FBFEh...00’FB00h SP.7...SP.0

0 1 0 b 64 00’FBFEh...00’FB80h SP.6...SP.0

0 1 1 b 32 00’FBFEh...00’FBC0h SP.5...SP.0

1 0 0 b --- Reserved. Do not use this combination. ---



1 1 1 b 1024 00’FDFEh...00’F600h (Note: No circular stack) SP.11...SP.0

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Figure 12-1. Physical Stack Address Generation

The following example demonstrates the circularstack mechanism which is also an effect of this vir-tual stack mapping: First, register R1 is pushedonto the lowest physical stack location accordingto the selected maximum stack size. With the fol-lowing instruction, register R2 will be pushed ontothe highest physical stack location although theSP is decremented by 2 as for the previous pushoperation.

MOV SP, #0F802h

;Set SP before last entry of;physical stack of 256 words

...

;(SP) = F802h: Physical stack;address = FA02h

PUSH R1

;(SP) = F800h: Physical stack;address = FA00h

PUSH R2

;(SP) = F7FEh: Physical stack;address = FBFEh

The effect of the address transformation is that thephysical stack addresses wrap around from theend of the defined area to its beginning. Whenflushing and filling the internal stack, this circular

stack mechanism only requires to move that por-tion of stack data which is really to be re-used (ie.the upper part of the defined stack area) instead ofthe whole stack area. Stack data that remain in thelower part of the internal stack need not be movedby the distance of the space being flushed or filled,as the stack pointer automatically wraps around tothe beginning of the freed part of the stack area.

Note : This circular stack technique is applicablefor stack sizes of 32 to 256 words (STKSZ = ‘000b’to ‘0116b’), it does not work with option STKSZ =‘111b’, which uses the complete internal RAM forsystem stack.

When a boundary is reached, the stack underflowor overflow trap is entered, where the user movesa predetermined portion of the internal stack to orfrom the external stack. The amount of data trans-ferred is determined by the average stack spacerequired by routines and the frequency of calls,traps, interrupts and returns. In most cases thiswill be approximately one quarter to one tenth thesize of the internal stack. Once the transfer iscomplete, the boundary pointers are updated toreflect the newly allocated space on the internalstack. Thus, the user is free to write code withoutconcern for the internal stack limits. Only the exe-cution time required by the trap routines affectsuser programs.

1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0

1 1 1 1 1 0 1 1 1 0 0 0 0 0 0 0

1 1 1 1 1 0 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0

1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0

1 1 1 1 1 0 1 1 0 1 1 1 1 1 1 0

1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0

FBFEh

FB80h

FB80h

FBFEh

FB7Eh

FBFEh

FBFEh

64 words 256 words

F800h 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0

FA00h

1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0

1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0

FBFEh

F7FEh

FBFEh

1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0

1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0

<SP>

<SP>

Phys.A.

Phys.A.

Stack Size

After PUSH After PUSH

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The following procedure initializes the controllerfor usage of the circular stack mechanism:

• Specify the size of the physical system stackarea within the internal RAM (bitfield STKSZ inregister SYSCON).

• Define two pointers, which specify the upper andlower boundary of the external stack. These val-ues are then tested in the stack underflow andoverflow trap routines when moving data.

• Set the stack overflow pointer (STKOV) to thelimit of the defined internal stack area plus sixwords (for the reserved space to store two inter-rupt entries).

The internal stack will now fill until the overflowpointer is reached. After entry into the overflowtrap procedure, the top of the stack will be copiedto the external memory. The internal pointers willthen be modified to reflect the newly allocatedspace. After exiting from the trap procedure, theinternal stack will wrap around to the top of the in-ternal stack, and continue to grow until the newvalue of the stack overflow pointer is reached.

When the underflow pointer is reached while thestack is emptied the bottom of stack is reloadedfrom the external memory and the internal point-ers are adjusted accordingly.

Linear Stack

The ST10R163 also offers a linear stack option(STKSZ = ‘111b’), where the system stack mayuse the complete internal RAM area. This allowsto provide a large system stack without requiringprocedures to handle data transfers for a circularstack. However, this method also leaves lessRAM space for variables or code. The RAM areathat may effectively be consumed by the systemstack is defined via the STKUN and STKOV point-ers. The underflow and overflow traps in this caseserve for fatal error detection only.

For the linear stack option all modifiable bits ofregister SP are used to access the physical stack.Although the stack pointer may cover addressesfrom 00’F000h up to 00’FFFEh the (physical) sys-tem stack must be located within the internal RAMand therefore may only use the address range00’F600h to 00’FDFEh. It is the user’s responsibil-ity to restrict the system stack to the internal RAMrange.

Note: Avoid stack accesses within address range00’F000h to 00’F5FEh (ESFR space and reserved

area) and within address range 00’FE00h and00’FFFEh (SFR space). Otherwise unpredictableresults will occur.

User Stacks

User stacks provide the ability to create task spe-cific data stacks and to off-load data from the sys-tem stack. The user may push both bytes andwords onto a user stack, but is responsible for us-ing the appropriate instructions when poppingdata from the specific user stack. No hardware de-tection of overflow or underflow of a user stack isprovided. The following addressing modes allowimplementation of user stacks:

[– Rw], Rb or [– Rw], Rw : Pre-decrement IndirectAddressing.Used to push one byte or word onto a user stack.This mode is only available for MOV instructionsand can specify any GPR as the user stack point-er.

Rb, [Rw+] or Rw, [Rw+] : Post-increment IndexRegister Indirect Addressing.Used to pop one byte or word from a user stack.This mode is available to most instructions, butonly GPRs R0-R3 can be specified as the userstack pointer.

Rb, [Rw+] or Rw, [Rw+] : Post-increment IndirectAddressing.Used to pop one byte or word from a user stack.This mode is only available for MOV instructionsand can specify any GPR as the user stack point-er.

15.5 REGISTER BANKING

Register banking provides the user with an ex-tremely fast method to switch user context. A sin-gle machine cycle instruction saves the old bankand enters a new register bank. Each registerbank may assign up to 16 registers. Each registerbank should be allocated during coding based onthe needs of each task. Once the internal memoryhas been partitioned into a register bank space,internal stack space and a global internal memoryarea, each bank pointer is then assigned. Thus,upon entry into a new task, the appropriate bankpointer is used as the operand for the SCXT(switch context) instruction. Upon exit from a taska simple POP instruction to the context pointer(CP) restores the previous task’s register bank.

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15.6 PROCEDURE CALL ENTRY AND EXIT

To support modular programming a proceduremechanism is provided to allow coding of fre-quently used portions of code into subroutines.The CALL and RET instructions store and restorethe value of the instruction pointer (IP) on the sys-tem stack before and after a subroutine is execut-ed.

Note: Procedures may be called conditionally withinstructions CALLA or CALLI, or be called uncon-ditionally using instructions CALLR or CALLS.

Any data pushed onto the system stack during ex-ecution of the subroutine must be popped beforethe RET instruction is executed.

Passing Parameters on the System Stack

Parameters may be passed via the system stackthrough PUSH instructions before the subroutineis called, and POP instructions during execution ofthe subroutine. Base plus offset indirect address-ing also permits access to parameters withoutpopping these parameters from the stack duringexecution of the subroutine. Indirect addressingprovides a mechanism of accessing data refer-enced by data pointers, which are passed to thesubroutine.

In addition, two instructions have been implement-ed to allow one parameter to be passed on thesystem stack without additional software over-head.

The PCALL (push and call) instruction first pushesthe ’reg’ operand and the IP contents onto the sys-tem stack and then passes control to the subrou-tine specified by the ’caddr’ operand.

When exiting from the subroutine, the RETP (re-turn and pop) instruction first pops the IP and then

the ’reg’ operand from the system stack and re-turns to the calling program.Cross Segment Subroutine CallsCalls to subroutines in different segments requirethe use of the CALLS (call inter-segment subrou-tine) instruction. This instruction preserves boththe CSP (code segment pointer) and IP on thesystem stack.Upon return from the subroutine, a RETS (returnfrom inter-segment subroutine) instruction mustbe used to restore both the CSP and IP. This en-sures that the next instruction after the CALLS in-struction is fetched from the correct segment.Note : It is possible to use CALLS within the samesegment, but still two words of the stack are usedto store both the IP and CSP.Providing Local Registers for SubroutinesFor subroutines which require local storage, thefollowing methods are provided:Alternate Bank of Registers: Upon entry into asubroutine, it is possible to specify a new set of lo-cal registers by executing the SCXT (switch con-text) instruction. This mechanism does not providea method to recursively call a subroutine.Saving and Restoring of Registers: To providelocal registers, the contents of the registers whichare required for use by the subroutine can bepushed onto the stack and the previous values bepopped before returning to the calling routine. Thisis the most common technique used today and itdoes provide a mechanism to support recursiveprocedures. This method, however, requires twomachine cycles per register stored on the systemstack (one cycle to PUSH the register, and one toPOP the register).

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PROCEDURE CALL ENTRY AND EXIT (Cont’d)Use of the System Stack for LocalRegisters: Itis possible to use the SP and CP to set up localsubroutine register frames. This allows subrou-tines to dynamically allocate local variables asneeded within two machine cycles. A local frameis allocated by simply subtracting the number ofrequired local registers from the SP, and thenmoving the value of the new SP to the CP.

This operation is supported through the SCXT(switch context) instruction with the addressingmode ’reg, mem’. Using this instruction saves theold contents of the CP on the system stack andmoves the value of the SP into CP (see examplebelow). Each local register is then accessed as if itwas a normal register. Upon exit from the subrou-tine, first the old CP must be restored by popping itfrom the stack and then the number of used localregisters must be added to the SP to restore theallocated local space back to the system stack.

Note : The system stack is growing downwards,while the register bank is growing upwards.The software to provide the local register bank forthe example above is very compact:After entering the subroutine:

SUB SP, #10

;Free 5 words in the current system;stack

SCXT CP, SP

;Set the new register bank pointer

Before exiting the subroutine:POP CP

;Restore the old register bank

ADD SP, #10

;Release the 5 word of the current;system stack

Figure 12-2. Local Registers

OldStackArea

NewlyAllocatedRegister

Bank

R4R3R2R1R0

Old CP Contents

Old SP

New SPNew CP

NewStackArea

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15.7 TABLE SEARCHING

A number of features have been included to de-crease the execution time required to search ta-bles. First, branch delays are eliminated by thebranch target cache after the first iteration of theloop. Second, in non-sequentially searched ta-bles, the enhanced performance of the ALU al-lows more complicated hash algorithms to beprocessed to obtain better table distribution. Forsequentially searched tables, the auto-incrementindirect addressing mode and the E (end of table)flag stored in the PSW decrease the number ofoverhead instructions executed in the loop.

The two examples below illustrate searching or-dered tables and non-ordered tables, respectively:

MOV R0, #BASE

;Move table base into R0

LOOP: CMPR1, [R0+

;Compare target to table entry

JMPR cc_SGT, LOO

;Test whether target has not been;found

Note: The last entry in the table must be greaterthan the largest possible target.

MOV R0, #BASE

;Move table base into R0

LOOP: CMPR1, [R0+]

;Compare target to table entry

JMPR cc_NET, LOO

;Test whether target is not found;AND the end of table...

;...has not been reached.

Note: The last entry in the table must be equal tothe lowest signed integer (8000h).

15.8 PERIPHERAL CONTROL ANDINTERFACE

All communication between peripherals and theCPU is performed either by PEC transfers to andfrom internal memory, or by explicitly addressingthe SFRs associated with the specific peripherals.After resetting the ST10R163 all peripherals (ex-cept the watchdog timer) are disabled and initial-ized to default values. A desired configuration of aspecific peripheral is programmed using MOV in-structions of either constants or memory values tospecific SFRs. Specific control flags may also bealtered via bit instructions.Once in operation, the peripheral operates auton-omously until an end condition is reached at whichtime it requests a PEC transfer or requests CPU

servicing through an interrupt routine. Informationmay also be polled from peripherals through readaccesses to SFRs or bit operations includingbranch tests on specific control bits in SFRs. Toensure proper allocation of peripherals amongmultiple tasks, a portion of the internal memoryhas been made bit addressable to allow user sem-aphores. Instructions have also been provided tolock out tasks via software by setting or clearinguser specific bits and conditionally branchingbased on these specific bits.

It is recommended that bit fields in control SFRsare updated using the BFLDH and BFLDL instruc-tions or a MOV instruction to avoid undesired in-termediate modes of operation which can occur,when BCLR/BSET or AND/OR instruction se-quences are used.

15.9 FLOATING POINT SUPPORT

All floating point operations are performed usingsoftware. Standard multiple precision instructionsare used to perform calculations on data typesthat exceed the size of the ALU. Multiple bit rotateand logic instructions allow easy masking and ex-tracting of portions of floating point numbers.

To decrease the time required to perform floatingpoint operations, two hardware features havebeen implemented in the CPU core. First, the PRI-OR instruction aids in normalizing floating pointnumbers by indicating the position of the first setbit in a GPR. This result can the be used to rotatethe floating point result accordingly. The secondfeature aids in properly rounding the result of nor-malized floating point numbers through the over-flow (V) flag in the PSW. This flag is set when aone is shifted out of the carry bit during shift rightoperations. The overflow flag and the carry flagare then used to round the floating point resultbased on the desired rounding algorithm.

15.10 TRAP/INTERRUPT ENTRY AND EXIT

Interrupt routines are entered when a requestinginterrupt has a priority higher than the current CPUpriority level. Traps are entered regardless of thecurrent CPU priority. When either a trap or inter-rupt routine is entered, the state of the machine ispreserved on the system stack and a branch to theappropriate trap/interrupt vector is made.

All trap and interrupt routines require the use ofthe RETI (return from interrupt) instruction to exitfrom the called routine. This instruction restoresthe system state from the system stack and thenbranches back to the location where the trap or in-terrupt occurred.

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15.11 UNSEPARABLE INSTRUCTIONSEQUENCES

The instructions of the ST10R163 are very effi-cient (most instructions execute in one machinecycle) and even the multiplication and division areinterruptable in order to minimize the response la-tency to interrupt requests (internal and external).In many microcontroller applications this is vital.

Some special occasions, however, require certaincode sequences (eg. semaphore handling) to beuninterruptable to function properly. This can beprovided by inhibiting interrupts during the respec-tive code sequence by disabling and enablingthem before and after the sequence. The neces-sary overhead may be reduced by means of theATOMIC instruction, which allows to lock 1...4 in-structions to an unseparable code sequence, dur-ing which the interrupt system (standard interruptsand PEC requests) and Class A Traps (NMI,stack overflow/underflow) are disabled. AClass BTrap (illegal opcode, illegal bus access, etc.),however, will interrupt the atomic sequence, sinceit indicates a severe hardware problem. The inter-rupt inhibit caused by an ATOMIC instruction getsactive immediately, ie. no other instruction will en-ter the pipeline except the one that follows theATOMIC instruction, and no interrupt request willbe serviced in between. All instructions requiringmultiple cycles or hold states are regarded as oneinstruction in this sense (eg. MUL is one instruc-tion). Any instruction type can be used within anunseparable code sequence.

EXAMPLE:

ATOMIC #3

The following 3 instructions arelocked (No NOP required)

MOV R0, #1234h

;Instruction 1 (no other instr.;enters the pipeline!)

MOV R1, #5678h

;Instruction 2

MUL R0, R1

;Instruction 3: MUL regarded as one;instruction

MOV R2, MDL

;This instruction is out of the;scope of the ATOMIC instruction;sequence

15.12 OVERRIDING THE DPP ADDRESSINGMECHANISM

The standard mechanism to access data locationsuses one of the four data page pointers (DPPx),which selects a 16 KByte data page, and a 14-bitoffset within this data page. The four DPPs allowimmediate access to up to 64 KByte of data. In ap-plications with big data arrays, especially in HLLapplications using large memory models, this mayrequire frequent reloading of the DPPs, even forsingle accesses.

The EXTP (extend page) instruction allows toswitch to an arbitrary data page for 1...4 instruc-tions without having to change the current DPPs.

EXAMPLE:

EXTP R15, #1

;The override page number is stored;in R15

MOV R0, [R14]

;The (14-bit) page offset is stored;in R14

MOV R1, [R13]

;This instruction uses the standard;DPP scheme!

The EXTS (extend segment) instruction allowsto switch to a 64 KByte segment oriented data ac-cess scheme for 1...4 instructions without havingto change the current DPPs. In this case all 16 bitsof the operand address are used as segment off-set, with the segment taken from the EXTS in-struction. This greatly simplifies address calcula-tion with continuous data like huge arrays in “C”.

EXAMPLE

EXTS #15, #1

;The override seg. is #15;(0F’0000h...0F’FFFFh)

MOV R0, [R14]

;The (16-bit) segment offset is;stored in R14

MOV R1, [R13]

;This instruction uses the standard;DPP scheme!

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OVERRIDING THE DPP ADDRESSING MECHANISM (Cont’d)Note: Instructions EXTP and EXTS inhibit inter-rupts the same way as ATOMIC.Short Addressing in the Extended SFR (ESFR)SpaceThe short addressing modes of the ST10R163(REG or BITOFF) implicitly access the SFRspace. The additional ESFR space would have tobe accessed via long addressing modes (MEM or[Rw]). The EXTR (extend register) instruction al-lows to redirect accesses in short addressingmodes to the ESFR space for 1...4 instructions, sothe additional registers can be accessed this way,too.The EXTPR and EXTSR instructions combine theDPP override mechanism with the redirection tothe ESFR space using a single instruction.Note: Instructions EXTR, EXTPR and EXTSR in-hibit interrupts the same way as ATOMIC.The switching to the ESFR area and data page

overriding is checked by the development tools orhandled automatically.

Nested Locked Sequences

Each of the described extension instruction andthe ATOMIC instruction starts an internal “exten-sion counter” counting the effected instructions.When another extension or ATOMIC instruction iscontained in the current locked sequence thiscounter is restarted with the value of the new in-struction. This allows to construct locked sequenc-es longer than 4 instructions.

Note:

– Interrupt latencies may be increased whenusing locked code sequences.

– PEC requests are not serviced during idlemode, if the IDLE instruction is part of alocked sequence.

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Notes :

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ST10R163User Manual

16 - REGISTER SET

This section summarizes all registers, which areimplemented in the ST10R163 and explains thedescription format which is used in the chaptersdescribing the function and layout of the SFRs.For easy reference the registers are ordered ac-cording to two different keys (except for GPRs):• Ordered by address, to check which register agiven address references,• Ordered by register name, to find the location ofa specific register.Register Description FormatIn the respective chapters the function and the lay-out of the SFRs is described in a specific formatwhich provides a number of details about the de-

scribed special function register. The example be-low shows how to interpret these details.A word register looks like this:Elements:REG_NAMEName of this registerA16 / A8Long 16-bit address / Short 8-bit address

E/SFRRegister space (SFR or ESFR)(* *) * *Register contents after reset

0/1: defined value, X: undefined, U: un-changed (undefined after power up)hwbitBits that are set/cleared by hardware aremarked with a shaded access box

REG_NAME (A16h / A8h) E/SFR Reset Value: * * * *h

A byte register looks like this:

REG_NAME (A16h / A8h) E/SFR Reset Value: - - * *h

Bit Function

bit(field)nameExplanation of bit(field)name

Description of the functions controlled by this bit(field).

5 4 3 2 1 011 10 9 8 7 615 14 13 12

rw rw- w rw r rw rw- - - -

res.res.res.res.res.writeonly

readonly bitfield bitfield

hwbit

stdbit

hwbit

5 4 3 2 1 011 10 9 8 7 615 14 13 12

rw rw- - - - rw rw- - - -

bitfieldbitfieldstdbit

hwbit

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16 - REGISTER SET (ST10R163)

16.1 CPU GENERAL PURPOSE REGISTERS (GPRS)

The GPRs form the register bank that the CPUworks with. This register bank may be located an-ywhere within the internal RAM via the Context

Pointer (CP). Due to the addressing mechanism,GPR banks can only reside within the internalRAM. All GPRs are bit-addressable.

NamePhysicalAddress

8-BitAddress

DescriptionResetValue

R0 (CP) + 0 F0h CPU General Purpose (Word) Register R0 UUUUh










R10 (CP) + 20 FAh CPU General Purpose (Word) Register R10 UUUUh

R11 (CP) + 22 FBh CPU General Purpose (Word) Register R11 UUUUh

R12 (CP) + 24 FCh CPU General Purpose (Word) Register R12 UUUUh

R13 (CP) + 26 FDh CPU General Purpose (Word) Register R13 UUUUh

R14 (CP) + 28 FEh CPU General Purpose (Word) Register R14 UUUUh

R15 (CP) + 30 FFh CPU General Purpose (Word) Register R15 UUUUh

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CPU GENERAL PURPOSE REGISTERS (GPRS)(Cont’d)The first 8 GPRs (R7...R0) may also be accessedbytewise. Other than with SFRs, writing to a GPRbyte does not affect the other byte of the respec-

tive GPR.The respective halves of the byte-accessible reg-isters receive special names:

NamePhysicalAddress

8-BitAddress


RL0 (CP) + 0 F0h CPU General Purpose (Byte) Register RL0 UUh

RH0 (CP) + 1 F1h CPU General Purpose (Byte) Register Rh0 UUh


RH1 (CP) + 3 F3h CPU General Purpose (Byte) Register RH1 UUh







RL5 (CP) + 10 FAh CPU General Purpose (Byte) Register RL5 UUh

RH5 (CP) + 11 FBh CPU General Purpose (Byte) Register RH5 UUh

RL6 (CP) + 12 FCh CPU General Purpose (Byte) Register RL6 UUh

RH6 (CP) + 13 FDh CPU General Purpose (Byte) Register RH6 UUh

RL7 (CP) + 14 FEh CPU General Purpose (Byte) Register RL7 UUh

RH7 (CP) + 14 FFh CPU General Purpose (Byte) Register RH7 UUh

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16.2 SPECIAL FUNCTION REGISTERS ORDERED BY NAME

The following table lists all SFRs which are imple-mented in the ST10R163 in alphabetical order.Bit-addressable SFRs are marked with the letter

“b” in column “Name”. SFRs within the ExtendedSFR-Space (ESFRs) are marked with the letter“E” in column “Physical Address”.

NamePhysicalAddress

8-BitAddress


ADDRSEL1 FE18h 0Ch Address Select Register 1 0000h

ADDRSEL2 FE1Ah 0Dh Address Select Register 2 0000h

ADDRSEL3 FE1Ch 0Eh Address Select Register 3 0000h

ADDRSEL4 FE1Eh 0Fh Address Select Register 4 0000h

BUSCON0 b FF0Ch 86h Bus Configuration Register 0 0000h

BUSCON1 b FF14h 8Ah Bus Configuration Register 1 0000h

BUSCON2 b FF16h 8Bh Bus Configuration Register 2 0000h

BUSCON3 b FF18h 8Ch Bus Configuration Register 3 0000h

BUSCON4 b FF1Ah 8Dh Bus Configuration Register 4 0000h

CAPREL FE4Ah 25h GPT2 Capture/Reload Register 0000h

CC8IC b FF88h C4h External Interrupt 0 Control Register 0000h

CC9IC b FF8Ah C5h External Interrupt 1 Control Register 0000h

CC10IC b FF8Ch C6h External Interrupt 2 Control Register 0000h

CC11IC b FF8Eh C7h External Interrupt 3 Control Register 0000h



CC14IC b FF94h CAh External Interrupt 6 Control Register 0000h

CC15IC b FF96h CBh External Interrupt 7 Control Register 0000h

CP FE10h 08h CPU Context Pointer Register FC00h

CRIC b FF6Ah B5h GPT2 CAPREL Interrupt Control Register 0000h

CSP FE08h 04hCPU Code Segment Pointer Register(8 bits, not directly writeable)

0000h

DP0L b F100h E 80h P0L Direction Control Register 00h

DP0H b F102h E 81h P0H Direction Control Register 00h



DP2 b FFC2h E1h Port 2 Direction Control Register 0000h


DP4 b FFCAh E5h Port 4 Direction Control Register 00h

DP6 b FFCEh E7h Port 6 Direction Control Register 00h

DPP0 FE00h 00h CPU Data Page Pointer 0 Register (10 bits) 0000h




EXICON b F1C0h E E0h External Interrupt Control Register 0000h

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MDC b FF0Eh 87h CPU Multiply Divide Control Register 0000h

MDH FE0Ch 06h CPU Multiply Divide Register – High Word 0000h

MDL FE0Eh 07h CPU Multiply Divide Register – Low Word 0000h

ODP2 b F1C2h E E1h Port 2 Open Drain Control Register 0000h


ODP6 b F1CEh E E7h Port 6 Open Drain Control Register 00h

ONES b FF1Eh 8Fh Constant Value 1’s Register (read only) FFFFh

P0L b FF00h 80h Port 0 Low Register (Lower half of PORT0) 00h

P0H b FF02h 81h Port 0 High Register (Upper half of PORT0) 00h



P2 b FFC0h E0h Port 2 Register 0000h


P4 b FFC8h E4h Port 4 Register (8 bits) 00h

P5 b FFA2h D1h Port 5 Register (read only) XXXXh

P6 b FFCCh E6h Port 6 Register (8 bits) 00h

PECC0 FEC0h 60h PEC Channel 0 Control Register 0000h





PECC5 FECAh 65h PEC Channel 5 Control Register 0000h

PECC6 FECCh 66h PEC Channel 6 Control Register 0000h

PECC7 FECEh 67h PEC Channel 7 Control Register 0000h

PSW b FF10h 88h CPU Program Status Word 0000h

RP0H b F108h E 84h System Startup Configuration Register (Rd. only) XXh

S0BG FEB4h 5Ah Serial Channel 0 Baud Rate Generator Reload Register 0000h

S0CON b FFB0h D8h Serial Channel 0 Control Register 0000h

S0EIC b FF70h B8h Serial Channel 0 Error Interrupt Control Register 0000h

S0RBUF FEB2h 59hSerial Channel 0 Receive Buffer Register(read only)

XXXXh

S0RIC b FF6Eh B7h Serial Channel 0 Receive Interrupt Control Register 0000h

S0TBIC b F19Ch E CEh Serial Channel 0 Transmit Buffer Interrupt Control Register 0000h

S0TBUF FEB0h 58hSerial Channel 0 Transmit Buffer Register(write only)

0000h

S0TIC b FF6Ch B6h Serial Channel 0 Transmit Interrupt Control Register 0000h

SP FE12h 09h CPU System Stack Pointer Register FC00h

STKOV FE14h 0Ah CPU Stack Overflow Pointer Register FA00h

STKUN FE16h 0Bh CPU Stack Underflow Pointer Register FC00h

Name PhysicalAddress

8-BitAddress

Description ResetValue

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Note:1) The system configuration is selected during reset.2) Bit WDTR indicates a watchdog timer triggered reset.

SYSCON b FF12h 89h CPU System Configuration Register 0XX0h1)

T2 FE40h 20h GPT1 Timer 2 Register 0000h

T2CON b FF40h A0h GPT1 Timer 2 Control Register 0000h

T2IC b FF60h B0h GPT1 Timer 2 Interrupt Control Register 0000h













TFR b FFACh D6h Trap Flag Register 0000h

WDT FEAEh 57h Watchdog Timer Register (read only) 0000h

WDTCON b FFAEh D7h Watchdog Timer Control Register 000Xh2)

XP1IC b F18Eh E C7h X-Peripheral 1 Interrupt Control Register 0000h

XP3IC b F19Eh E CFh X-Peripheral 3 Interrupt Control RegisterT 0000h

ZEROS b FF1Ch 8Eh Constant Value 0’s Register (read only) 0000h


8-BitAddress


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16.3 REGISTERS ORDERED BY ADDRESS

The following table lists all SFRs which are imple-mented in the ST10R163 ordered by their physicaladdress. Bit-addressable SFRs are marked with

the letter “b” in column “Name”. SFRs within theExtended SFR-Space (ESFRs) are marked withthe letter “E” in column “Physical Address”.

NamePhysicalAddress

8-BitAddress



DPOH b F102h E 81h P0H Direction Control Register 00h



RP0H b F108h E 84h System Startup Configuration Register (Rd. only) XXh

XP1I b F18Eh E C7h X-Peripheral 1 Interrupt Control Register 0000h

S0TBIC b F19Ch E CEh Serial Channel 0 Transmit Buffer Interrupt Control Register 0000h

XP3IC b F19Eh E CFh X-Peripheral 3 Interrupt Control Register 0000h

EXICON b F1C0h E E0h External Interrupt Control Register 0000h


ODP b F1C6h E E3h Port 3 Open Drain Control Register 0000h

ODP6 b F1CEh E E7h Port 6 Open Drain Control Register 00h





CSP FE08h 04hCPU Code Segment Pointer Register(8 bits, not directly writeable)

0000h

MDH FE0Ch 06h CPU Multiply Divide Register – High Word 0000h

MDL FE0Eh 07h CPU Multiply Divide Register – Low Word 0000h

CP FE10h 08h CPU Context Pointer Register FC00h

SP FE12h 09h CPU System Stack Pointer Register FC00h

STKOV FE14h 0Ah CPU Stack Overflow Pointer Register FA00h

STKUN FE16h 0Bh CPU Stack Underflow Pointer Register FC00h

ADDRSEL1 FE18h 0Ch Address Select Register 1 0000h

ADDRSEL2 FE1Ah 0Dh Address Select Register 2 0000h

ADDRSEL3 FE1Ch 0Eh Address Select Register 3 0000h

ADDRSEL4 FE1Eh 0Fh Address Select Register 4 0000h






CAPREL FE4Ah 25h GPT2 Capture/Reload Register 0000h

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WDT FEAEh 57h Watchdog Timer Register (read only) 0000h

S0TBUF FEB0h 58hSerial Channel 0 Transmit Buffer Register(write only)

0000h

S0RBUF FEB2h 59hSerial Channel 0 Receive Buffer Register(read only)

XXXXh

S0BG FEB4h 5Ah Serial Channel 0 Baud Rate Generator Reload Register 0000h






PECC5 FECAh 65h PEC Channel 5 Control Register 0000h

PECC6 FECCh 66h PEC Channel 6 Control Register 0000h

PECC7 FECEh 67h PEC Channel 7 Control Register 0000h


POH b FF02h 81h Port 0 High Register (Upper half of PORT0) 00h



BUSCON0 b FF0Ch 86h Bus Configuration Register 0 0000h

MDC b FF0Eh 87h CPU Multiply Divide Control Register 0000h

PSW b FF10h 88h CPU Program Status Word 0000h

SYSCON b FF12h 89h CPU System Configuration Register 0XX0h1)

BUSCON1 b FF14h 8Ah Bus Configuration Register 1 0000h

BUSCON2 b FF16h 8Bh Bus Configuration Register 2 0000h

BUSCON3 b FF18h 8Ch Bus Configuration Register 3 0000h

BUSCON4 b FF1Ah 8Dh Bus Configuration Register 4 0000h

ZEROS b FF1Ch 8Eh Constant Value 0’s Register (read only) 0000h

ONES b FF1Eh 8Fh Constant Value 1’s Register (read only) FFFFh











CRIC b FF6Ah B5h GPT2 CAPREL Interrupt Control Register 0000h


8-BitAddress


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Note:1) The system configuration is selected during reset.2) Bit WDTR indicates a watchdog timer triggered reset.

S0TIC b FF6Ch B6h Serial Channel 0 Transmit Interrupt Control Register 0000h

S0RIC b FF6Eh B7h Serial Channel 0 Receive Interrupt Control Register 0000h

S0EIC b FF70h B8h Serial Channel 0 Error Interrupt Control Register 0000h


CC9IC b FF8Ah C5h External Interrupt 1 Control Register 0000h

CC10IC b FF8Ch C6h External Interrupt 2 Control Register 0000h

CC11IC b FF8Eh C7h External Interrupt 3 Control Register 0000h



CC14IC b FF94h CAh External Interrupt 6 Control Register 0000h

CC15IC b FF96h CBh External Interrupt 7 Control Register 0000h

P5 b FFA2h D1h Port 5 Register (read only) XXXXh

TFR b FFACh D6h Trap Flag Register 0000h

WDTCON b FFAEh D7h Watchdog Timer Control Register 000Xh2)

S0CON b FFB0h D8h Serial Channel 0 Control Register 0000h





P4 b FFC8h E4h Port 4 Register (8 bits) 00h

DP4 b FFCAh E5h Port 4 Direction Control Register 00h

P6 b FFCCh E6h Port 6 Register (8 bits) 00h

DP6 b FFCEh E7h Port 6 Direction Control Register 00h


8-BitAddress


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Notes:

Figure 13-1

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ST10R163User Manual

17 - INSTRUCTION SET SUMMARY

This chapter briefly summarizes the ST10R163’sinstructions ordered by instruction classes. Thisprovides a basic understanding of theST10R163’s instruction set, the power and versa-tility of the instructions and their general usage.

A detailed description of each single instruction,including its operand data type, condition flag set-tings, addressing modes, length (number of bytes)and object code format is provided in the “In-struction Set Manual” for the ST10 Family. Thismanual also provides tables ordering the instruc-

tions according to various criteria, to allow quickreferences.Summary of Instruction ClassesGrouping the various instruction into classes aidsin identifying similar instructions (eg. SHR, ROR)and variations of certain instructions (eg. ADD,ADDB). This provides an easy access to the pos-sibilities and the power of the instructions of theST10R163.Note : The used mnemonics refer to the detailleddescription.

Arithmetic Instructions

• Addition of two words or bytes: ADD ADDB

• Addition with Carry of two words or bytes: ADDC ADDCB

• Subtraction of two words or bytes: SUB SUBB

• Subtraction with Carry of two words or bytes: SUBC SUBCB

• 16*16 bit signed or unsigned multiplication: MUL MULU

• 16/16 bit signed or unsigned division: DIV DIVU

• 32/16 bit signed or unsigned division: DIVL DIVLU

• 1’s complement of a word or byte: CPL CPLB

• 2’s complement (negation) of a word or byte: NEG NEGB

Logical Instructions

• Bitwise ANDing of two words or bytes: AND ANDB

• Bitwise ORing of two words or bytes: OR ORB

• Bitwise XORing of two words or bytes: XOR XORB

Compare and Loop Control Instructions

• Comparison of two words or bytes: CMP CMPB

• Comparison of two words with post-incrementby either 1 or 2: CMPI1 CMPI2

• Comparison of two words with post-decrementby either 1 or 2: CMPD1 CMPD2

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17 - INSTRUCTION SET SUMMARY (ST10R163)

Boolean Bit Manipulation Instructions

• Manipulation of a maskable bit fieldin either the high or the low byte of a word: BFLDH BFLDL

• Setting a single bit (to ‘1’): BSET

• Clearing a single bit (to ‘0’): BCLR

• Movement of a single bit: BMOV

• Movement of a negated bit: BMOVN

• ANDing of two bits: BAND

• ORing of two bits: BOR

• XORing of two bits: BXOR

• Comparison of two bits: BCMP

Shift and Rotate Instructions

• Shifting right of a word: SHR

• Shifting left of a word: SHL

• Rotating right of a word: ROR

• Rotating left of a word: ROL

• Arithmetic shifting right of a word (sign bit shifting): ASHR

Prioritize Instruction

• Determination of the number of shift cycles requiredto normalize a word operand (floating point support): PRIOR

Data Movement Instructions

• Standard data movement of a word or byte: MOV MOVB

• Data movement of a byte to a word locationwith either sign or zero byte extension: MOVBS MOVBZ

Note: The data movement instructions can be used with a big number of different addressing modes in-cluding indirect addressing and automatic pointer in-/decrementing.

System Stack Instructions

• Pushing of a word onto the system stack: PUSH

• Popping of a word from the system stack: POP

• Saving of a word on the system stack,and then updating the old word with a new value(provided for register bank switching): SCXT

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Jump Instructions

• Conditional jumping to an either absolutely,indirectly, or relatively addressed target instructionwithin the current code segment: JMPA JMPI JMPR

• Unconditional jumping to an absolutely addressedtarget instruction within any code segment: JMPS

• Conditional jumping to a relatively addressedtarget instruction within the current code segmentdepending on the state of a selectable bit: JB JNB

• Conditional jumping to a relatively addressedtarget instruction within the current code segmentdepending on the state of a selectable bitwith a post-inversion of the tested bitin case of jump taken (semaphore support): JBC JNBS

Call Instructions

• Conditional calling of an either absolutelyor indirectly addressed subroutine withinthe current code segment: CALLA CALLI

• Unconditional calling of a relatively addressedsubroutine within the current code segment: CALLR

• Unconditional calling of an absolutely addressedsubroutine within any code segment: CALLS

• Unconditional calling of an absolutely addressedsubroutine within the current code segment plusan additional pushing of a selectable register ontothe system stack: PCALL

• Unconditional branching to the interrupt ortrap vector jump table in code segment 0: TRAP

Return Instructions

• Returning from a subroutinewithin the current code segment: RET

• Returning from a subroutinewithin any code segment: RETS

• Returning from a subroutine within the currentcode segment plus an additional popping of aselectable register from the system stack: RETP

• Returning from an interrupt service routine: RETI

229

4/4


System Control Instructions

• Resetting the ST10R163 via software: SRST

• Entering the Idle mode: IDLE

• Entering the Power Down mode: PWRDN

• Servicing the Watchdog Timer: SRVWDT

• Disabling the Watchdog Timer: DISWDT

• Signifying the end of the initialization routine(pulls pin RSTOUT high, and disables the effect ofany later execution of a DISWDT instruction): EINIT

Miscellaneous

• Null operation which requires 2 bytes ofstorage and the minimum time for execution: NOP

• Definition of an unseparable instruction sequence: ATOMIC

• Switch ‘reg’, ‘bitoff’ and ‘bitaddr’ addressing modesto the Extended SFR space: EXTR

• Override the DPP addressing schemeusing a specific data page instead of the DPPs,and optionally switch to ESFR space: EXTP EXTPR

• Override the DPP addressing schemeusing a specific segment instead of the DPPs,and optionally switch to ESFR space: EXTS EXTSR

Figure 14-1

Note: The ATOMIC and EXT* instructions provide support for uninterruptable code sequences eg. forsemaphore operations. They also support data addressing beyond the limits of the current DPPs(except ATOMIC), which is advantageous for bigger memory models in high level languages. Referto chapter “System Programming” for examples.

Protected Instructions

Some instructions of the ST10R163 which arecritical for the functionality of the controller areimplemented as so-called Protected Instructions.These protected instructions use the maximuminstruction format of 32 bits for decoding, while theregular instructions only use a part of it (eg. thelower 8 bits) with the other bits providing additionalinformation like involved registers. Decoding all 32bits of a protected doubleword instruction

increases the security in cases of data distortionduring instruction fetching. Critical operations likea software reset are therefore only executed if thecomplete instruction is decoded without an error.This enhances the safety and reliability of amicrocontroller system.

230

February 1996 1/2


ST10R163User Manual

18 - DEVICE SPECIFICATION

The device specification describes the electricalparameters of the device. It lists DC characteris-tics like input, output or supply voltages or cur-rents, and AC characteristics like timing character-istics and requirements.

Other than the architecture, the instruction set orthe basic functions of the ST10R163 core and itsperipherals, these DC and AC characteristics aresubject to changes due to device improvements orspecific derivatives of the standard device.

Therefore these characteristics are not con-tained in this manual, but rather provided in a

separate Data Sheet, which can be updatedmore frequently.Please refer to the current version of the ST10R163Data Sheet for all electrical parameters.Note : In any case the specific characteristics of adevice should be verified, before a new design isstarted. This ensures that the used information isup to date.The following figure shows the pin diagram of theST10R163. It shows the location of the differentsupply and IO pins. A detailed description of all thepins is also found in the Data Sheet.

231

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18 - DEVICE SPECIFICATION (ST10R163)

Figure 15-1. Pin Description of the ST10R163, TQFP-100 Package

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for theconsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. Nolicense is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specificationsmentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previouslysupplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systemswithout the express written approval of SGS-THOMSON Microelectronics.

1996 SGS-THOMSON Microelectronics - All rights reserved.

Purchase of I2C Components by SGS-THOMSON Microelectronics conveys a license under the Philips I2C Patent. Rights to use thesecomponents in an I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips.

SGS-THOMSON Microelectronics Group of CompaniesAustralia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands

Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.

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232

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