17.Three-Phase Hybrid Multilevel Inverter

Copyright (c) 2011 IEEE. Personal use is permitted. For any other purposes, Permission must be obtained from the IEEE by emailing [email protected].

This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication.TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. ??, NO. ??, MONTH 2011. 1

Three-Phase Hybrid Multilevel InverterBased on Half-Bridge Modules

Alessandro L. Batschauer, Samir A. Mussa and Marcelo L. Heldwein Santa Catarina State University - DEE/NPEE - www.npee.joinville.udesc.br - Phone:+55-47-4009-7844

Federal University of Santa Catarina - EEL/INEP - www.inep.ufsc.br - Phone:+55-48-3721-9204e-mail: [email protected], [email protected], [email protected]

AbstractA novel three-phase hybrid multilevel converter isproposed for medium-voltage applications. The converter em-ploys a conventional three-phase voltage source inverter (VSI)linking series connected half-bridge modules at each phase.With the proposed connection, a large portion of energy canbe processed by the VSI by employing a single multi-pulserectifier, while smaller power shares are processed within the half-bridge modules. Thus, the requirements for galvanically insulateddc sources are reduced. Modularity is naturally achieved. Amodulation scheme for a four-level version is proposed andanalyzed in detail. This scheme allows unidirectional power flowin all dc sources and, consequently enables diode bridges tobe employed in the rectification input stage for unidirectionalapplications.

Index TermsMultilevel converters, Hybrid converters, PWMmodulation, Three-phase inverters.

I. INTRODUCTION

POWER ELECTRONICS applications requiring mediumvoltage (MV) high power converters have been steadilygrowing in fields such as power quality, power systems control,adjustable speed drives (ASD), uninterruptible power supplies(UPS), equipment testing, co-generation and others. Mostapplications demand three-phase multilevel inverters. Varioustopologies have been proposed in the literature [1][16] inorder to improve performance, adapt to requirements and avoidproprietary technologies.

Some topologies find more widespread use in industrialmultilevel inverters. Among these are the neutral clampedconverters, the capacitor clamped converter, the cascaded full-bridge converter, the hybrid Voltage Source Inverter (VSI)/ Neutral Point Clamped (NPC) plus cascaded full-bridgeconverter and the active neutral clamped converter (ANPC).

The diode clamped converter, commonly named NeutralPoint Clamped (NPC), [1], [2], [10], [17] is a multileveltopology, which is widely employed in three-phase powerconversion. There is a single dc-link that is split into twoor more equal voltages which clamp the maximum voltageof the main switches through fast switching diodes. A high

A. L. Batschauer is with the Department of Electrical Engineer-ing, Santa Catarina State University, Joinville 89223-100, Brazil (e-mail:[email protected]). M. L. Heldwein and S. A. Mussa are withthe Power Electronics Institute (INEP), Federal University of Santa Catarina(UFSC), Florianopolis 88040-970, Brazil (e-mail: [email protected],[email protected]).

Copyright (c) 2011 IEEE. Personal use of this material is permitted.However, permission to use this material for any other purposes must beobtained from the IEEE by sending a request to [email protected].

Manuscript received August 31, 2010; revised May 2, 2011.

number of diodes is observed as the number of levels increase.Stabilization of the dc-link voltages for NPC converters withfour or more levels is typically complex and is achieved byposing limitations at the output voltages or loads [18].

The capacitor clamped converter, also know as FlyingCapacitor (FC) converter [5], provides the clamping of thevoltages across the switches through capacitors. The stabiliza-tion of the clamping voltages is achieved due to the highernumber of switching possibilities. Even though the number ofclamping diodes is reduced, the number of capacitors increasesrapidly with the number of levels, increasing the number ofisolated voltage sensors.

The active neutral clamped converters (ANPC) present a sin-gle dc-link for a three-phase inverter. The three-level version isintroduced in [19] and shows improved performance regardinglosses distribution. Five or more level ANPC topologies, whichintegrate some advantages of the NPC and FC converters, areanalyzed in [7], [20], [21]. These topologies also present asingle dc-link and the voltage clamping is achieved with thecontrol of the dc-link and floating capacitors voltages. Thus,the single dc-link of the NPC and the flexibility for voltagestabilization of the FC are observed in these topologies.However, the number of active switches is increased or thevoltage ratings of some of them must be higher. The capacitorsprecharge process is complex. The ANPC topologies areproprietary technologies [22], [23].

Cascaded H-Bridge (CHB) converters [3], [4] employ dc-side isolated series connected full-bridge modules at eachphase allowing high modularity and the lower total numberof components when compared to NPC, ANPC or FC. Thesecharacteristics make them widely employed in industrial ap-plications. As single-phase full-bridge modules are employed,the pulsating power in each dc-source presents a high lowfrequency ripple, increasing the storage effort. In addition,all modules and input rectifiers must process their share ofthe total power, increasing the demands for the rectifier stagetransformers. Furthermore, the CHB is proprietary technologyfor many applications [1], [4], [24][26].

Cascaded half-Bridge (C1/2B) converters [27][31] employhalf-bridge modules connected in series instead of the full-bridge ones. These converters are an alternative to the con-ventional cascaded full-bridge converters. The modular mul-tilevel converter (MMC or M2C) [27][30] employ seriesconnections of pairs of half-Bridge modules. These modulesare connected in delta forming a three phase system and thecapacitors of dc links do not need isolated dc supplies [27],



VR Lin

Lin

Lin

D1A

iAix1A

D1A'

D2A

D2A'

D3A

D3A'

D1B

D1B'

D2B

D2B'

D3B

D3B'

D1C

D1C'

D2C

D2C'

D3C

D3C'

VS

VT

3-phase rectifieriB iC

B CA

R

optional

harmonic filter

S

T

3-phase inverter (VSI)

+ + +

+ + +

S1A

Vx

Vx

Vx

Vx

Vx

Vx

+

+

V

2y

V

2y

Sec1A

Db1A

Db2A

Db3

Db4

Db1B

Db2B

Db1C

Db2C

Sec2A

Sec1B

Sec2B

Sec1C

Sec2C

S1A'

S2A

S2A'

S3A

S3A'

S1B

S1B'

S2B

S2B'

S3B

S3B'

S1C

S1C'

S2C

S2C'

S3C

S3C'

LhRhCh

iR

iS

iT

Fig. 1. Circuit schematic of the proposed hybrid multilevel converter employing half-bridge modules and a three-phase inverter. Further pairs of half-bridgemodules can be connected in series at each phase-leg. The three-phase inverter can be replaced by other three-phase voltage source inverter topologies, forinstance an NPC converter. With an NPC 3-phase inverter five levels in the output phase voltage is reached with the symmetrical version.

[28] since the voltage across each half-bridge module dc-link capacitor can be actively controlled. The C1/2B converter[31] uses an alternative connection of half-bridge modulesto eliminate the output dc level. The three phase systemis reached through a Y connection. The modules are alsoconnected in pairs and the converter is able to provide justodd levels in the output phase voltages. This type of converterrequires a higher number of insulated dc sources for the samenumber of levels of a CHB. However, lower active powerlevels are processed in the dc sources.

Hybrid topologies employing three-phase two-level VSI orNPC cascaded in each phase with series connected H-bridgemodules (HCHB) have been proposed [8], [12], [32][34]as an alternative to the CHB. The number of componentscan be the same as for the CHB given the same numberof voltage levels, while the three-phase converter can bedirectly fed without insulation. Thus, the requirements forthe insulation transformers and for the main capacitive dc-link storage are lessened. Both, HCHB and CHB have theirasymmetric versions [12], [35], presenting advantages anddrawbacks depending on the specific application and availableswitch technology. Hybrid topologies are mainly proprietarytechnology as well [32], [34].

This work presents a novel hybrid topology, here namedHybrid Cascaded Half-Bridge converter (HC1/2B) that makesuse of a three-phase inverter (shown as a VSI in Fig. 1), whereeach output is series connected to a pair, or multiple pairs(cascade), of half-bridge converters connected with inversepolarity as shown in Fig. 1. There, the special connection ofthe half-bridge modules [31] guarantees that no dc level isobserved at the output voltages. In the symmetrical versionthe modularity is preserved. The connection of the 12-pulserectifier that generates the isolated dc sources (cf. Fig. 1)leads to low input current harmonics and well distributedcurrent efforts for the rectifying diodes and windings of thetransformers. Even though the number of insulated sources isincreased, for the same number of voltage levels as for the

CHB or HCHB, the proposed converter lowers the ratings ofthese devices since the average current that is drawn fromeach 6-pulse rectifier feeding a half-bridge module is lowerwhen compared to an H-bridge based converter. Thus, higherpower levels can be achieved for a given transformer/rectifiertechnology.

The possible operation modes for the proposed HC1/2B arediscussed in section II, where the asymmetric versions of thetopology are addressed and the symmetric 4-level converteris presented in detail. Unidirectional power flow is requiredin many applications, such as high power UPS, co-generationand others. In this context, the operation of the converter isoptimized in order to achieve unidirectional power flow in alldc sources and thus, reduce costs associated to bi-directionalrectifiers. A modulation scheme is presented in section III inorder to achieve this goal. Based on the proposed modulation,the output voltage is analyzed in section V regarding itsharmonic spectrum and total harmonic distortion (THD). Thetheoretical analysis is verified in section VI through experi-mental results based on a four-level inverter prototype.

Circuit simulations of the complete four level converteremploying the 12-pulse rectifier (cf. Fig. 1), dc voltagesources maximum ripple Vo 4%, grid-side input in-ductors Lin,p.u. = 5% and transformer leakage inductancesof L,p.u. = 0.2% have been carried out. The inverterload was kept constant regardless the modulation index. Twoac-grid operating conditions have been analyzed, namelly:(i) balanced grid voltages; and, (ii) grid supply voltagespresenting unbalances of 3%. The achieved THD valuesare presented in Fig. 2. Ac-grid unbalances lead to higherdistortion, including triplen harmonics, and different RMScurrent values in each phase. The harmonic distortion may befurther reduced with the use of an appropriately sized filter.The input phase currents and their spectrum for the LM andHM modulation are shown in Fig. 2 for both grid conditions.Fig. 2(a) presents the input currents for LM modulation withmodulation index M = 0.5 and Fig. 2(b) shows the same



variables for HM modulation with modulation index M = 0.9.The same amount of energy is processed by each half bridgecell under all operating conditions. The 12-pulse rectifier thatfeeds these modules does not have its performace degraded bychanges in the modulation pattern. This is achieved becausethe 12-pulse rectifier is actually split into two parts, one thatfeeds the 2-level VSI and the other, whose secondaries supplyenergy for all half-bridge modules. Therefore, each part of the12-pulse rectifier operates with balanced processed powers,thus leading to the same behavior of a conventional 12-pulserectifier supplying two secondaries with balanced loads.

II. MULTILEVEL OPERATION

The following assumptions are made for the analysis: (i)the switching devices are ideal; (ii) the dc sources are con-stant positive voltages; (iii) parasitics are neglected; (iv) thevirtual center point of the VSIs dc-link (drawn in Fig. 1) isassumed as reference for the voltages. Considering a phase-leg composed of a pair of half-bridge modules and a phase-leg of the VSI, the possible operation stages of the proposedconverter are depicted in Fig. 3 for phase A positive values. It

Input

phase

curr

ents

R,unbi

Ri

R,unbi

Ri

S,unbi

T,unbi

Si

S,unbi

Si

Ti

Input

phase

curr

ents

(a)

Ti

0 2T

n1 5 9 13 17 21 25 29 33 37 41 45

0%

4%

8%

100 %T,unbfft(i )

Tfft(i )

THD = 6.3 %iR,unbTHD = 7.0 %iS,unbTHD = 7.2 %iT,unb THD = 2.6 %iR,S,T

2T0

(b)

10 %

6 %

2 %

14 % 100 %

n1 5 9 13 17 21 25 29 33 37 41 45

T,unbfft(i )

Tfft(i )

THD = 11.0 %iR,unbTHD = 12.8 %iS,unbTHD = 13.7 %iT,unb THD = 6.4 %iR,S,T

Fig. 2. (a) Input phase currents and phase T spectrum for LM modulationwith modulation index M = 0.5. (b) Input phase currents and phase Tcurrent spectrum with respect to the fundamental current RMS amplitude forHM modulation with M = 0.9. Simulation conditions: dc voltage sourcesmaximum ripple Vo 4%, inductors Lin,p.u. = 5% and transformerleakage inductances of L,p.u. = 0.2%. Grid supply voltages unbalances of3% (subscript unb) and 0%.

is observed that the output voltage vA can assume six differentvalues, which are given for vo, with o = A,B,C, in Table I.These output voltage levels depend on the dc sources voltagesVx and Vy and on the states of switches Sjo and Sjo , withj = 1, 2, 3. Based on these results, the HC1/2B can be operatedwith a number of levels Nlevel varying from four to six giventhat

Nlevel =

4, if Vx = Vy5, if Vx = Vy/26, if Vy 6= Vx 6= Vy/2

(1)

Based on the possible operation stages for a phase-leg andthe considerations given in Table I, the available space vectorscan be found as shown in Fig. 4(a) for a 4-level HC1/2Bemploying symmetric dc sources with Vy = Vx. The resultingstate-space is a composition of the vectors generated by theVSI with the allowable combination of vectors generated bythe half-bridge cascades. This is highlighted in Fig. 4(b) forthe symmetric case where Vy = Vx and in Fig. 4(c) for theasymmetric case where Vy > Vx. Within each half-bridgespace it is not necessary to switch the VSI state in orderto generate any voltage vector contained in it. It is seen in

vAV

(a) (b)

(c) (d)

x

Vx

Vy2

Vy2

Load

S1A

S1A'

S2A

S2A'

S3A

S3A'

D3A

D3A'

D2A

D2A'

D1A

D1A'

vA

S1A

S1A'

S2A

S2A'

S3A

S3A'

D3A

D3A'

D2A

D2A'

D1A

D1A'i > 0A

i < 0AVx

Vx

Load

Vy2

Vy2

vA

S1A

S1A'

S2A

S2A'

S3A

S3A'

D3A

D3A'

D2A

D2A'

D1A

D1A'

vA

S1A

S1A'

S2A

S2A'

S3A

S3A'

D3A

D3A'

D2A

D2A'

D1A

D1A'

Vx

Vx

Load

Vx

Vx

Load

Vy2

Vy2

Vy2

Vy2

i > 0A

i < 0A

i > 0A

i < 0A

i > 0A

i < 0A

Fig. 3. Operation stages for a phase-leg of the proposed hybrid multilevelconverter employing half-bridge modules for a positive output voltage. Switch-ing stages are: (a) S1A , S2A and S3A are on and va = Vy/2 Vx; (b)S1A, S2A and S3A are on and va = Vy/2; (c) S1A , S2A and S3A areon and va = Vy/2; (d) S1A, S2A and S3A are on and va = Vy/2 + Vx.The output voltage va is referred to the virtual reference shown in the centerpoint of Vy source.



TABLE IRESULTING OUTPUT PHASE VOLTAGE (vo , WITH o = A,B,C) AS A FUNCTION OF THE SWITCHING STATES AND OF THE DC SOURCES VALUES Vx AND

Vy , WHERE sjo(j = 1, 2, 3) CORRESPONDS TO THE STATE OF SWITCH Sjo AND sjo = sjo . (SWITCH ON: 1, SWITCH OFF: 0.)

s1o s2o s3o voCase 1 Case 2 Case 3

Vx = Vy = Vcc Vx = Vy/2 = Vcc Vx = Vy/3 = Vcc

0 0 0 Vx Vy2 3Vcc2 2Vcc 5Vcc21 0 0 Vy

2Vcc2

Vcc 3Vcc20 1 0 Vy

2Vcc2

Vcc 3Vcc21 1 0 Vx Vy2 +Vcc2 0 Vcc20 0 1 Vx + Vy2 Vcc2 0 +Vcc21 0 1 +Vy

2+Vcc2

+Vcc+3Vcc

2

0 1 1 +Vy2

+Vcc2

+Vcc+3Vcc

2

1 1 1 +Vx +Vy2

+3Vcc2

+2Vcc+5Vcc

2

Fig. 4(c) that relatively increasing the dc voltage for the VSIexpands the VSI space and creates a higher number of levels.However, the voltage ratings for the semiconductors is changedaccordingly. The number of redundant switching states is alsopresented in Fig. 4(a) for the four-level converter.

III. MODULATION SCHEME FOR THE 4-LEVELCONVERTER

This section presents a modulation scheme for the four-leveloperation of the HC1/2B where the switches of the three-phase

v5

v15

v31

v3

v

v

4v0

14

v30

v11

v12

v13

v29

v25

26

27

v

v

v

28v1

v6

v16

v32

v2

v10

v24

v7

v18

v17

v33

v8

v9

v23

v19

v36

v35

v34

v

v

20

21

v22

VSI space

y xV = V

(a)

VSI space

Half-bridge

modules spaces

(b) (c)

yV = 3

xV

yV

a

b> 3 xV

a = yV2/3

b = xV 2 2/3

(56) (38) (11)

(16)

(16)

(16)

(16)

(16)

(16)

(11)

(1)

(3)

(3)

(1)

(3)

(3)

(3) (3) (1)

(3)

(3)

(1)

(3)

(3)

(1)(3)(3)(1)

(Redundant states)

(11)

(11)

(11)(11)

(38)

(38)

(38) (38)

(38)

b

a

j

Fig. 4. Space vectors for the proposed converter: (a) space vectors for the4-level converter employing Vy = Vx; (b) contributions for the modulationdomain for Vy = 3Vx, and; (c) contributions for the modulation domain forVy > 3Vx.

VSI switch at low frequency in order to transfer the switchinglosses to the half-bridge modules. This feature allows to uselow speed switches in the three-phase inverter reducing theconduction losses in the VSI [36], while keeping the switchinglosses at the same level, although shifted to the half-bridgemodules. Even though non-uniform losses distribution amongthe power switches occur, the modulation scheme is able tobetter distribute losses among the power modules (comprisingtwo IGBTs and their anti-parallel diodes). The half-bridgemodules are switched at high frequency. Switches Sjo andSjo , with o = A,B,C and j = 1, 2, 3, are switched in a

S

0

12/31/3

1/3

12/3

2A

S

t

1A

Ref

T0 2T

o

S

(a)

(b)

3A

Car3

Car2

Car1

S1o'

S1o

Car

Car

Car

Car

2

3

S3o

S3o'

S2o'

S2o

S3o'

S3o

1

2

S3o

S3o'

Refo

Fig. 5. Modulation strategy HM: (a) timing diagram for the 4-level operation,and; (b) PWM generation logic.



complementary way. The first modulation pattern, is based onthe level shifted in-phase disposition PWM [37]. However,the three-phase VSI switching signals are not directly derivedfrom the modulator/carrier comparison and demand logic to begenerated at the output frequency. Thus, the first strategy isconfigured as a hybrid modulation. As it is used with highmodulation indexes it is here named HM. The half-bridgemodules are derived from sinusoidal modulating signals Refocompared to three synchronized triangular carriers Carj asshown in Fig. 5(a) for a generic phase o, with o = A,B,C.The VSI switches are driven by the direct comparison ofthe modulating signals Refo to zero. The logic employed togenerate the modulation pattern is presented in Fig. 5(b). Forthe four-level converter, the modulation index is defined asM = 2Vp/(3Vcc), where Vp is the peak value of the sinusoidalPWM generated output phase voltages.

The Phase Shift modulation pattern, applied in the proposedconverter, allows that all switches have the same conductionand switching losses. However, these losses and the distortionat the output line voltage are greater than it is achieved withthe proposed modulation [36].

Focusing in unidirectional applications, it is desirable thatall dc sources supply an unidirectional power flow, so thatuncontrolled rectifiers can be employed. Table II shows thatpositive or negative power flow at some of the insulated dcsources does not depend only on the switching states, butalso on the direction of the phase currents. Thus, it is notpossible to control the power flow at all dc sources onlyby choosing proper switching states. The modulation patternpreviously described is not able to guarantee unidirectionalpower flow in the dc sources for the half-bridge modules fora modulation index ranging from null to unity. The outputvoltages of the VSI are kept constant during each half periodand this forces the half-bridge modules to process more powerand regenerate it to the source for low modulation indexes.

TABLE IIOUTPUT PHASE VOLTAGE vo (o = A,B,C) AND ACTIVE POWER

DIRECTION AT THE DC SOURCES AS A FUNCTION OF THE SWITCHINGSTATES AND OUTPUT CURRENTS io DIRECTION. P1o AND P2o ARE THE

AVERAGE POWERS PROCESSED BY THE UPPER AND THE LOWER DCSOURCES, RESPECTIVELY, FEEDING THE HALF-BRIDGE MODULES AT

PHASE o. THE PLUS SIGNAL (+) INDICATES THAT THE SOURCE IS FEEDINGPOWER. THE MINUS SIGNAL (-) INDICATES THAT THE SOURCE IS SINKINGPOWER. THE EMPTY SIGNAL () INDICATES THAT NO CURRENT FLOWS IN

THE SOURCE.

s1o s2o s3o vo P1o P2o io

0 0 0 3Vcc2

/+ / io > 0/io < 01 0 0 Vcc

2/ / io > 0/io < 0

0 1 0 Vcc2

/+ +/ io > 0/io < 01 1 0 +Vcc

2/ +/ io > 0/io < 0

0 0 1 Vcc2

/+ / io > 0/io < 01 0 1 +Vcc

2/ / io > 0/io < 0

0 1 1 +Vcc2

/+ +/ io > 0/io < 01 1 1 +3Vcc

2/ +/ io > 0/io < 0

0

200

100

100

300

200

400

300

Act

ive

po

wer

[%

of

tota

l]

x

yActive power in V

Sum of active power

in all insulated sources V

0.0 1.00.1 0.2 0.3 0.4 0.5 0.6 0.7

M

0.8 0.9

Fig. 6. Active power handled by the dc sources as a percent of the totalload power for modulation pattern HM.

(a)

(b)

S1o'

S1oCar

Car

1,LM

2,LM

S2o'

S2o

Refo

S2A

S

t

1A

Ref

T 2T

o

S3A

Car2,LM

Car1,LM

0

S3o'

S3o

0

12/31/3

1/3

12/3

Fig. 7. Modulation strategy LM: (a) timing diagram for the 3-level operation,and; (b) PWM generation logic.

This is clearly observed in Fig. 6, where the power flow at aninsulated dc source Vx becomes negative for M < 0.42 andthe active power handled by all dc sources is extremely highat low modulation indexes when compared to the total activepower transferred to the load. This characteristics preventsthe employment of modulation HM for the entire modulationindex range.

One way to avoid the regenerative power flow in theinsulated dc sources is to switch the three-phase VSI at highfrequency, generating output PWM voltages with a sinusoidalbehavior proportional to the modulation index. Nevertheless,switching losses at the VSI would increase accordingly. Thus,a modification of the modulation logic is proposed. The VSIhigh side or low side switches are kept turned-on during thewhole period whenever M < 1/2. The modulation pattern forM < 1/2 is presented in Fig. 7 and is named modulation LM.The LM modulation is a variation of the unipolar PWM [37].



Lin

e vo

lt.

Phase

volt

ages

Ph. cu

rren

ts

Bv

Av

Av

VSI,Av

Vx1Ap

HM

0(a)

0(b)

T 2T

0

0

0

0

T 2T 7.5T

LM

Ai

Ai

x1Ai

Bi Ci

AB,(1)v

ABv

Changed modulation scheme

HM LM

Changed modulation scheme

Fig. 8. Waveforms for M = 0.5 during a change from HM to LMmodulation: (a) phase voltages vA and vB , line-to-line voltage vAB and itsfundamental component, and phase currents iA, iB and iC ; (b) phase voltagevA and current iA, output voltage of the VSI vVSI,A, dc source current ix1Aand power pV x1A.

In the LM modulation the command signals of the three-phaseinverter do not change and the command of the half-bridgemodules are the same as for the unipolar PWM.

The modulation scheme basic algorithm is as follows [37]: 0 M 1/2 (LM): the VSI has all switches either

clamped to the positive or to the negative rail. Theclamping can be changed at every modulation cyclein order to balance the losses at all semiconductorsor, whenever possible a bypass mechanical switch canbe driven to reduce conduction losses. The half-bridgemodules process all the active power transferred to theload.

M > 1/2 (HM): each VSI leg switches a single timeper modulation period (cf. Fig. 5) and the half-bridgemodules handle a smaller power share.

This modulation scheme is able to generate three-phasesinusoidal PWM modulated voltages under any modulationindex. It presents the advantage of processing larger powerlevels by the three-phase VSI, which does not require an in-sulated dc source and switches at low frequency. Furthermore,

as seen in section VI, it guarantees that active power levelsequal or lower than the total load active power are processedwithin the multilevel sub-converters.

Both modulation patterns are able to produce line-to-linevoltages with 5-level while all dc sources supply positiveactive power for the range 4/(3pi) < M < 2/3. Therefore,any modulation index within this range can be achieved anda hysteresis control can be used to switch between the twomethods without resulting in oscillations. For instance, whenmodulation index is to be reduced, the pattern change takesplace for M = 0.45, while it happens for M = 0.55 whenM increases. In order to verify modulation pattern transition,Fig. 8 shows simulation results for voltages and currentsduring a modulation change from HM to LM at a modulationindex M = 1/2. It is observed that the modulation patternchange is smooth and does not cause any oscillation at theline voltages and, more importantly, at the phase currents. Itis also important to notice that just some of the redundantstates have been used with the proposed modulation pattern.

IV. EXTENSION FOR MORE THAN TWO HALF-BRIDGEMODULES

This section presents an extension of the proposed multi-level hybrid converter for four half-bridge modules per phase.Employing the symmetric configuration shown in Fig. 9(a)allows to achieve six levels in the phase voltages. Fig. 9(b)shows the converter phase voltages (vA, vB , vC) and linevoltage (vAB) for the multilevel inverter in Fig. 9(a). Anadaption of the proposed HM modulation was used to drivethe inverter. The phase and line voltages present low harmonicdistortion, where the line voltage synthesizes up to elevenlevels. It should be noticed that more transformers (or moresecondaries) and their rectifiers must be added to the converterto supply the additional half-bridge modules with insulated dcsources.

V. OUTPUT VOLTAGE ANALYSIS

The output voltage analysis for the 4-level HC1/2B employ-ing the proposed modulation is performed based on [37] andconsists in expressing the output phase voltages as functionsof harmonic components of the fundamental and carrier fre-quencies. Inverter phase voltages can be expressed by,

f (t) =A002

+

n=1

[A0n cos (n y) +B0nsin (n y)]+m=1

[Am0 cos (m x) +Bm0sin (m x)]+m=1

n=(n 6=0)

[Amn cos (m x+ n y) +Bmnsin (m x+ n y)

],

(2)

with x = ct+ c and y = ot+ o.In (2), variables x and y represent the angular carrier

frequency and the angular fundamental frequency, respectively,



and the terms Amn and Bmn express the amplitude of eachharmonic component. The harmonic components are obtainedthrough the double Fourier integral,

Cmn =Amn + j Bmn=

1

2 pi2 pipi

pipi

f (x, y) ej(mx+ny)dx dy, (3)

where f(x, y) is the output phase voltage synthesized by theinverter. For the computation of the double Fourier integral itis necessary to determine the integration limits for variablesx and y. Those limits are obtained equaling the expressionthat represents the reference modulating signals with theexpressions that represent the ramps that generate the threecarrier signals. This mathematical manipulation follows theconcepts presented in [37], from where a unitary cell with allintegration limits is derived. This unitary cell for the inverteroperation with four levels at the phase voltage is shown inFig. 10. This figure shows variable x integration limits, fromx1..6 and axis y integration limits y1 and y2, which are,

y1 = acos

(1

3 M)

y2 = pi acos(

1

3 M). (4)

iA

A

+Vx

+Vx

+Vx

+Vx

+V

Three-phase voltage source invertery

iB

B

+Vx

+Vx

+Vx

+Vx

iC

C

+Vx

+Vx

+Vx

+Vx

Lin

e vo

lt.

Ph

ase

vo

lta

ges

Av

Cv

Bv

0 T 2T

ABv

(a)

(b)

Fig. 9. Extension of the proposed structure to include more half bridge cellsin a cascade configuration: (a) symmetrical topology (i.e. Vx = Vy) for asix-level converter; and (b) Phase and line voltages for six levels in phasevoltage.

The aforementioned integration limits lead to twenty fourintegrals that are solved to find the amplitude of each harmoniccomponent. Equation (3) is rewritten as

Cmn,i =Vcc2pi2

biai

dici

fi (x, y) ej(mx+ny)dx dy, (5)

which shows the integration limits ai, bi, ci, di and functionfi (x, y) that is the generated voltage level. Integration limitsare given in Table III for positive values of x and y axis.Further eighteen integral limits exist by employing similarprocedures. All twenty four integrals are solved to find theamplitude of each harmonic component. This is shown exem-plarily in Fig. 11 with a comparison to experimental results.Simulation results have led to negligible error values and, thus,are not presented. The theoretical harmonic amplitudes are ingood accordance with the experimental results except from thefact that the low frequency voltage ripple at the dc sources,the interlock delay times and the switching intervals generateharmonic components that are not theoretically computed and,thus, lead to the errors given in Fig. 11.

pi-2 -1 0 1 2

-2

-1

0

pi

pi pi

1x =

-x2

1

x = -x4 3

x = -x

56

2

1

2

-3 Vcc

y

y

x = t + c c

y =

t

+

oo

x = [ 3 M cos( y ) + 3]

52

pi

x = [ 3 M cos( y ) + 1]

32

pi

x = [ 3 M cos( y ) - 1]

12

pi

-3 Vcc -3 Vcc

-Vcc

-Vcc

Vcc

Vcc

3 Vcc

Fig. 10. Unitary cell for 4-level output phase voltage va.

0.06 1.02 1.50 1.980.54 2.520.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

Frequency [kHz]

Experimental

Theoretical

Outp

ut

volt

age

spec

trum

2V

/3V c

cp

1.5 % 1.4 % 1.0 % 3.7 %

2.8 %2.3 %

Fig. 11. Harmonic spectral results for M = 0.9, fvo = 60 Hz and fs =1.02 kHz HM modulation: experimental and theoretical results along withthe absolute error values for the harmonic components that presented absoluteerrors higher than 1%.



TABLE IIIINTEGRATION LIMITS FOR ANALYTICAL OUTPUT VOLTAGE CALCULATION.

PPPPPPLimiti =

1 2 3 4 5 6

ai 0 0 y1 y2 y2 y2

bi y1 y1 y2 pi pi pi

ci 0 x1 0 x3 0 x5

di x1 pi x3 pi x5 pi

fi(x, y) 3 1 1 -1 -1 -3

VI. EXPERIMENTAL VERIFICATION

Experimental verification is carried out in a small scaleIGBT based prototype that implements a symmetrical four-level (Vx = Vy) converter as drawn in Fig. 1. The prototypepresents all dc sources with galvanic insulation through three-phase transformers, which are fed by the mains with a three-phase auto-transformer in order to achieve control of theinput voltages. Three-phase diode bridges rectify the voltagesin the secondary side of the transformers and electrolyticcapacitors smooth the rectified voltages in order to achievelow ripple dc voltages in all dc sources with an average valueof approximately 400 V. A total of nine IGBT half-bridgemodules implement the four-level converter. The employedIGBTs are manufactured by Semikron in half-bridge modules(SKM75GB063D) rated for 600 V and 75 A. The switchingfrequency for the half-bridge converters is set to 1.02 kHz,while the output fundamental voltage is 60 Hz. The hardwarehas been built to offer safe operation margins and flexibilityand, thus, is not optimized for specific operation conditions.The employed RL load presents R = 60 and L = 111 mHdelta connected, leading to a current displacement anglearound 34 @ 60 Hz.

The practical implementation of both modulation patterns,LM and HM, is performed in a DSP, model TMS320F2812,where the gate signals are generated in an open-loop scheme.The modulation employs the DSPs event manager (EVAand EVB) and a few I/O pins. The high frequency PWMpulses are produced by the DSPs PWM modules, while thelow frequency signals are software generated by comparingthe modulating signals to zero. The sinusoidal references areinternally computed through a routine that calculates 60 Hzsinusoidal signals displaced by 120. A zero crossing detectoris virtually implemented in order to compare the polarity of thesinusoidal references. Depending on the instantaneous valueof the modulating function an algorithm adapts the functionlevels to the DSPs PWM modulator. The modulation patternsgenerated by the implemented logic are observed in Fig. 12.

The command signals for both modulation patterns (HMand LM) are shown in Fig. 12. In Fig. 12(a) the commandsignals for HM strategy and a modulation index M = 0.9are presented, while Fig. 12(b) shows the implemented gatecommand signals for LM modulation for a modulation indexM = 0.5. In these figures the switching frequency are reducedto improve visualization.

(a)S2,A

S1,A

S3,A

(b)S2,A

S1,A

S3,A

Fig. 12. Implemented gate signal patterns for (a) HM modulation; (b) LMmodulation. The switches SjA are driven by complementary signals with adead-time of 4 s. Scales 10 V/div, 4 ms/div.

vA

vB

vC

(b)

(a)

vAB

iA

Fig. 13. Experimental results for M = 0.9, fvo = 60 Hz and fs = 1 kHz HM modulation: (a) phase voltage at phase A, B and C; (b) line voltagevAB and phase current iA. Scales are 500 V/div, 10 A/div, 4 ms/div.



vA

vB

vC

vAB

iA(b)

(a)

Fig. 14. Experimental results for M = 0.5, fvo = 60 Hz and fs = 1 kHz LM modulation: (a) phase voltage at phase A, B and C; (b) line voltagevAB and phase current iA. Scales are 500 V/div, 10 A/div, 4 ms/div.

2

33

4

33

(b)

(a)

0

100

200

300

400

500

TH

D [

%]

0.0 1.00.1 0.2 0.3 0.4 0.5 0.6 0.7

Modulation index (M)

0.8 0.9

0

40

20

60

80

100

120

Act

ive

pow

er [

% o

f to

tal]

0.0 1.00.1 0.2 0.3 0.4 0.5 0.6 0.7

Modulation index (M)

0.8 0.9

yP (V )

x P (V )

Phase

Line

Theoretical

Measurement

LM modulation HM modulation

Theoretical

Measurement

7-level5-levelLine-to-line: 3-level

Fig. 15. Measured and theoretical (a) THD for line and phase voltagesaccording to the modulation index M , and; (b) active power for the VSI dcsource P (Vy) and for the sum of the sources for the half-bridge modules

P (Vx). The THD values are computed considering harmonics from 2 to1000.

Applying a modulation index M = 0.9 leads to the phasevoltages, i.e. voltages between the load terminals A, B, Cand the mid-point of the VSIs dc-link, as shown in Fig. 13.Fig. 13(a) presents voltages vA, vB and vC . It is observedthat the phase voltages closely follow the simulated patternsand are displaced by 2pi/3 from each other. The measuredline voltage vAB is given in Fig. 13 (b) together with phasecurrent iA (-connected RL load). Once again the experimen-tal waveforms verify the theoretical analysis demonstrating aseven-level line voltage with low harmonic distortion.

Applying a modulation index M = 0.5 leads to the phasevoltages depicted in Fig. 14. It is observed that the three-levelphase voltages follow the theoretical LM modulation patternwith the dc offset (= 200 V) due to the measurement fromthe phase terminals to the center point of the VSIs dc-link.The line voltage vAB is shown in Fig. 14(b) with the phasecurrent iA. The line voltage presents five-levels as expected.

Fig. 16 shows the output line voltage vAB and the outputphase current iA during two modulation pattern changes fromHM to LM and back to LM to HM. There is no synchronismscheme to perform the changes and it is observed that thereare no significant change in the voltage/current applied to theload. Small oscillations in the modulation signals might bepresent in a closed loop system. Such oscillations may leadto fast changes from a modulation pattern to the other. Thiswill be reduced by employing a hysteresis band that profitsfrom the modulation index range where both patterns can beemployed. This issue would need to be considered carefullywhen applied as part of a closed loop control system.

The modulation index has been varied from close to unityto close to null in order to verify the active power distributionbetween the insulated dc sources and to measure the THDof line and phase voltages. The HM modulation pattern wasemployed from M = 1 down to M = 0.5, while the LMwas used for lower modulation index values. The measurementresults are summarized in Fig. 15 along with the theoreticalresults reported in section III. Regarding voltage THDs, both,theoretical and experimental results are very well matched.Errors lower than 10% are observed at the power distributioncurves, which do verify the simulation results and showthe importance of the modulation scheme for this type ofmultilevel converter.

VII. CONCLUSIONS

A novel hybrid multilevel converter able to achieve four,five or six level operation has been proposed. The mainadvantage for this solution is the possibility of reduction ofthe power ratings for insulated dc sources compared to theCHB and to other hybrid solutions such as the VSI cascadedwith full-bridge converters. The operation principle of theconverter has been clarified and the achievable space vectorspaces presented. A four-level hybrid modulation scheme hasbeen presented, which allows unidirectional power flow inall dc sources for any modulation index and, thus, lowersthe power demand on the insulated dc sources for highmodulation indexes. A pair of 12-pulse rectifiers to supplythe converter is proposed in order to minimize input current



v

HM LM

AB

iA

Fig. 16. Modulation pattern logic signal where HM modulation = 5V andLM modulation = 0V; output line voltage vAB and phase current iA duringmodulation schemes changed from LM to HM and back. Scales are 500V/div,10A/div and 10ms/div.

harmonics. The theoretical analysis of the output voltages hasbeen presented and experimentally verified. Furthermore, themodulation scheme is able to generate, both, phase and linevoltages with low THD. Experimental results based on a builtprototype have validated the performed analysis and shown therelevant operating characteristics of the proposed converter.

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[13] S. Lu and K. Corzine, Multilevel multi-phase propulsion drives, inIEEE Electric Ship Technologies Symposium, 2005, pp. 363370.

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Alessandro Luiz Batschauer Alessandro LuizBatschauer (S09) was born in Balneario Cam-boriu, Brazil, in 1977. He received the B.S. andM.S.degrees in Electrical Engineering and fromFederal University of Santa Catarina (UFSC), Flo-rianopolis, Brazil, in 2000 and 2002, respectively.

Since 2002, he has been with Department of Elec-trical Engineering, Santa Catarina State University.His fields of interest include high-frequency switch-ing converters, power quality, multilevel invertersand soft-switching techniques.

A. L. Batschauer is currently a member of the Brazilian Power ElectronicSociety (SOBRAEP).

Samir Ahmad Mussa Samir Ahmad Mussa (M06)was born in Jaguari-RS, Brazil, in 1964. He receivedhis B.S. degree in electrical engineering from theFederal University of Santa Maria, Santa Maria,Brazil, in 1988, and also holds a second degreein mathematics/physics. His M.Eng. and PhD. de-grees in electrical engineering were awarded by theFederal University of Santa Catarina, Florianopolis(UFSC), Brazil, in 1994 and 2003, respectively.He is currently an adjunct professor at the PowerElectronics Institute (INEP-UFSC), Florianopolis -

SC, Brazil. His research interests include digital control applied to PowerElectronics, power factor correction techniques and DSP/FPGA applications.He is currently a member of the Brazilian Power Electronics Society (SO-BRAEP).

Marcelo Lobo Heldwein Marcelo Lobo Heldwein(M99) received the B.S. and M.S. degrees inelectrical engineering from the Federal Universityof Santa Catarina, Florianopolis, Brazil, in 1997and 1999, respectively, and the Ph.D. degree fromthe Swiss Federal Institute of Technology (ETH),Zurich, Switzerland, in 2007.

He is currently working as a Postdoctoral Fellowat the Power Electronics Institute (INEP), FederalUniversity of Santa Catarina (UFSC), Florianopolis,Brazil under the PRODOC/CAPES program.

From 1999 to 2001, he was a Research Assistant with INEP, UFSC. From2001 to 2003, he was an Electrical Design Engineer with Emerson EnergySystems, in Sao Jose dos Campos, Brazil and in Stockholm, Sweden.

His research interests include power factor correction, static power convert-ers and electromagnetic compatibility.

Mr. Heldwein is currently a member of the Brazilian Power ElectronicSociety (SOBRAEP).

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17.Three-Phase Hybrid Multilevel Inverter

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