18vedic multiplier

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DESIGN AND IMPLEMENTATION OF HIGH SPEED MULTIPLIER USING VEDIC

MATHEMATICS

A Thesis

by

SUPRIYA NIMMAGADDA

Submitted to the College of Graduate StudiesTexas A&M University-Kingsville

in partial fulfillment of the requirements for the degree of

MASTER OF SCIENCE

DECEMBER 2013

Major: Electrical Engineering


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ACKNOWLEDGEMENT

I consider this opportunity to show my gratitude towards my advisor chair Dr. Reza Nekovei,

for his invaluable guidance throughout this thesis work, my career choices and for answering

every question very patiently.

I also extend my appreciation to the members of the supervisory committee; Dr.

Lifford McLauchlan and Dr.Claudio Montiel. This thesis would not have been possible or

successful without their invaluable instructions.

I would like to thank all the faculty and members and staff of Texas A&M University-

Kingsville for the timely response and help I received during my course of study here.


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TABLE OF CONTENTS

Page

ABSTRACT ................................................................................................................................... iii

ACKNOWLEDGEMENT ............................................................................................................. iv

TABLE OF CONTENTS .................................................................................................................v

LIST OF FIGURES ...................................................................................................................... vii

LIST OF TABLES ......................................................................................................................... ix

CHAPTER I. INTRODUCTION .....................................................................................................1

1.1 MAIN PROPOSAL .......................................................................................................3

1.2 ORGANIZATION .........................................................................................................4

1.3 SOFTWARES USED FOR SIMULATION AND SYNTHESIS .................................5

CHAPTER II. DIFFERENT VEDIC MULTIPLICATION TECHNIQUES ..................................6

2.1 BACKGROUND OF VEDIC MATHEMATICS ..........................................................6

2.2 ALGORITHMS OF VEDIC MULTIPLICATIONS .....................................................8

2.2.1 URDHVA TIRYAKBHYAM SUTRA ..........................................................8

2.2.2 NIKHILAM SUTRA ....................................................................................16

CHAPTER III. ARCHITECTURE AND IMPLEMENTATION OF VEDIC MULTIPLIER .....18

3.1 64X64 VEDIC MULTIPLIER BLOCK DESIGN .....................................................18

3.2 ARCHITECTURE AND DESIGN OF 2X2 BIT VEDIC MULTIPLIER .................19



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3.5 ARCHITECTURE AND DESIGN OF 16X16 BIT VEDIC MULTIPLIER .............27



CHAPTER IV. RESULTS .............................................................................................................35

4.1 SIMULATION AND SYNTHESIS RESULT OF 64X64 VEDIC MULTIPLIER ...35



4.4 SIMULATION AND SYNTHESIS RESULT OF 8X8 VEDIC MULTIPLIER .......41

4.5 COMPARISION OF RESULTS OF VEDIC AND ARRAY MULTIPLIERS ..........42

CHAPTER V. CONCLUSION ......................................................................................................44

REFERENCES ..............................................................................................................................45

APPENDIX A: PROGRAM CODES ............................................................................................48

VITA ..............................................................................................................................................71


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LIST OF FIGURES

Page

Fig. 2.1. The Multiplication of integer numbers by urdhva tiryakbhyam .. ...................................10

Fig. 2.2. Line diagram of two 4-bit numbers multiplication .........................................................13

Fig. 2.3. Vedic multiplier Hardware architecture .........................................................................15

Fig. 2.4. Multiplication using Nikhilam sutra ................................................................................16

Fig. 3.1. Block representation of 64X64 Vedic multiplier ............................................................18

Fig. 3.2. Block representation of 2X2 Vedic multiplier ...............................................................19

Fig. 3.3. RTL view of 2X2 Vedic multiplier in quartus II .............................................................20

Fig. 3.4. Block diagram of 4X4 Vedic multiplier ....................................................................…21

Fig. 3.5. 4X4 bit Vedic multiplier Algorithm ................................................................................22

Fig. 3.6. 4X4 Vedic multiplier architecture ...............................................................................…23

Fig. 3.7. 4X4 Vedic multiplier RTL view ......................................................................................24

Fig. 3.8. Block representation of 8X8 Vedic multiplier ..............................................................24

Fig. 3.9. 8X8 Vedic multiplier architecture ..............................................................................…26

Fig. 3.10.8X8 Vedic multiplier RTL view using Quartus II .........................................................27

Fig. 3.11. Block representation of 16X16 Vedic multiplier .........................................................27

Fig. 3.12. 16X16 Vedic multiplier architecture ............................................................................28

Fig. 3.13. 16X16 Vedic multiplier RTL view ...............................................................................29


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Fig. 3.18. 64X64 Vedic multiplier architecture ……………………………………………..…..33

Fig. 3.19. RTL view of 64X64 Vedic multiplier ………………………………………….……34

Fig. 4.1. Simulation Result of 64X64 vedic multiplier by modelsim…………………...…….…35

Fig. 4.2. Simulation Result of 32X32 vedic multiplier by modelsim…………………...….……37

Fig. 4.3. Simulation Result of 16X16 vedic multiplier by modelsim…………………...…….…38

Fig. 4.4. Simulation Result of 8X8 vedic multiplier by modelsim………………………...…….40


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LIST OF TABLES

Page

Table. 4.1. Synthesis report of 64X64 Vedic multiplier ...............................................................36



Table. 4.4. Synthesis report of 8X8 Vedic multiplier ...................................................................41

Table. 4.5. Comparison of delays in both Vedic and array multiplier ...........................................41


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CHAPTER I

INTRODUCTION

Arithmetic operations contain several fundamental functions like Addition, Subtraction,

Multiplication, and Division and so on. Multiplication is one of the basic and mostly used

functions in arithmetic operations [1]. Arithmetic logical unit and multiply and Accumulate

(MAC) are the basic blocks in Digital Signal Processing applications and in these operation

multiplication is the basic function to be implemented [1]. In Convolution, Fast Fourier

Transform (FFT) and microprocessors we implement DSP applications in their arithmetic and

logic units [2]. We need high speed multipliers in DSP processors as these multiplication

operations decide their execution time. Currently, the execution time of a digital signal

processing chip still depends on the multiplication time.

The recent improvement of technologies in many digital and signal processing

applications, the need of high speed processors increased. In many signal and computer

applications, high output of the arithmetic operations are needed to achieve the required

performance [3]. Multiplication is one of the operations in arithmetic operations in such

applications and to develop a high speed multiplier circuit became the main interest over many

years. By reducing the time delay and the amount of power consumed we can meet the

requirements of many applications [3]. This thesis presents different multiplier architectures and

there implementation using Vedic Mathematics.

We need to optimize at all levels that involve the design to minimize power consumption.

The technologies and algorithms used to implement the digital circuits must includes this

optimization, circuit design, topology used to implement the circuits and the level at which the

algorithms are designed. Digital multipliers are the main components used in any digital


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architecture. To implement any operation we need fast, reliable and efficient components. We

have different types of multipliers available depending on the arrangement of the components.

In many DSP algorithms, the performance of digital signal processor algorithm depends

on the multiplier that lies in the critical delay path. The speed and time delay of multiplication

operation are important in DSP and also in the general processor. Previously a set of addition,

subtraction and shift operations are used to implement the multiplications. Previously, there were

a lot of algorithms described to perform multiplication operation, each offering different

advantages based on the speed, circuit design, effective area, and time delay, power dissipation

and consumption.

In computing system the major block is multiplier. The relation between the circuit

design and constancy is, the amount of circuitry involved i.e. size of the device (n) is directly

proportional to square of its constancy i.e. constancy is having gates. For all the multiplication

algorithms that are used in DSP applications, the latency and execution time are the two major

terms in the time delay perspectives. While computing a function when a latency delay occurs,

it's nothing but calculation of how much time the inputs of a device are constant; it is the final

result on the outputs. Multiplier is a major source of power dissipation and it's also a high delay

block in the processor. Due to the high delay the power dissipation is also high so we plan

minimize power consumption we also require to minimize the delay by using various delay

optimizations [4].

In many of the digital signal processors (DSPs), digital multipliers are the main

component used in it and their speed is largely determined by the speed of the DSPs [2]. The

basic multipliers used in digital systems are Booth multiplication and Array multiplication. The

execution time of the array multiplier less as the partial products is calculated individually.


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multipliers arises. In order to reduce the Delay and speed up the digital signal processors, new

multipliers are implemented using Vedic mathematics techniques.

Vedic mathematics is mainly defined by 16 formulas (sutras) and was re discovered in twentieth

century [6]. The proposed multiplier technique is f rom “urdhva tiryakbhayam sutra “which is one

of the sutras in Vedic mathematics which is discussed in chapter 2. Now we are going to code

this technique in VHDL and synthesis using Quartus II. So we can calculate time delay, speed of

the proposed multiplier and can see the performance of multiplier by comparing to some

standard multipliers use in the processors such as array multipliers.

1.2 ORGANIZATION

• In chapter II the basic concept of multiplications, different algorithms of multipliers and

performance of Vedic multiplier are discussed.

• In Chapter III the architectures and design of different size of the Vedic multiplier are

discussed. These different size modules are coded in VHDL using the software

ModelSim10.2c.

• In chapter IV the results obtained from simulation of Vedic multiplier on Modelsim are

shown. Then the results obtained from synthesis of Vedic multiplier i.e. time delay is

tabulated.

• Chapter V presents conclusion and future development of the thesis.


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1.3 SOFTWARES USED FOR SIMULATION AND SYNTHESIS

• Simulation Software: Modelsim10.2c

•

Synthesis Software: Quartus II 9,1 version.


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CHAPTER II

DIFFERENT VEDIC MULTIPLICATION TECHNIQUES

2.1 BACK GROUND OF VEDIC MATHEMATICS

They are four types of ancient mathematics, the Vedas and Vedic mathematics is one of part the

four Vedas. The Atharva Veda is a UPA-Veda (appendix), the Sthapatya-Veda (Civil

engineering and construction of the book), part of the atharva Veda . Arithmetic, trigonometry

geometry (plane, coordinate), quadratic equations, calculus factor, and also including the

description applies to many modern mathematical terms are explained in this atharva Veda[6].

His Holiness jagadguru Shankaracharya Bharati Krishna Teerthaji Maharaja (1884 −

1960 comprised all this work together and gave its mathematical explanation while using it for

various applications. After thorough research in Atharva Veda, swahij described

16 sutras(formulae)and 16 upa sutras(sub formulas). In present text of Atharva Veda these

formulae are not found because these formulae were implemented by Swamiji himself [6]. Vedic

mathematics is a mathematical miracle, but it is also logically. That is the reason why Vedic

mathematics has such a degree of fame. Because of this unusual characteristic, Vedic

mathematics has already crossed the boundaries of India and became the upcoming topic of

research. Several basic and complex multiplications can be easily solved by Vedic mathematic.

They are many basic methods in vedic mathematics for arithmetic, which are very simple and

effective [6][7][8][9].

The word “Vedic” is derived from the Sanskrit word “veda” which means the wisdom. The

branches of maths like geometry, arithmetic, algebra, etc are solved by Vedic mathematics by

using the 16 sutras. These Sutras are listed with their brief meanings are shown below[6].


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1)(Anurupye)shunyamanyat − if one is in ratio, the other is zero.

2)Chalana − kalanabyham − Difference and similarities.

3)Ekadhikina purvena − By one more than the previous one.

4)Ekanyunena purvena − By one less than the previous one.

5)Gunakasamuchyah − The factors of the sum is equal to the sum of the factors.

6)Gunitasamuchyah − The product of the sum is equal to the sum of product.

7)Nikhilam navatashcaramam dashatah − All from 9 and last from 10.

8)Paraavartya yojayet − Transpose and adjust.

9)Puranapuranabyham − By the completion or non completion.

10)sankalana vyavakalanabhyam − By addition and by subtraction.

11)Shesanyankena charamena − The remainders by the last digit.

12)Shunyam saamyasamuccaye − When the sum is the same that sum is zero.

13)Sopaantyadvayamantyam − The ultimate and twice the penultimate.

14)Urdhva − tiryakbhyam − Vertically and crosswise.

15)Vyashtisamanstih − Part and whole.

16)Yaavadunam − Whatever the extent oits deiciency

These ideas and algorithms can be directly implemented to some mathematical branches like

algebra, trigonometry, and geometry and so on. As explained above, all these formulae were re

constructed from ancient texts of Vedic of some centuries ago. And many other Sub-sutras were

also re-discovered.

The best aspect of Vedic mathematics is to simplify the cumbersome calculations of

conventional mathematics. For this reason, the Vedic formulae are gives the direct and simple


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way of calculation by using our brain. Now a days this became a interesting field for research

and some effective designs are implemented that are used in various branches of mathematics

and engineering.

The architecture of multiplier is divided into three main categories. Firstly, the serial

multiplier and it is benefit for hardware implementation as it requires only a minimum area of the

chip. Secondly, parallel multiplier which is also known as array multiplier and it performs high

speed mathematical operations. Higher consumption of chip area is the main drawback. Lastly,

the serial- parallel multiplier and it delivers a satisfactory trade-off between the area consuming i

parallel multipliers and the serial multiplier consuming times [1].

2.2

The Vedic multiplier is implemented based on the one of the sutras that is mentioned in the

above list. These sutras have been usually used in the decimal number system for the product of

two numbers. In this thesis, In this paper, the similar idea is applied to the binary system in an

appropriate way using the digital hardware of the suggested algorithm. Vedic multiplication

based on some algorithms such as urdhva tiryakbhyam and nikilam

2.2.1

The multiplier is based on an algorithm Urdhva tiryakbhyam sutra of ancient Indian Vedic

Mathematics. Among all sutras UrdhvaTiryakbhayam Sutra is applicable for any type of

multiplication. Precisely, it means “vertically and crosswise”. The main concept is generation of

partial products and concurrent addition of these partial products is done that which gives the

final result. Using UrdhvaTriyakbhyam in Fig.2.1, the parallelism is obtained in formation of

partial products and their sum. This algorithm can be generalized for higher number bits like n x

n bit number. In the processor, the multiplier is not dependent on the frequency of the clock as


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the partial products and their additions are computed in parallel. Thus, the similar amount of time

is required by the multiplier to compute the multiplication and hence, not dependent on the clock

frequency. Therefore, the main net advantage is that it lessens the usage of microprocessors to

run at higher clock frequency. The main drawback is that it results in greater device operating

temperatures as the power dissipation also increases. By adopting the Vedic multiplier, the

catastrophic device losses are avoided as the microprocessors designers can easily be evaded.

Because of its traditional structure, the input and output data bus widths are increased as the

processing power of multiplier is easily increased. Due to its normal structure, it can be simply

designed on a Silicon chip. As the count of bits increases, delay in the gate and area are increased

very slowly when compared with other basic multipliers, which is the main advantage of the

multiplier. Therefore, it is time, area and power efficient. Hence, this architecture is capable in

terms of area/speed of silicon [6][7][8][9][10].

Multiplication of two decimal numbers- 325*738

1) Multiplication scheme is explained by the product of two decimal. Consider the product of

two numbers (325*738). Fig.2.2 shows the line diagram. The numbers of the line on the two

sides are multiplied and are added along with the carry from the last step. Hence, a carry and

result of one of the bits is generated by it. In the later step, the previous carry is added to it and

therefore, the method goes on. If there are several lines in one step, all the current results are

added to the former carry. In every step, LSB acts as the outcome bit and all other remaining bits

act as carry for the next coming step. At the beginning, the carry is taken as zero. To make the

method more clear, the other explanation is given in Fig.2.2 which is a line diagram .,/0


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Fig 2.1: The multiplication of two integers by UrdhvaTiryakbhyam.

2) 4 x 4

= ( )

Multiplicand

Multiplier

--------------------------------------------------------------------

--------------------------------------------------------------------

Product


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---------------------------------------------------------------------

PARALLEL CALCULATION METHODOLOGY

1. = ∗ =

2. = ∗ + ∗ =

3. = ∗ + ∗ + ∗ =

4. = ∗ + ∗ + ∗ + ∗ =

5. = ∗ + ∗ + ∗ =

6. = ∗ + ∗ =

7. = ∗ =


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3) × [11]-

=

=

*

----------------------------------------------------

-----------------------------------------------------

= ∗ =

= ∗ + ∗ =

= ∗ =

Where CP = Cross Product.

Two binary numbers are considered to explain the multiplication algorithm, say

and and perform multiplication for these two binary numbers. The product

of this multiplication would be of size 8-bits or even less and it is expressed

as. Figure 2.2 shows the Line diagram representation of two 4-bit numbers

multiplication. It is nothing but mapping in binary system of Fig.2.1. To understand easily, bit is

denoted by a circle. LSB is achieved by LSB multiplication of the LSB of multiplier with LSB of

multiplicand and the process proceeds in a step wise manner as shown in Fig.2.1[6][11].


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Fig 2.2: Line diagram representation of two 4-bit numbers multiplication

LSB (vertical) are achieved by multiplying the last bits of both multiplier and

multiplicand. The last but one bit of the product is obtained by The multiplier’s next higher bit is

multiplied with last bit of the multiplicand and added with the product of next higher bit of the

multiplicand and last bit of multiplier (diagonally)in order to obtain the last but one bit of the

product. During addition of bits they may generate a carry and the carry obtained is added to the

result of next step. The next step sum is achieved by the adding the diagonal and vertical product


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of multiplicand and multiplier and also the previous step carry is added to the result. In the step,

all the 4-bits of two numbers are done through diagonal multiplication and addition to deliver

sum and carry. The obtained sum is the similar bit of the multiplication and the carry is again

added to the next step product and sum of three bits excluding the LSB. The similar process goes

for MSBs until we get the product of bits of MSB

Thus we get the following expressions:

= ; (1)

= + ; (2)

= + + + (3)

= + + + + (4)

= + + + (5)

= + + (6)

= + (7)

Therefore the product of two binary numbers is

=


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Fig 2.3: Vedic multiplier Hardware architecture [12]

In Figure 2.3 the four bit multiplier hardware realization is shown. The hardware design

of Vedic multiplier is similar to the array multiplier where the adders in an array order are

required to get the product. The partial products are obtained by parallel computing methodology

and the time delay taken is the time taken to propagate carry over the adders through which the

multiplication array is formed. Precisely, it is not a productive algorithm for the product of big

numerical as high amount of propagation delay is involved. This problem can be eliminated by

the Nikhilam Sutra which provides an effective process to multiply two big numbers.


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2.2.2 Nikhilam sutra

This Sutra actually means “all from 9 and last from 10”. Though it is applicative to all

types of multiplication, it is highly capable when the numbers involved are high. As the

compliment of the big number is found from its nearby base to do the multiplication activity on

it, greater is the original number, minor the complexity of the multiplication. Firstly, this Sutra is

explained by doing the multiplication of two decimal numbers (96 * 93) where the selected base

is taken as 100 which is closest to and higher than both these numbers[4][6].

Figure 2.4: Multiplication Using Nikhilam Sutra [11]

By seeing the Fig. 2.4 column 2 is obtained by subtracting the both numbers with nearest

common base number. So we get 4(100-96) and 7(100-93) and by multiplying these numbers we


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get the least significant bits (7*4 = 28) .In these way we get the right hand side of the product is

achieved. In a cross-way manner subtracting the first number of Column 2 from the second

number of column 1(93-4=89) or in similar way, the second number of Column 2 is subtracted

from the first number of column 1( 96 – 7 = 89) we get the same result that is 89 , this gives left

hand side product . The final output is achieved by joining RHS and LHS (output = 8928) [12].


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CHAPTER III

ARCHITECTURE AND IMPLEMENTATION OF VEDIC MULTIPLIER

The designing of Vedic Multiplier is different from conventional multiplier like array

multipliers. Even though both multiplier have the same number of multiplications, the array

multiplier use some small blocks like shift and add for designing higher order multipliers. Vedic

Multiplier is designed in VHDL, as it is more effective in structural way of coding. The

individual block is implemented using VHDL language. The performance of each multiplier is

determined using the software ModelSim 10.2c and the timing report is obtained by synthesis in

quartusII 9.1 version [13][14][15].

3.1. 64X64 BIT VEDIC MULTIPLIER BLOCK DESIGN

A (63:0)

P (127:0)

B (63:0)

Fig 3.1: Block representation of 64x64 Vedic Multiplier

Input data register (A), Input data register (B), output data register (P) are three ports used.

The representation has three ports:

1) (63: 0): first input of Vedic Multiplier of length 64.

2)(63: 0) : second input of Vedic Multiplier of length 64.

3) P (127:0): Vedic Multiplier output register.

64 X 64 VEDIC

MULTIPLER


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This code was implemented by using VHDL language. Both time delay and implementation of

the Vedic Multiplier structures of this code have been simulated in modelsim 10.2c and

synthesized in a quartus II 9.1 version with devices stratixII EP2S15F484C3 and StratixII

EP2S60F672C3ES.

3.2 ARCHITECTURE AND DESIGN OF 2x2 VEDIC MULTIPLIER

One bit multipliers and adders are the basic building blocks the 2!2 multiplier. The two input

AND gate is used to perform one bit multiplier and for one bit adder we can use full adder. The

basic 2 ! 2 bit multiplier block representation is shown in Fig. 3.2.

A (1:0)

P (3:0)

B (1:0)

Fig. 3.2: Block representation of 2!2 Vedic Multiplier.

Let us consider two data inputs, each of length 2 bits; say and. The output can be of four

bit length, say. As per basic method of multiplication, we can obtain the result by getting

partial product and then by adding it.

2 X 2 VEDIC

MULTIPLER


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× 10

------------------

-----------------------------------

In Vedic multiplier, is obtained by vertical multiplication of data bits and ,

is obtained by addition of crosswise bit product i.e. and and next is obtained by

adding the product vertical data bits and with the carry generated from the previous addition

during . is the nothing but carry generated in calculation of . This part is the operation

of 2x2 multiplier block.

Fig 3.3: RTL View of 2!2 Bits Vedic Multiplier in quartus II


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3.3 ARCHITECTURE AND DESIGN OF 4!4 BIT VEDIC MULTIPLIER

As number of bits increases in input, a small modification is required. Divide the total number of

bits of each input into two equal parts [8].

A (3:0)

P (7:0)

B (3:0)

Fig 3.4: Block representation of 4x4 Vedic Multiplier.

Now let us implement 4x4 multiplications with inputs as and . The

result obtained by multiplication the two inputs are represented as . 4x4

Vedic Multiplier block diagram is shown in Fig. 3.4.

Let us divide the inputs A and B into two equal parts as we mentioned above, say

and for input A and and for input B. Take two bits at a time by using the basic

principle of Vedic multiplication and using 2 bit Vedic multiplier block,

×

4 X 4 VEDIC

MULTIPLER


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&&

-----------------------------------------

Fig 3.5: 4x4 Vedic Multiplier Algorithm[7].

The blocks shown above are 2x2 bits multipliers. The first block is 2!2 multiplier with

inputs as and .The end block is 2!2 multiplier with and as inputs. The

middle one shown in algorithm is two 2x2 bits Vedic multiplier one with inputs and

and the other one with inputs and . So the multiplication of two 4 bits numbers is 8

bit number and the output bits are represented as . The final result is obtained

by adding the outputs of 2!2 bit multipliers in a specific way. So we require three ripple carry

adders at final stage as shown in Fig. 3.6.

By observing the algorithm we can say that 4x 4 bit multipliers are designed from 2X2 bit

blocks.


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PRODUCT = ( − )& ( − )& ( − ).

Fig. 3.6: 4!4 Bits Vedic Multiplier architecture

The RTL view of the 4!4 Vedic multiplier is obtained by compilation in QuartusII 9.1 version.

The RTL view is in Fig. 3.7.


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Fig 3.7: 4x4 Vedic Multiplier RTL View


The 8!8 Vedic multiplier block representation is shown in the figure below

A (7:0)

P (15:0)

B (7:0)

Fig. 3.8 Block representation of 8!8 Vedic multiplier

8x8 Vedic

multiplier


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The 8x8 bit Vedic multiplier is designed using 4!4 multiplier as shown in the block

diagram in Fig. 3.9 can be easily implemented by using four 4x4 bit Vedic multiplier modules as

discussed above. Let us implement 8x8 multiplications with inputs as =

and . The result obtained by multiplication of two 8-bit inputs is represented

as . 8x8 Vedic Multiplier block diagram is shown

in Fig 3.8.

Now divide the inputs A and B into two equal parts, the 8 bit multiplicand A can be split

into pair of four bits − . In Similarly way multiplicand B can be split into − . The 16

bit result can be written as

= ×

= ( − ) × (−)

=( × ) + ( × ) + ( × ) + ( × )

Where =

=

=

=

By observing the structural implementation block diagram of 8!8 Vedic multiplier as

shown in Fig. 3.9, we require four 4!4 multipliers and three ripple carry adders. The outputs of

four 4!4 bit multipliers are added according with three 8-bit RCA as in Fig 3.9, in order to

obtain the final product. Thus, 4!4 Vedic multipliers are the basic building blocks to implement

8!8 Vedic multiplier [8].


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For higher multiplier implementation like 16!16 bits multiplier is reduced to 8!8 bits multiplier

module which is already implemented in Modelsim10.2

In similar way we can implement higher bit multiplier such as 16, 32, and 64.

PRODUCT = ( − )& ( − )& ( − ).

Fig 3.9: 8X8 Bits Vedic Multiplier architecture

The RTL view of the 4!4 Vedic multiplier is obtained by compilation in QuartusII 9.1 version.



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Fig 3.10: 8!8 Bits Vedic Multiplier RTL view using quartus II

3.5 DESIGN AND IMPLEMENTATION OF 16! 16 BIT VEDIC MULTIPLIER

The 16x16 Vedic multiplier block diagram representation is shown in the Figure 3.11.

A (15:0)

P (31:0)

B (15:0)


16x16 Vedic

multiplier


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The 16!16 bit vedic multiplier structured using 8X8 bits vedic blocks as shown in Figure 3.12.

PRODUCT = ( − )& ( − )& ( − ).

Fig 3.12: 16!16 Bits Vedic Multiplier architecture

In this Fig. 3.12 the 16 bit multiplicand A and multiplicand B are split into a pair of 8 bit, Say

− and − respectively.


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By observing the structural implementation block diagram of 16!16 vedic multiplier as

shown in Fig. 3.12. We require four 8!8 multipliers and three ripple carry adders. The outputs

of four 8!8 bit multipliers are added according with three 16-bit RCA as shown in Fig. 3.12, in

order to get the final product.

In similarly way, we can extend the same for input bits 32, 64.

The RTL view of the 16!16 Vedic multiplier is obtained by compilation in QuartusII 9.1

version. The RTL view is in Fig. 3.13.

. Fig 3.13: 16!16 Bits Vedic Multiplier RTL view


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The 32!32 Vedic multiplier block diagram representation is shown in the figure below

A (31:0)

P (63:0)

B (31:0)

Fig. 3.14 Block representation of 32!32 vedic multiplier



1) A (31:0): Vedic Multiplier first input of length 32.

2) B (31:0): Vedic Multiplier second input of length 32

3) P (63:0): Vedic Multiplier output register of length 64.

This code was implemented by using VHDL language

In the Fig. 3.15 the 32 bit multiplicand A and multiplicand B are split into a pair of 16 bit,

Say − and − respectively.

By observing the structural implementation block diagram of 32!32 vedic multiplier as

shown in Fig. 3.15. We require four 16!16 multipliers and three ripple carry adders. The outputs

of four 16!16 bit multipliers are added according with three 32-bit RCA as in Fig. 3.15, in order

to get the product.

32!32 vedic

multiplier


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The 32x32 bits Vedic Multiplier design is shown in Fig. 3.15.

PRODUCT = ( − )& ( − )& ( − ).

Fig 3.15: 32!32 Bits Proposed Vedic Multiplier

The RTL view of the 32!32 Vedic multiplier is obtained by compilation in QuartusII 9.1

version. The RTL view is in Fig. 3.16.


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Fig. 3.16. 32!32 Bits Vedic Multiplier RTL view

3.7. ARCHITECTURE AND DESIGN OF 64!

64 BIT VEDIC MULTIPLIER

The 64!64 Vedic multiplier block diagram representation is shown in the Figure 3.17.

A (63:0)

P (127:0)

B (63:0)


64!64 Vedic

multiplier


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1) (63: 0): first input of Vedic Multiplier of length 64.

2)(63: 0) : second input of Vedic Multiplier of length 64.

3) P (127:0): Vedic Multiplier output register.

The 64!64 bits Vedic Multiplier design is shown in Fig. 3.18

Fig. 3.18: 64!64 Bits Proposed Vedic Multiplier architecture


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PRODUCT = ( − )& ( − )& ( − ).

In the Fig. 3.18 the 64 bit multiplicand A and multiplicand B are split into a pair of 32 bit,

Say − and − respectively. By observing the structural implementation block

diagram of 64!64 Vedic multiplier as shown in Fig. 3.18, we require four 32!32 multipliers and

three ripple carry adders. The outputs of four 32!32 bit multipliers are added according with

three 64-bit RCA as in Fig. 3.18, in order to get the final product.


Fig. 3.18: RTL View of 64!64 Bits Vedic Multiplier


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CHAPTER IV

RESULTS

4.1. SIMULATION AND SYNTHESIS RESULT OF 64!64 VEDIC MULTIPLIER

4.1.1 Simulation result:

Fig. 4.1 Simulation Result of 64!64 Vedic Multiplier by modelsim

Description:

a = Vedic multiplier data input of length 64.

b = Vedic multiplier data input of length 64.

p = Output data of length 128.


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= 1100110011001100110011001100110011001100110011001100110011001100

= 1010101010101010101010101010101010101010101010101010101010101010

= 000001111000011110000110100001110000010110000110100001001000010111

11010001110110011101010111011011110110011101110111011101111000

4.1.2. Synthesis result:

The 64!64 Vedic multiplier is synthesized by using Quartus II 9.1 build 22210/21/2009 sj

version. The following Table 4.1 shows the synthesis report by using two different devices of

startix II family.

STARTIX II

DEVICE

MAXIMUM TIME

DELAY

NO. OF I/O PINS

USED

COMBINATIONAL

ALUT’S

EP2S15F484C3 84.960ns 256 out of 343(75%) 11199/12480(90%)

EP2S60F672C3ES 96.414ns 256 out of 493(52%) 12148/48352(25%)

Table 4.1. Synthesis report of 64!64 Vedic multiplier


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4.2. SIMULATION AND SYNTHESIS RESULT OF 32!32 VEDIC MULTIPLIER:



Description:




= 11110000111100001111000011110000

= 11001100110011001100110011001100

= 0011111110111111101111101011111010111110001111110011111101000000


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startix II family.

STARTIX II

DEVICE

MAXIMUM TIME

DELAY

NO. OF I/O PINS

USED

COMBINATIONAL

ALUT’S

EP2S15F484C3 44.826ns 128 out of 343(37%) 2939/12480(24%)

EP2S60F672C3ES 48.150ns 128 out of 493(26%) 2939/48352(6%)



4.3.1 Simulaton result:



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Description:




= 1010101010101010

= 1110111011101110

= 00001110001010000010011000001100




startix II family.

STARTIX II

DEVICE

MAXIMUM TIME

DELAY

NO. OF I/O PINS

USED

COMBINATIONAL

ALUT’S

EP2S15F484C3 26.959ns 64 out of 343(37%) 690/12480(24%)

EP2S60F672C3ES 27.006ns 64 out of 493(26%) /48352(6%)



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Description:




= 10111011

= 00100010

= 0001100011010110


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The 8!8 Vedic multiplier is synthesized by using Quartus II 9.1 build 22210/21/2009 sj version.

The following Table 4.3 shows the synthesis report by using two different devices of startix II

family.

STARTIX II

DEVICE

MAXIMUM TIME

DELAY

NO. OF I/O PINS

USED

COMBINATIONAL

ALUT’S

EP2S15F484C3 16.255ns 32 out of 343(6%) 156/12480(1%)

EP2S60F672C3ES 19.672ns 32 out of 493(3%) 156/48352(1%)


4.5. COMPARISION OF RESULTS OF VEDIC MULTIPLIER AND ARRAY

MULTIPLIER:

The time delay of different sizes of array multiplier is calculated and compared with proposed

Vedic multiplier. If the delay is less when compared to the delay of general multipliers like array

multipliers then Vedic multipliers are the fastest multipliers.

Table 4.5 Comparison of delays in both Vedic and array multipliers

STARTIX II

FAMILY DEVICE

SIZE OF

MULTIPLIER

TYPE OF

MULTIPLIER

MAXIMUM TIME

DELAY

EP2S15F484C3 64!64 VEDIC 84.960ns


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64!64 ARRAY 118.318ns

EP2S60F672C3ES 64!64 VEDIC 96.414ns

64!64 ARRAY 109.044ns

EP2S15F484C3 32!32 VEDIC 44.826ns

32!32 ARRAY 58.492ns


32!32 ARRAY 59.034ns

EP2S15F484C3 16!16 VEDIC 26.959ns

16!16 ARRAY 28.075ns


16!16 ARRAY 31.368ns

EP2S15F484C3 8!8 VEDIC 16.255ns

8!8 ARRAY 17.32ns


8!8 ARRAY 18.830ns

Table 4.5. Continued


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CHAPTER V

CONCLUSION

The thesis work shows the design and implementation of 8!

8 Vedic multiplier using VHSIC

hardware description language and then on observing the architecture of 8 bit Vedic multiplier, I

have designed and implemented the 16!16 bit, 32!32 bit, 64!64 bit Vedic multipliers by using

VHSIC hardware description language and then the codes are compiled and simulated in

modelsim10.2c.

Later on all the designs is synthesized using quartus II 9.1 version with startix II family

devices and the RTL view of implementation of 2!2 bit, 4!4 bit, 8!8 bit, 16!16 bit, 32!32 bit,

64!64 bit Vedic multiplier is observed. Then time report of each Vedic multiplier is observed

with two devices of startix II family namely EP2S15F484C3, EP2S60F672C3ES and worst delay

of all Vedic multipliers are observed and also tabulated in Chapter 4.

I have designed the array multiplier for the same 2!2 bit, 4!4 bit, 8!8 bit, 16!16 bit,

32!32 bit, 64!64 bit multiplier using vhdl and then synthesized in quartus II 9.1 version with

two devices of startix II namely EP2S15F484C3, EP2S60F672C3ES. After synthesis, the worst

case delays are calculated for all the multipliers and are also tabulated in Chapter 4.

On observing the worst case delays of Vedic and array multipliers of different sizes of

input bits, the Vedic multipliers has less delay when compared to the array multipliers. As the

numbers of bits at the input increases the computational delay is very less. So the worst case

delays of Vedic and array multipliers of different input bits are tabulated below.


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Number of bits Array multiplier worst case

delay(ns)

Vedic multiplier worst case

delay(ns)

8x8 17.32 16.255

16x16 28.075 26.959

32x32 58.492 44.826

64x64 118.318 84.960

Therefore on observing it the proposed Vedic multipliers are fast multipliers than conventional

multipliers. As number of input bits increases the Vedic multiplier is more efficient.

Hence my aim of designing of fast and low time delay multiplier is fulfilled.

In future if these multipliers have best hardware, then we can easy reduce the computational

delay of many processors. By using different algorithms of Vedic mathematics we can even

design a ALU and even we can use these multipliers in calculation of FFT and IFFT transforms.


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REFERENCES

[1] Purushottam D. Chidgupkar and Mangesh T. Karad, “The Implementation of Vedic

Algorithms in Digital Signal Processing”, Global J. of Engng. Educ., Vol.8, No.2 © 2004

UICEE Published in Australia.

[2] Akkhalesh K. Itawadiya, Rajesh Mahle, Vivek Patel, Dadan Kumar, “Design a DSP

Operations using VedicMathematics”, International conference on Communication and

Signal Processing, April 3-5, 2013

[3] E. Abu-Shama, M. B. Maaz, M. A. Bayoumi, “A Fast and Low Power Mul tiplier

Architecture”, The Center for Advanced Computer Studies, The University of Southwestern

Louisiana Lafayette, LA 70504, Proceeding of 39th Midwest Symposium on Circuit and

Systems,1996.

[4] Harpreet Singh Dhillon and Abhijit Mitra, “A Reduced- Bit Multiplication Algorithm for

Digital Arithmetics”, International Journal of Computational and Mathematical Sciences,

2008.

[5] Shamim Akhter, “VHDL Implementation of Fast NXN Multiplier Based on Vedic

Mathematics”, 18th European Conference on Circuit Theory and Design,2007.

[6] Jagadguru Swami, Sri Bharati Krisna, Tirthaji Maharaja, “Vedic Mathematics or Sixteen

Simple Mathematical Formulae from the Veda, Delhi (1965)”, Motilal Banarsidas,

Varanasi, India, 1986.

[7]

Zhijun Huang, Milos D. Ercegovac, "High-Performance Lefl-to-Right Array Multiplier

Design," arith, pp.4, 16th IEEE Symposium on Computer Arithmetic (ARITH 16 '03),

2003


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[8] Ramalatha, M Dayalan, K D Dharani, P Priya, and S Deborah, "High speed energy

efficient ALU design using Vedic multiplication techniques", ICACTEA, 2009. pp. 600 3,

Jul 15-17, 2009.

[9] Pushpalata Verma, K. K. Mehta,” Implementation of an Efficient Multiplier based on

Vedic Mathematics Using EDA Tool”, IJEAT, 2249 – 8958, Volume-1, Issue-5, June 2012.

[10] G.Ganesh Kumar, V.Charishma, “ Design of High Speed Vedic Multiplier using Vedic

Mathematics Techniques”, International Journal of Scientific and Research Publications,

Volume 2, Issue 3, March 2012.

[11]

Sree Nivas A, Kayalvizhi N, “Implementation of Power Efficient Vedic Multiplier”,

International Journal of Computer Applications (0975 – 8887) Volume 43 – No.16, April

2012.

[12] Prabir Saha, Arindham Banerjee, Partha Battacharyya, Anup Dhandapat, “High speed

design of complex multiplier using Vedic mathematics”, Proceedings of the 2011 IEEE

students technology symposium, IIT Kharagpur, pp. 237-241, Jan. 2011.

[13]

Parth Mehta and Dhanashri Gawali, “Conventional versus Vedic mathematics method for

Hardware implementation of a multiplier”, International conference on Advances in

Computing, Control, and Telecommunication Technologies, pp. 640-642, 2009.

[14] Anthony O'Brien and Richard Conway "Lifting Scheme Discrete Wavelet Transform Using

Vertical and Crosswise Multipliers", International signals and systems conference (ISSC),

Galway, Ireland, June 18- 19, 2008.

[15] Himanshu Thapliyal, Saurabh Kotiyal and M.B Srinivas, “Design and analysis of a novel

parallel square and cube architecture based on ancient Indian Vedic mathematics”

Proceeding of 48th Midwest Symposium on Circuit and Systems, 2005.


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[16] Altera Corporation ‘Quartus II user manual’, USA, 2001.


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APPENDIX A. PROGRAMS


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VHDL CODE FOR FULL ADDER

library ieee;

use ieee.std_logic_1164.all;

entity full adder is

port(

A,B,Cin:in std_logic;

Sout,Cout: out std_logic);

end full adder;

Architecture beh of fulladder is

signal S1,C1,C2:std_logic;

begin

S1


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VHDL CODE FOR 4-BIT RIPPLE CARRY ADDER

library ieee;


entity ra4 is

port(a,b:in std_logic_vector(3 downto 0);

c:in std_logic;

s:out std_logic_vector(3 downto 0);

co: out std_logic);

end ra4;

architecture structural of ra4 is

signal cout:std_logic_vector(3 downto 0);

component fulladder is

port(A,B,Cin:in std_logic;

Sout,Cout:out std_logic);

end component;

begin

g1: fulladder port map(a(0),b(0),c,s(0),cout(0));

g2: fulladder port map(a(1),b(1),cout(0),s(1),cout(1));



co


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VHDL CODE FOR 8-BIT RIPPLE CARRY ADDER

library ieee;


entity ra8 is


c:in std_logic;


co: out std_logic);

end ra8;






end component;

begin









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co


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VHDL CODE FOR 16 BIT RIPPLE CARRY ADDER

library ieee;


entity ra16 is


c:in std_logic;


co: out std_logic);

end ra16;






end component;

begin


gen: for n in 1 to 15 generate

gn: fulladder port map(a(n),b(n),cout(n-1),s(n),cout(n));

end generate gen;

co


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Library ieee;


entity ra32 is


c:in std_logic;


co: out std_logic);

end ra32;






end component;

begin




end generate gen;

co


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library ieee;


entity ra64 is


c:in std_logic;


co: out std_logic);

end ra64;






end component;

begin




end generate gen;

co


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VHDL CODE FOR 2 BIT VEDIC MULTIPLIER

library ieee;


entity vm2 is

port(A,B: in std_logic_vector(1 downto 0);

P: out std_logic_vector(3 downto 0));

end vm2;

architecture dataflow of vm2 is

signal Y,Z: std_logic_vector(1 downto 0);

signal x,q,r,s: std_logic;




end component;

begin

x


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library ieee;


entity vm4 is

port(A,B:in std_logic_vector(3 downto 0);

P: out std_logic_vector(7 downto 0)

);

end vm4;

architecture structural of vm4 is

signal al,bl,ah,bh: std_logic_vector(1 downto 0);

signal s0,s1,s2,s3,r1,r2,r3,x,y: std_logic_vector(3 downto 0);

signal c1,c2,c3: std_logic;

component ra4 is


c:in std_logic;


co:out std_logic);

end component;

component vm2 is



end component;


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begin

al


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library ieee;


entity vm8 is



);

end vm8;





component ra8 is


c:in std_logic;


co:out std_logic);

end component;

component vm4 is




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end component;

begin

al


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Output:

Simulation Result of 8!8 Vedic Multiplier by modelsim

= 10111011

= 00100010

= 0001100011010110


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library ieee;


entity vm16 is



);

end vm16;





component ra16 is


c:in std_logic;


co:out std_logic);

end component;

component vm8 is




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end component;

begin

al


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Output:

Simulation Result of 16!16 Vedic Multiplier by modelism

= 1010101010101010

= 1110111011101110

= 00001110001010000010011000001100


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*)


library ieee;


entity vm32 is



);

end vm32;

architecture structural of 32 is




component ra32 is


c:in std_logic;


co:out std_logic);

end component;

component vm16 is



end component;


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**

begin

al


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Outputs:

Simulation Result of 32!32 Vedic Multiplier by modelsim

= 11110000111100001111000011110000

= 11001100110011001100110011001100

= 0011111110111111101111101011111010111110001111110011111101000000


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*,


library ieee;


entity vm64 is



);

end vm64;





component ra64 is


c:in std_logic;


co:out std_logic);

end component;

component vm32 is



end component;


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begin

al


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Outputs:

= 1100110011001100110011001100110011001100110011001100110011001100

= 1010101010101010101010101010101010101010101010101010101010101010

= 000001111000011110000110100001110000010110000110100001001000010111

11010001110110011101010111011011110110011101110111011101111000


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VITA

Supriya Nimmagadda was born in Andhra Pradesh, India. She has graduated with a Bachelor’s

degree in Electronics and Communication Engineering from JNTU University-Kakinada, Andhra

Pradesh, India in May 2011. After completion of her Bachelor’s degree, she worked as teaching

assistant for a few months and later moved to the United States of America in January 2012 to

pursue her Master of Science in Electrical Engineering at Texas A&M University – Kingsville.

She is scheduled to graduate in December 2013.

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