1984ANNUALREPORT COOPERATIVE

RESEARCH

SEMICONDUCTOR RESEARCH CORPORATIONMember Companies

COOPERATIVERESEARCH

The following companies areincluded in the SemiconductorEquipment and MaterialsInstitute, Inc., CHAPTER: MicrionCorporation; MicronixCorporation; Pacific WesternSystems, Inc.; Probe-Rite, Inc.;Pure Aire Corporation.

AT&T Technologies, IncorporatedAdvanced Micro Devices, IncorporatedBurroughs CorporationControl Data CorporationDigital Equipment CorporationE.I. du Pont de Nemours & CompanyE-Systems, IncorporatedEaton CorporationGCA CorporationGTE Laboratories, IncorporatedGeneral Electric CompanyGeneral Instrument CorporationGeneral Motors CorporationGoodyear Aerospace CorporationHarris CorporationHewlett-Packard CompanyHoneywell, IncorporatedIBM CorporationIntel CorporationEastman Kodak CompanyLSI Logic CorporationMonolithic Memories, IncorporatedMonsanto CompanyMotorola, IncorporatedNational Semiconductor CorporationThe Perkin-Elmer CorporationRCA CorporationRockwell International CorporationSEMI, Chapter*Silicon Systems, IncorporatedSperry CorporationTexas Instruments IncorporatedUnion Carbide CorporationVarian Associates, IncorporatedWestinghouse Electric CorporationXerox Corporation

*

The Semiconductor Research Corporationis a consortium of US. companies having acommon interest in accelerating the progressof research in semiconductor technology,broadening the university base, and increasingthe supply of qualified personnel for theindustry.

In February, 1982, articles were filed incor-porating the SRC as a nonprofit organizationto “conduct research which will include scien-tific study and experimentation directed towardincreasing knowledge and understanding inthe fields of engineering and physical sciencesrelated to semiconductors.” The SRC asses-ses its members’ needs for research, developsstrategies to meet these needs, and fundsresearch that is consistent with thesestrategies.

The goals of the research are aimed atproviding an advanced science and tech-nology base leading to development effortsand subsequent industrial use.

Beyond these research goals, the SRC hasa major responsibility for transferring researchresults to its member companies and in helpingthe United States maintain a lead in infor-mation technology.

Although the technical program is primarilyconducted at academic institutions, the SRC’scharter provides for undertaking exploratoryand advanced development programs whereand when appropriate to its goals and itsmembers’ needs.

The SRC is currently supported by 40 U.S.companies who are either suppliers or usersof integrated circuits, or vendors of material orequipment to the industry. The SRC’s Board ofDirectors is elected by the SemiconductorIndustry Association and consists of execu-tives from member companies. Two specialadvisory groups complement the board. TheTechnical Advisory Board, having representa-tion from each member company, providesthe Board and President with a continuingindustrial perspective on the research pro-gram. The University Advisory Committee,drawn from senior faculty of representativeU.S. universities, provides counsel on uni-versity relations, policies and practices.

— SRC Research, Microelectronics Center of N.C.

GEORGE M. SCALISEChairman,

Board of Directors

The SRC has completed its second full year of research funding. Having been involvedsince its inception, I have gained great personal satisfaction in the growth from the originaleleven firms to the current 40. But even more significant, I have seen and felt the effects ofthe SRC on the university research community and on our industry. Two years is a very shorttime for a still relatively small operation to make this kind of impact. Through cooperativeR&D, we are achieving together what we could not do separately!

The SRC was conceived as the U.S. semiconductor industry’s response to the challengeof concerted national research efforts in other countries. Never has that challenge beengreater. Since the SRC’s formation in 1982, the share of the worldwide semiconductormarket held by Japanese companies has increased from 33 percent to 37 percent.Worldwide market share for U.S. companies has dropped from 57 percent to 54 percent. Inselected segments, such as memory, the picture is much worse. It is an ominous trend.

One of the strengths of U.S. manufacturers in worldwide semiconductor trade competitionhas been our ability to innovate. And it is imperative that we maintain that innovator’s edge.However, the industrial community must take full responsibility for taking that innovationinto our factories and to market rapidly.

While we must be aggressive in putting new technology to use, we must be patient interms of our expectations from long-term research. The research we support looks far intothe future. Its purpose is preservation of our species. We cannot, and should not, expectshort-term miracles. It is also important to remember that we are getting a combination ofresearch results and highly trained manpower. If we wanted either one alone, we would havedone it another way.

Although not discussed in this report, a large amount of effort was expended by the SRCtechnical staff in preparation of an industrial research initiative: Project Leapfrog. For avariety of reasons this ambitious program was not initiated in 1984. We are continuing toevaluate options that would allow us to address this type of effort without dilution of ouruniversity research program.

I would like to share with you my vision of 1995 and the effects the SRC will have had onour industry by that time.

The US. semiconductor industry will cross the $100 billion/year level. This industrywill be using many of the devices, processes, concepts, and software that arecurrently being researched through SRC contracts. Over 3,000 professionals whowere supported by SRC-sponsored research will be employed in our industry, activelyproducing products and developing new ones. At least 50 universities will beproducing highly qualified undergraduate and graduate microelectronic engineersand scientists, at least 20 of which would not be involved except for SRC support.Over 1,000 graduate students and 300 faculty will be engaged in SRC research. TheSRC scheme of cooperative research will have been emulated by other industries,and a majority of their academic support will flow through such cooperatives. Thegovernment will recognize the role of the research cooperative and will funnelincreasing percentages of its research funds through these industry-directed efforts.

I would solicit your help in continuing to provide the SRC with the necessary resources tomake this happen, We are a cyclical industry, but we must not let short-term influencesdetermine our long-term future. I know that we are capable of meeting the challenge.

LARRY W. SUMNEYPresident

The forty companies that comprise the current SRC membership represent the bulk ofU.S. capability in integrated circuits and their application. These companies belong to theSRC for a variety of reasons. All of our members recognize the decline in U.S.competitiveness and the need for changes in the way we do business — like cooperativeR&D. Even the U.S. Government’s Office of Technology Assessment is questioning who willfill the role of a surrogate national laboratory for microelectronics and informationtechnology. Many members with small research organizations, concentrating on near-termproducts, recognize the need to invest in a longer range program. Others with significantinternal R&D efforts regard the growth of university faculty and a continuing stream ofqualified graduate students as a major interest. Still others emphasize directing the attentionof the academic community to areas such as manufacturing which have been traditionallyneglected. Trading off these various interests at current budget levels involves quite abalancing act.

In 1983, the Board of Directors encouraged us to begin to broaden this country’suniversity base in microelectronics by funding research at schools that do not yet have anestablished reputation in this field. This was supported by our University AdvisoryCommittee, and today we have contracts at 16 schools in this category. This is necessary ifwe are to have students needed for industry and the faculty necessary to train them. Theseseed efforts have resulted in significant leveraging of our funds through grants by federaland state agencies — as much as 3:1 in some cases. At the same time, we see the need toconcentrate programs requiring state-of-the-art capital equipment at major centers wherecosts can be shared and the faculty exceeds a critical threshold size.

You will note in this year’s report, a continuing change in emphasis and direction in someof our programs as problems are solved, priorities shift, and new opportunities arise. Nextyear will see increased emphasis on manufacturing and process research — fields in whichthe universities must become more involved.

The growth in understanding between industry and university that is occurring as theresult of interaction among our members, faculty and graduate students is most rewarding.Except in a few instances such as national defense and space, the United States has beenrelatively ineffective in mobilizing the academic community. I feel that through the SRC weare beginning to demonstrate that industry and academia can work together on solutionsthat are crucial for the economic survival of the commercial U.S. integrated circuit industry.

Various government agencies have expressed an interest in an appropriate relationshipwith the SRC. Although nothing is solidified, I would expect this situation to be resolved in thecoming year. It is also heartening to note that several of the recommendations of thePresident’s Commission on Industrial Competitiveness describe the type of cooperationembodied in the SRC.

In 1982, an estimated $70 million was provided to universities for integrated circuitresearch but only $7 million was associated with silicon — the backbone of our industry. In1984, we estimate that $23 million will be spent on silicon research at universities, more thanhalf of which is supplied directly by the SRC.

The SRC is beginning to make a difference!

Photo Courtesy of General Electric Company

1984 Research FundingMicrostructure Sciences $5,801,574Manufacturing Sciences $3,544,888Design Sciences $3,974,845

— SRC Research, University o f California a tSanta Barbara

RESEARCH“Setting Long-Term GoalsFor The SemiconductorIndustry”

T h e U.S. semiconductor/computer industry has establishedthe SRC as the organization throughwhich it sets research goals andfuture directions of the technology.This is accomplished jointly by theSRC Technical Advisory Board, itsworking committees, and the SRCtechnical staff. These directions arethen translated into relevant uni-versity research programs by theSRC which subsequently monitorsand guides the research progress,interprets and disseminates theresultant scientific information and,where applicable, transfers tech-nology to the member companiesthrough appropriate vehicles.

Starting in 1982 with a budget of$6 million, the research programhas expanded in scope and direc-tion. In 1984, over fifty researchcontracts totaling $12 million werein place at 37 universities. Currently,more than 180 faculty and 400graduate students are involved inSRC contracts. The program ad-dresses needs for improved per-formance and higher density inte-grated circuits with increased relia-bility, designed in short cycles to befree or tolerant of faults, easilytested, and produced by control-lable manufacturing processes atacceptable costs.

On a more quantitative level thesegoals read; “by 1994 we shall beable to:”

increase complexity 250 foldincrease performance 10,000 folddecrease cost/gate 500 foldmaintain chip reliability of nomore than one failure in 10 millionhours.

These goals must be reachedwith full consideration given to theadditional factors of capital costsper unit area of silicon, waferthroughput and automation, dispos-ability of reaction products, defectintroduction, stability of processes,safety, and increasing wafer size.

Pseudo Three-DimensionalDisplay of EBIC Image of ICSructure—SRC Research, University o f North Carolina

— SRC Research, University o f California a tSanta Barbara

MICROSTRUCTURE SCIENCESGoals

Microstructure Sciences researchencompasses materials, phenomena,devices, circuits, and techniques re-quired to achieve the industry’s 1994complexity and performance goals:

2 x 107 transistors/cm2

50 pico seconds logic gate delay5 femtojoules power-delay product16-bit analog-digital converter at100 MHz.

These goals are being addressedthrough a major effort on the identi-fication and solution of key problemslimiting the development of a 0.25micrometer CMOS technology, andthrough four complementary efforts onoptical interconnect, multilayer inte-grated circuits, high-speed submicronbipolar technology, and III-V high elec-tron mobility transistor/heterojunctionbipolar integrated circuits. Feature sizewill continue to decrease, four levels ofinterconnect will be required, and newconcepts will be needed to overcomethe circuit speed limitation imposed bytoday’s interconnect technology.

0.25 Micrometer CMOSCMOS circuits have the inherent

advantages of low-power dissipation,improved transfer characteristic,greater resistance to soft errors, andenhanced noise immunity. Coupled witha manufacturing cost near parity withNMOS for advanced complexity ULSIcomponents, CMOS has become theMOS technology of choice for theVLSI/ULSI era. Device modeling hasshown that MOS gate lengths of about0.25 micrometer are the practicalscaling limit as contact resistance,interconnect delays, and, eventually,reliability, will limit further size reduc-tion The SRC 0.25 micrometer CMOSresearch thrust is centered at CornellUniversity, with contributing projects atWisconsin, Illinois, Stanford, ColoradoState, Arizona, Yale, and Notre Damewhere particular expertise exists.

During this past year several keyprocesses, models, and fundamentalphysical effects have been elucidated.A 0.5 micrometer minimum feature sizeprocess employing E-beam patterninghas been demonstrated, and 0.25

micrometer minimum feature size MOStransistors have been fabricated.Device models have been formulatedwhich include the effects of ballistictransport in short-channel devices.Selective deposition of tungsten byLPCVD has been demonstrated to pro-duce high-quality Schottky diodes suit-able to fabricate latchup-free CMOS.MoSi2 and WSi2 deposited from hot-wall CVD reactors, and SiO2 and SiOfilms produced from ion cluster beams,have been shown to have acceptablefilm quality. A new protonic interfacetrap has been discovered and identi-fied, and an ion implantation processhas been developed and characterizedwhich inhibits the lateral encroachmentof silicide in small silicide contact areas.Integration of these important elementsinto a total CMOS process will begin inthe coming year.

Optical InterconnectsA potential solution to both interchip

and intrachip communications delay isoptical interconnect. Ill-V light emittersand silicon photodetectors integratedon the silicon wafer are one possibilitywith interlevel dielectric acting as anoptical wave guide. MBE and MOCVDtechniques are being pursued to fabri-cate GaxAI1-xAs quantum-well, light-emitting devices on silicon substratesas an optical interconnect source.GaAs light-emitting diodes integral withsilicon have been made.

Multilayer Integrated CircuitsThe potential for multilayer integrated

circuits is being explored in the SRCresearch program at MIT. The thrust ofthe effort is to produce single-crystalsilicon films on non-crystalline sub-strates at low temperature, and to fabri-cate integrated circuits in these filmsusing low temperature processes.Although a new method (surface-energy-driven secondary grain growth)for producing large crystals has beendeveloped, it does not appear thatusable single-crystal films of sufficientarea in 750-angstrom-thick layers canbe produced below a temperature of800°C. P-channel MOSFETS, fabri-cated as the second-level transistor ofa joint CMOS gate inverter were madeusing a composite Si3N4 on SiO2 gate

dielectric. The devices have a leakagecurrent dependent on gate voltage due tofield-enhanced emission.

High-Speed Bipolar DevicesAlthough CMOS technology is

favored for ULSI circuits, bipolar tech-nology remains important for high-performance analog and high-speeddigital applications. For CPU applica-tions, package design can accommo-date the power dissipation require-ments of emitter-coupled logic circuits.Logic circuits that combine CMOSFET’s with bipolar transistors canoperate at subnanosecond speeds butonly dissipate the fractional milliwattpower level of CMOS. Bipolar totempole drivers, fully oxide-isolated withsidewall base contact and polysiliconemitters, can drive the off-chip capaci-tive loads. Polysilicon emitter researchis underway, and additional projects inbipolar/CMOS and high-speed bipolartechnology are planned.

I I I-V Digital DevicesIll-V technology, in addition to its

well-known, band structure dependentproperties of direct band gap opticalphoton emission and high mobility,provides a flexibility to build devicesusing artificially structured material thatis not available in silicon. Recentresearch in quantum-well lasers andhigh electron mobility transistors hastaken advantage of these properties. Ajoint effort between the University ofCalifornia at Santa Barbara and Stan-ford University is conducting HEMT/HJBT device research. The basic differ-ence between HEMT and MESFETdevices has been explored in terms ofelectrostatic potential that causes asaturation of the diffusion velocityrather than the drift velocity. A HEMTSPICE model has been developed, andthe use of superlattice structures underthe gate has been investigated to elimi-nate deep levels in the n-AIGaAs barrierlayer. MBE growth stop-and-restartcapability has been demonstrated usingInAs as a passivating layer.

The guidance of the MicrostructureSciences Subcommittee has beeninvaluable in the formulation and thereview of SRC research programsduring the past year. The research hasbeen high quality and productive.

GoalsThe research goals in Design

Sciences specify that a chip at 1994levels of complexity (2 x 108 transis-tors) should require no more than sixman-months of design effort to mapfrom high-level description to error-free layout. In addition, the resultingdesign must be economically testableto assure less than 1 in 106 rejects.This design productivity goal exceedscurrent capability by several orders ofmagnitude, and the design fortestabilitygoal is much more aggressive than the‘fault coverage’ metrics often used fortestability today. A more subjectivegoal is the development of new archi-tectures that provide enhanced pro-cessing and memory capabilities, ICtechnology is becoming increasinglyI/O, and interconnect limited and novelarchitectures may offer alternativesolutions. Workstations having twoorders of magnitude more computa-tional power are needed to supportdesign using next generation levels ofIC complexity. Moreover, the designprocess must be moved to higher levelsof abstraction in order to increasedesigner productivity.

SRC research in design methodsincludes work in device and processmodeling. physical design, synthesismethods, design verification, designfor fault tolerance and testability, andnew design concepts for VLSI archi-tectures In 1984, a Request For Pro-posal was issued to expand effort indesign concepts.

Photo Courtesy General Electric Company

DESIGN SCIENCESPhysical Design

The physical design problem is oneof the most important IC design taskssince it deals with the placement ofmacrocells on the chip and the subse-quent interconnection of the macro-cells according to a given net list. Aneffective solution minimizes both thechip area and the length of intercon-nects between the macrocells andthereby enhances yield and perform-ance simultaneously. Approximately 15tasks were underway in 1984 in theSRC Design Sciences research pro-gram across a wide spectrum of algo-rithms and design styles, Examplesinclude: TALIB, an NMOS cell layoutsystem based on knowledge engi-neering principles; algorithms basedon eigenvalue methods for graph bisec-tion; probabilistic search methods forlayout using the simulated annealingparadigm; fast and efficient PLA foldingsoftware; and fundamental channelrouting studies. SRC graduate studentsalso contributed to larger projects suchas MAGIC and BBL.2. The latter twoprograms are now available to U.S.companies from the SRC Center ofExcellence in IC/CAD at the Universityof California at Berkeley.

Device and Process ModelingThe need for accurate models for

short channel MOS devices as well asextraction methodologies to determineparameter values from process meas-urements has served to motivate thedevelopment of the BSIM project atBerkeley. If one accepts the view thatthe actual manufacturing process forIC’s is characterized by statistical dis-turbances that create variations in ICdevice parameters, then analysis toolsare needed to predict the impact ofprocess variability on the circuits’ per-formance. The FABRICS-II softwaretool set has been developed at the SRCCenter of Excellence in IC/CAD atCarnegie-Mellon University to allowevaluation of the impact of processstatistics on design. Process modelssuch as those used in FABRICS arealso providing impetus to the study ofoptimization methods for both circuitand manufacturing control systemdesign.

Design SynthesisIt has been clear for some time that

the designer should enter the designprocess at a higher level in order toincrease productivity. However, mostpast attempts fall short with respect toboth levels of abstraction and densityof design. The design automation effortat Carnegie-Mellon has several pro-jects that address elements of thisproblem, including: DEMETER, a high-level design aid for a computer systemon a chip; a chip interface synthesisproject; MOBY, a module binder thatassociates hardware with data paths;ULYSSES, a CAD knowledge-basedadvisor for tool utilization; and CLEO-PATRA, a natural language interfacefor circuit simulation. In addition, sev-eral other tasks are underway thatfocus on other specialized synthesisapplications: analog-digital signal pro-cessors; silicon compilation fromBoolean equations based on levelgraph heuristics; UNIGRAFIX, aflexiblegraphics interface software system;and hardware compilers based on thegate matrix design style.

Design VerificationAfter an IC layout has been com-

pleted, there remains the very impor-tant issue of verifying that the circuit iserror-free and that it achieves the in-tended functional and performancegoals. SRC research tasks in designverification include circuit simulators(BIASlisp, a Lisp-based circuit simu-lator; RUBICC, an expert circuit critic),timing simulators, logic simulators (E-Logic), design rule checkers, circuit ex-tractors, and a layout profile predictorfor use in estimating device charac-teristics from process parameters andflow (SIMPL2). Software systems aresometimes complemented by the useof hardware accelerators for verifica-tion. At Berkeley, a multiprocessorsystem has been shown to reducecircuit simulation time relative to a com-parable single processor system.

Design for TestabilityThe testing of integrated circuits to

assure that they are fault free to thedegree required by the 1994 goal set isvery difficult and may require lengthy

and expensive test procedures. In thenew SRC Program in Reliable ChipArchitectures at the University ofIllinois/Urbana-Champaign, severalfacets of the design-for-test problemare being addressed. Tasks include: (1)software to automatically generate testpatterns for a wide class of micro-processors, (2) built-in self test formicroprocessors, (3) fault simulatorsthat efficiently evaluate the effective-ness of test procedures, and (4) faulttolerant design procedures for highlyconcurrent matrix and signal processorcomputing arrays. Other research tasksinclude: VICTOR II, an automatic testpattern generator for digital circuits;PLATEST, a generator of automatictest patterns and/or self-test circuitryfor PLA’s; concurrent on-line testingschemesfor microprocessors; testableCMOS speed-independent circuits; anda new technique called Inductive FaultAnalysis that relates physically occur-ring process defects to circuit faults.

VLSI ArchitecturesAnother major area of research is

novel architectures and applicationsfor IC technology. Two processordesign projects — CONDEL (CON-current Directly Executed Languagemachine), and MISP, (Multiple Instruc-tion stream, Shared Pipeline processor)— are currently being supported. A 20nanosecond pipelined floating pointprocessor is being designed using thevery dense NORA CMOS Technology.This effort will be expanded in 1985.

This country has a lead in designsciences. The SRC is fortunate to haveinvolved in its programs a number ofworld-recognized universities and re-searchers Universities are an idealplace to conduct research in designsciences, and the results of thisresearch can often be rapidly trans-ferred to industry. The dedication of theDesign Sciences Subcommittee hascontributed in a major way to the effec-tiveness of this program.

MANUFACTURING SCIENCESGoals

The purpose of the ManufacturingSciences research program is to de-velop a generic technology base thataddresses the effective use of techni-cal, economic, and human resourcesin optimizing production capabilities forintegrated circuits at the cost and withthe quality required. Because the man-ufactuing sciences have not been partof academic research agendas, mucheffort is required to define and initiate aresearch program where none previ-ously existed. inherent in the programis the development of means to attracthigh-quality graduate students andfaculty to semiconductor manufacturingsciences. Packaging and reliability, bothof which suffer from a similar lack ofuniversity attention, are included aspart of the manufacturing scienceseffort.

The ten-year goals of the SRC Manu-facturing Sciences research programare to create manufacturing capabili-ties for the 1994 complex chip tech-nologies defined in the microstructuresciences program. This requires re-ducing defect levels to 0.25/cm2,developing process capabilities andautomation that enable five-fold im-provements in productivity, and keepingcapital costs at acceptable levels, Theperformance of high-speed digital cir-cuits is already limited by packagingfrom both a thermal and electricalviewpoint, and the goals of 100 wattpackages with 400 I/O’s and port•hertzproducts of 1012 are probably conserva-tive. Current levels of reliability with a250-fold increase in the number ofdevices/chip must be maintained.

Fabrication TechnologyThe core Manufacturing Sciences

research program consists of threerelated efforts at the MicroelectronicsCenter of North Carolina (MCNC),Stanford University, and the Universityof Michigan.

The program at Stanford is focusedon modeling and simulation of equip-ment and unit manufacturing opera-tions directed toward the evolution ofmore efficient CAM/CAF tools and themanagement of yield. The initial year ofthis research has concentrated onautomation, micropattern generationand inspection, etching, device andprocess modeling, and testing and yieldmodeling. The automation researchcenters on the development of a repre-sentation language, FABLE, for fabri-cation operations. A sensitive electricalend-point detection method for plasmaetching has been demonstrated, and adefect reduction scheme for lithogra-phy using successive exposuresthrough different but identical reticuleshas been developed.

At Michigan, SRC research is di-rected to automation of selected semi-conductor unit operations. Reactive ionetching is the in i t ia l researchvehicle. In-process sensors, testing,machine vision, expert systems, andmodeling are the subjects of researchduring the first year. A thermal imager,an integrated gas flow controller, andan automated process cell controllerare being developed.

MCNC is integrating a low-tempera-ture, 1.0 micrometer CMOS fabricationcapability. The scaling of vertical dopingprofiles and lateral lithographic dimen-sions is being approached throughtasks on shallow junction formation,extrinsic gettering, plasma contamina-tion and damage, and plasma-assistedoxidation. The fabrication related re-search is addressing the effects ofparticulates, CMOS latchup, and pro-cess integration. It has been found thatB+ implants are preferred over boronfluoride ions and that implant chan-neling necessitates precise wafer ori-entation control. Leakage current inshallow p+/n junctions can be reducedsignificantly by a two-stage annealing

procedure: a low temperature pre-anneal followed by rapid thermalannealing. The incorporation of ger-manium during epitaxial growth toobtain misfit dislocations has beensuccessfully demonstrated for impuritygettering. In the particulate area, meas-urements have been made in cleanrooms down to 10 nanometer particlediameters, and current research isfocusing on the study of particles onwafers.

ReliabilityA research program directed to the

reliability of submicron integrated cir-cuits is underway at Clemson Univer-sity. The three tasks are electromigra-tion, charge trapping, and electrostaticdischarge. During the initial period ofthis research, emphasis has beenplaced on expanding the university’sinstrumentat ion and analyt icalcapability.

PackagingA major effort in packaging was

initiated at the University of Arizona in1984. The goal of this work is a com-puter modeling and simulation schemefor first-level packages based on inter-active thermal and electrical consider-ations. Several existing modelingschemes have been evaluated for theirapplicability to packaging. Particularemphasis is being placed on the induc-tive switching noise and transmissionline problems in high-speed circuits,The program at Stanford on enhancedcooling techniques for VLSI producedthe first technology transfer for SRCresearch with at least two membercompanies proceeding with advanceddevelopment activities. Thermal dissi-pation of 1400 watts/ cm2 was demon-strated in silicon through the use ofliquid-cooled microchannels. This workhas led to other applications on capil-lary hold-down of wafers in vacuumand improved die attach. The Cornellactivities on defects in multilayerceramics is leading to models for con-trolling shrinkage for composites usedin complex packages. A new project onhybrid wafer-scale integration, whichinvolves a silicon wafer as an active

package substrate, was initiated atAuburn University. A Packaging Strat-egy Committee composed of expertsfrom twelve member companies hasbeen instrumental in developing a planfor increased university attention topackaging sciences. Five universitieswill participate in study contractsleading to a major new program in1985.

MetrologyAt the University of North Carolina,

work with digital scanning electronmicroscopy has resulted in a newtechnique (PREBIC) which has beenapplied to the analysis of current-related phenomena in CMOS devices.The acoustical microscopy project atMinnesota continues to evaluate theutility of this instrument for nondestruc-tive analysis of subsurface VLSIstructures.

Manufacturing sciences representsthe SRC’s biggest challenge. It com-bines the largest need expressed byindustry with a major void in academicresearch to date. It is further compli-cated by the fact that the technicalliterature does not represent state-of-the-art industry practice, thus dictatinga diligent educational and motivationaleffort by experts from member com-panies directed to university scientists.

Photo by Tom Tracy; Courtesy o f AdvancedMicro Devices, Inc.

CAD Simulation of CMOS InverterCross Section Using SIMPL-2

— SRC Research, University of California at Berkeley

Photo Courtesy of Eaton Corporation

FUTURE DIRECTIONSGoals

By continuing refocus of establishedresearch thrusts, the SRC is addressingthe near-term needs of its membercompanies. New thrusts are directedto longer range research in the ten-year time frame. Three areas are pre-sently identified, with funding plannedand initiated: “post-shrink“ silicondevices, in-situ manufacturing, andsystem design concepts.

“Post-Shrink” SiliconThe feasibility of building computing

structures of higher performance andcomplexity than can be accomplishedat the limit of 0.25 micrometer silicon ICtechnology has recently been definedby the SRC in a “Post-Shrink” SiliconWorkshop. Through the use of artifici-ally structured materials, systems ofreduced dimensionality may be fab-ricated which exhibit quantum domainphenomena. Distributed computer arch-itecture systems, consisting of quantum-coupled oscillator arrays, may then beenvisioned. Principal contributions tothe “post-shrink” thrust are being madeat Cornell and the University of Cali-fornia at Los Angeles. A theory for theband structure of two-dimensional (pat-terned), ultra-small, periodic superlat-tice structures has been developed;and, three-terminal device structuresbased on a superlattice construct havebeen conceived. Additional projectsare planned.

In-Situ ProcessingAs the sophistication of computer-

aided design tools for the rapid designof integrated circuits and integratedcircuit complexity increases, a greaterportion of the circuits manufacturedwill be custom designs. Artificial intelli-gence applications that require severalorders of magnitude more logic andmemory than provided by the currentgeneration of custom designs andaccelerators can be identified. Thisuse of custom circuits impacts theapproach for future manufacturingsystems; i.e., high-yield, short-cycle-time fabrication (based on in-situ pro-cessing in which the wafer is main-tained in a stable environment and

processes are brought to the wafer)will become increasingly important. TheSRC is establishing a thrust to developan in-situ technology that addressesthis future need. Research programsemploying energy beam processingare underway at Rensselaer Poly-technic Institute, the University ofIllinois, the University of California atLos Angeles, The Johns Hopkins Uni-versity, and Columbia University. Atime-dependent general model de-scribing the incorporation of dopantsinto single-crystal films grown by MBEhas been developed. Prior to attemptingto fabricate superlattice structures,growth of laterally uniform CoSi2 onsilicon by MBE has been achieved.

Design ConceptsAlgorithm design, system architec-

ture, concurrency of operation, anddevice technology are the major ave-nues along which computer scienceand engineering have traditionally pur-sued their central goal of increasingcomputational throughput. In the past,algorithm design has sought to developbetter procedures and data structuresthat will reduce the time to solve specificproblems on a given computing system;concurrency of operation has soughtto achieve a better utilization of avail-able resources by overlapping activitiesthat use disjoint parts of the computingsystem; device technology has ad-vanced along the traditional lines ofreducing the minimum geometries; and,system architecture has constructedthe hardware resources to optimize thesystem for classes of algorithms.Increasing complexity and design capa-bility mean that architectures specificto a given algorithm are affordablethrough custom design. Recognizingthis, the SRC has initiated a thrust toinvestigate and develop advanced arch-itectures that will address identifiedfuture applications.

In late 1984, the SRC began a searchfor innovative design concepts for theULSl/VLSI generation of technologyby issuing a Request for Proposal tothe university community. As a conse-quence of this solicitation, new re-search will be started in 1985 in com-

puting arrays for large chips, highspeed/accuracy analog-to-digital con-version, and new built-in test designmethods. The SRC is continuing toexpand its initiative in the design con-cepts with research in signal pro-cessing architectures, adaptive associ-ative memories, and artificial intelli-gence engines.

GoalsThe activities of the SRC are pro-

viding an opportunity for technical pro-fessionals and managers to becomeinvolved with university researchers,often for the first time. Participation intechnical committees, conferences,and workshops are vehicles for inter-change not found in the large profes-sional societies, Following are some ofthe highlights that characterize thisincreasing involvement and commit-ment of the members.

Technical Advisory Board andSubcommittees

The Technical Advisory Board (TAB)continues to be the major focus ofinteraction and information exchangeamong industry, the SRC staff, and theuniversities. Participation in the Tech-nical Advisory Board and its threesubcommittees doubled in 1984 withthe opportunity for each member com-pany to be represented on each sub-committee. The addition of nine newmember companies during 1984brought new expertise and perspective.The first SRC-TAB planning sessionheld in August resulted in changes inscope and direction of the researchprogram and further quantified thetechnical goals for the 1990’s. Thisannual “summer study” provides con-tinuity in TAB leadership.

Industrial Mentor ProgramThe Industrial Mentor Program in

which technical experts from membercompanies affiliate with individual uni-versity research tasks as resourcepeople is unique to the SRC. Thisprogram is the result of recognition bythe Technical Advisory Board that theuniversity benefits from continuingindustrial perspective and resources.Layouts, mask sets and custom fabri-cation of wafers are examples of ser-vices offered to universities by mem-bers At the request of the TAB, thenumber of mentors was increased from55 to 145 during the year. This wasapplauded by the university community.The mentors gain from real-time inter-action with faculty and students per-forming research relevant to their

OUTREACHspecial interests. Opportunities foradditional mentors will continue to growas the research program expands.

Topical Research ConferencesTopical Research Conferences deal

with a specific topic that is part of theSRC’s ongoing research. They createan environment for active dialogueamong researchers in the field. Manypurposes are served: early access toresearch results, inputs from unpub-lished industrial research efforts, andconstructive critique. During 1984, con-ferences on the following subjects wereheld:

Built-In TestabilityVLSI Interface EngineeringDesign SynthesisDevices and StructuresManufacturing SciencesInterconnections and ContactsRapid Thermal Annealing

Attendance, limited in order to encour-age interaction, averaged 45 personsper meeting. Over 285 different repre-sentatives from member companiesand faculty participated. The confer-ence on Rapid Thermal Annealing wasjudged by leading researchers as thebest forum ever held on the subject.

WorkshopsWorkshops help the SRC decide

whether a new research thrust is appro-priate and where the most fruitfulapproaches lie. Leading researchersare invited from industry, government,and academia to present historicalperspectives, current research, andviews of technology limits and oppor-tunities. For the Wafer-Scale Integra-tion Workshop, survey papers writtenby commission of the SRC reviewedthe history of worldwide research onthis subject while active industrial anduniversity researchers provided a cut-ting edge view. The conclusions wereused to formulate beginning projects inthe new in-situ processing thrust.Workshops on “Post-Shrink” Silicon,Health and Safety, In-Situ Processingand Technology Assessment are sched-uled for 1985.

Technology Transfer CoursesThe product of research is under-

standing and sometimes invention,while technology is usually the result ofdevelopment. Since the SRC is not yetengaged in development, the task is toassist the universities in interpretingthe significance of their research andin defining what needs to be done byindustry to develop technology. In thecase of software and analytical tech-niques, a direct translation can oftenbe made from university research toindustry use. An effective way toaccomplish this for the member com-panies is through short courses givenby the researchers themselves, Thefirst Transfer Course, FABRICS-II, washeld at Carnegie-Mellon University.Due to limitations imposed by labor-atory facilities, attendance was re-stricted. Repeat sessions will be sched-uled to meet all members’ needs. Threeadditional courses are scheduled for1985:

Microstructure CharacterizationTechniques — Cornell

Ill-V HEMT Modeling —Stanford

Analog Design CAD —Georgia Tech

A continuing stream of these eventsis anticipated as the SRC researchprograms progress.

PublicationsPublishing activities increased dra-

matically in 1984. The library now con-tains 800 documents including contractreports and papers, the TechnicalReport Series, proceedings of SRCconferences and workshops, and news-letters Twenty-one company librarieshave established procedures to archiveand distribute SRC information. In addi-tion to regular mailings, individualrequests are being received at the rateof over 400 per month — most of whichare filled within 48 hours.

Information CentralOver 125 people now have direct

access to our VAX 11/780 InformationCentral system. The primary activitiesare electronic mail and requests for

publications. New features are beingadded as this computer capability isupgraded.

The user base will increase as soft-ware support for a variety of terminalsbecomes available from the SRC. Por-tions of the SRC data base are now ontape and available to members forincorporation into internal informationsystems.

Researchers in ResidenceOpportunities are provided for re-

searchers who are employees of mem-ber companies to hold visiting researchfaculty positions at universities that areparticipants in the SRC program. Appli-cants must be approved by the univer-sity, and the residencies are typicallysix months to two years.

Speakers BureauEffective in March, 1985, the SRC

Speakers Bureau will begin operation.Over forty university researchers undercontract to the SRC will be available asvisiting lecturers to member companylocations. Eighty topics are included.This program provides company audi-ences the opportunity to review re-search and to discuss issues of partic-ular relevance to their business.

Industrial Residency at theSRC

The SRC provides the opportunityfor member companies to place Pro-gram Managers on the SRC TechnicalStaff for periods of one to two years.This residency program seeks em-ployees with management and techni-cal expertise in specific fields of interestto the SRC to lend industry perspectiveto the research effort and to help withthe task of monitoring research con-tracts To date, seven specialists fromfive companies have participated.

Photo by Tom Tracy; Courtesy o f AdvancedMicro Devices, Inc.

1984 RESEARCH PORTFOLIO

Arizona, University ofChemical Vapor Deposition of Refractory Metals

and Their Silicides From Solid Sources

Efficient Method for Simulating MOS IntegratedCircuits and Its Implementation in CurrentlyUsed GAD Tools

Electrical Modeling and Simulation of VLSIPackages

Thermal Modeling and Simulation of VLSIPackages

Experimental Characterization of VLSI Packages

Arizona State University

A Three-Dimensional VLSI Device Simulator

Auburn University

Active Silicon Wafer-Scale PackagingTechnology

Brown University

Hierarchical Silicon Compilation

California at Berkeley, University ofGoal-Oriented Hierarchical Building-Block

Layout System

Routing Region Definition and Ordering

Gridless Channel Routing

Routing in MAGIC

YACR-Yet Another Channel Router

Topological Design of Array Logic

Theoretical Analysis of Probabilistic Hill ClimbingMethods for Layout of Integrated Circuits

Graph Bisection Using Multiple Eigenvectors

Global Wire Routing in Two-DimensionalGate-Arrays

Electrical Logic Simulation

Object Oriented Programming in BIASlisp

BLOSIM

SIMPL-2 (SIMulated Profiles from Layout —version 2)

BSIM, an IC Process-Oriented MOSFET Modeland Associated Characterization andSimulation Facility

Nonlinear Device Validation: Hardware andSoftware Aspects

Characterization and Modeling of Intrinsic andExtrinsic Gate Capacitances of Small-Geometry MOSFETs

Scalable, Process-Independent AnalogMacrocells for Analog-Digital VLSI

Expert Systems for Circuit Verification

Software Aids for Programmable Digital SignalProcessors

Flexible Manufacturing Cells for CAM

DELIGHT.MIMO: An Interactive, Optimization-Based Control System Design Package

Information System for a Microfabrication Facility

Low-Pressure Hot-Wall Silicon Epitaxy

Control of Dopant Diffusion in Silicon Dioxide

Stress-Strain Analysis of Oxidation Process forAdvance Isolation Technologies

Antialiasing and Realistic Rendering

Applying Color Science to Raster ComputerGraphics

Berkeley UNIGRAFIX

Testing for Regular Structures and Self-TestingTechniques

Testability Analysis of Digital Circuits

Testability Analysis for Analog Circuits

Software Reliability

MOS Model lmplementation in Next GenerationCircuit Simulation

Transistor Models for BIAS-B/P

Bagel: Berkeley Automatic Gate Array Layout

Automated Parameter Extraction System for theCSIM MOS Device Model

Optimization-Based Design of Robust ControlSystems

Robot Programming and Inverse Kinematics

Hand-Eye Coordination Problems for Robots

Computer-Based Precision A/D ConverterTesting

Floating Point Support for Special-PurposeSimulation Hardware

California at Los Angeles, University ofMBE of Silicides for VLSI Applications

California at Santa Barbara, University ofDevice Physics of III-V Heterojunction Field-

Effect Transistors

Optimization of III-V HeterostructureConfigurations

Laterally-Structured, Multiple-Level MBECapability for Ill-V Devices

Carnegie-Mellon UniversityAn interactive Graphical Process Editor for

FABRICS-II

A Methodology for Optimal Test Structure Design

Analytical Modeling of Small GeometryMOSFET’s

Parameter Estimation for Statistical ProcessCharacterization

PROMISE — A Fabrication Process OptimizationSystem

Interface Specification and Synthesis

DEMETER Project — DA Design Aid forIntegrated Circuit Computer Systems

MOBY — A Module Binder for the CMU-DASystem

Knowledge-based Layout Tools: TALIB

Towards a Natural Language Interface for CAD

ULYSSES — An Environment for VLSI DesignAutomation

Exploitation of Low-Level Concurrency: An IMP

Compilation of MultipIe ProcessorInterconnections

Polysilicon In Advanced Integrated CircuitProcesses

On-Line Testable Processors and Testing ofMOS VLSI Circuits

Clemson UniversityElectromigration in the Pulsed Mode

Charge Injection in Gate Oxides

Latent Electrostatic Discharge Effects

Colorado State University

Low Resistance Ohmic Contacts for VLSITechnology

Columbia University

VLSI Circuit Layout

Cornell University

One-Quarter Micron CMOS Device/CircuitTechnology

High Density Memory Cell Considerations

Multilevel Integrated Circuits

Monolithic Optical Interconnect

Low Resistance Contacts

Reactive Ion Etching

Transmission Lines as Interconnects for VLSI

Ballistic Transport Devices

Laser Photochemistry for In-Situ Processing

“Post-Shrink” Periodic Submicron DeviceStructures

Heat Removal in ICs

Physics of Submicron Scale ElectronConfinement

Noise Mechanisms in Small Devices

Electron Microscopy of Submicron Devices andICs

Defects and Morphology of Interfaces

Polyimide Films for Interlevel Dielectrics

Damage Induced During Plasma Etching

Duke University (See Microelectronics Centerof NC)

Florida, University ofThe Optimization of Polysilicon Emitters for

Bipolar Transistors

Georgia Institute of Technologylnvestigations of Mechanical-Environmental

Interactions in VLSI Bond Interfaces

A Computer-Aided Design Methodology forAnalog LSI/VLSI

Illinois at Urbana/Champaign, University ofInvestigation of Thermal and Accelerated

Dopant/Surface Interactions During VaporPhase Film Growth in VLSI Device Fabricationby MBE

Design Verification and Testing of VLSI Circuits

Design of Testable VLSI Circuits

Reliability Physics of Silicon VLSI Transistors

VLSI Arrays, Applications and Layout Techniques

Automatic Test Generation for Microprocessors

A Fault Simulator Using Multilevel SubscriptedDs

Built-In Self-Test for Microprocessors

Design of a Pipelined Floating-Point Multiplierwith Recursive Fraction Unit

Reducing the Technological Cost of MOS Self-Checking Checkers

Fault-Tolerant Matrix Arithmetic and SignalProcessing on Highly Concurrent ComputingStructures

Design Rule Checker and Circuit Extractor

An MOS Fault Simulator with WaveformInformation

A Multiple Instruction Stream Shared PipelineProcessor

Hierarchical Fault Simulation

Switch-Level Fault Simulation

Timing Verification

Channel Routing Algorithms

General Routing of Multiterminal Nets

Network Partitioning

VLSI Computing Arrays

Global Layout Techniques

Iowa, University ofDevelopment of a Design Automation System for

Speed-Independent Circuits

The Johns Hopkins University

Sources for Cluster Ion Beam Deposition

Massachusetts Institute of Technology

Surface-Energy-Driven Secondary Grain Growthfor Si Epitaxy

Low Temperature Silicon Epitaxy by LowPressure Plasma Enhanced CVD

Laser Induced Chemical Vapor Deposition ofActive and Passive Materials

Plasma Assisted CVD of Refractory Metals andSilicides

Characterization and Modeling of the PlasmaEtching of Polycide Structures

Controlled Heat Transfer for High QualityLiquid-Phase Recrystallization

Study of Stacked Device IC Technology

Ultra-Thin Gate Dielectrics for Scaled CMOSTechnology

Zero Shrinkage Ceramic Tape for IC Packages

Michigan, University of

Sensors and Advanced Instrumentation ForEquipment Diagnostics, Process Control,Wafer Diagnostics, and Process Evaluation

Modeling and Control of Semiconductor Facilities

End-Process Testing for Detection ofManufacturing Defects

Modeling of RIE Process for Characterizationand Control

Application of Machine Vision and LogicalInspection Units to Manufacturing ProcessControl

Expert Systems for VLSI Manufacturing

Microelectronics Center of North Carolina[MCNC] (including work performed by DukeUniversity [DU], North Carolina State University[NCSU], The University of North Carolina atChapel Hill [UNC/CH], and Research TriangleInstitute [RTI])

Ultra-Compaction Techniques for VLSI Layouts[DU, MCNC]

Shallow Junction Formation, Defects, andStructural Stresses [DU, MCNC, NCSU,UNC/CH]

Extrinsic Gettering of Impurities in Silicon Via theIntroduction of Misfit Dislocations [NCSU]

Effects of Plasma-Enhanced Etching Processesand Cleaning on Surface Layer Damage andContamination [NCSU, UNC/CH]

Plasma-Assisted Low Temperature Oxidation.Film Formation and Epitaxy [MCNC, NCSU]

The Role of Particles in Yield Considerations

[RTl]CMOS Latchup Modeling As Related to Process

Limits [DU, NCSU]

Integration of Low Temperature Processing IntoOne Micrometer CMOS Technology [MCNC,NCSU]

Minnesota, University of

Three-Dimensional Integrated Circuits

Very Low Temperature Silicon Epitaxy bySputtering

Application of Acoustic Microscopy to theExamination of ICs

Mississippi State University

Multilevel Interconnect Materials

Reactive Ion Beam Sources for VLSI

North Carolina at Chapel Hill, University of(See also Microelectronics Center of NC)

Transfer of Software Methodology to VLSI Design

Performance and Failure Analysis ofMicroelectronics Devices by Digital ScanningElectron Microscopy

North Carolina State University (seeMicroelectronics Center of NC)

Notre Dame, University of

Optimization of Incoherent Light and CW LaserAnnealing in Si

The Pennsylvania State University

Thermal Nitridation of Silicon

Plasma and Reactive-Ion Etching With FluorineBased Compounds

Purdue University

Advanced Models for Heterostructure Devices,including High-Speed Bipolar Transistors

Rensselaer Polytechnic InstituteProximity Correction for E-Beam Patterning

Electron Beam Annealing

Ion-Cluster Beam Deposition

Mass Spectroscopy Analysis of Ion ClusterBeams

Resist Development for Ion, X-Ray, E-Beam andUV Lithography

Focused Ion Beam Processing

Liquid Metal Ion Sources for FIB

Research Triangle Institute (SeeMicroelectronics Center of NC)

Rochester, University of

CAD Techniques for VLSI Layouts

South Carolina, University of

VLSI Digital Signal Processors

Southern California, University ofLaser Repair of Transparent VLSI Mask

Microfaults

Stanford University

Performance Enhancement of VLSI Through theUse of Advanced Cooling Techniques

Technology of Multilevel Interconnections andContacts for Submicron VLSI

Complementary MESFET Devices for VLSITechnology

Studies of the Origin of Silicon-Silicon DioxideInterface States

High-Level Language for Representation of VLSIFabrication Processes (FABLE)

Process and Equipment Modeling and Simulation

Generic Models for Semiconductor FabricationEquipment

Specialized Test Patterns

A Hierearchical Parameter Distribution ControlSystem: From Equipment to Process Circuit

Heterojunction Field-Effect Transistor Modelingand Development

The Texas A&M University

A Computer-Aided Design Methodology forAnalog LSI/VLSI

Vermont, University of

MOS VLSI at Low Temperatures

Wisconsin, University ofStudies of Silicide Metallizations for VLSI

Yale University

Process-Induced Radiation Effects InSmall-Dimension MOS Devices

Thin Insulators and Their Interfaces inMetal/Insulator/Semiconductor Systems

TECHNICAL ADVISORY BOARDTAB Co-ChairmenJames M. Daughton (Honeywell)Robert M. Burger (SRC)

AT&T Technologies, IncorporatedRichard M. Goldstein2,4

David J. Lando5

Hy J. Levinstein3

Advanced Micro Devices, IncorporatedJ. Philip Downing1,2

Colin W. T. Knight3

George RiggBurroughs CorporationRobert F. Elfant2

Greg GaertnerRakesh Kumar3

Control Data CorporationW. B. Edwards”W. W. Lindemann1,2,5

C. T. Naber3

Digital Equipment CorporationKenneth H. Slater1,2,4*

Don SumnerE. I. du Pont de Nemours & CompanyGrant A. Beske2,5

Denis G. Kelemen3

E-Systems, IncorporatedCharles T. Brodnax1,2,4

Samuel A. MusaEaton CorporationLyle HoppieS. V. Jaskolski2,5

GCA CorporationRobert W. Allison5

Michael W. Powell2,3

GTE Laboratories, IncorporatedJohn H. Blank4

Arthur H. Mones5

Leslie A. Riseberg2,3

General Electric CompanyGary W. Leive4

Kenneth A. Pickar2,3

General Instrument CorporationDon Butler2

General Motors CorporationGary L. Snyder5

Frank S. Stein2,4

J. Charles Tracy3

Goodyear Aerospace CorporationMelvin H. Davis1,2

Carter M. GlassRobert Parker4

Harris CorporationKurt E. Gsteiger5

Thomas J. Sanders2,3

James P. Spoto4

Hewlett-Packard CompanyDirk BartelinkDragan Ilic2,3

Richard Lucic5

Honeywell, IncorporatedJames M. Daughton1,2

Jack S. T. Huang3

Robert PayneIBM CorporationWilliam E. BernierBilly Lee Crowder1,2,5*

James F. Freedman3,4

Intel CorporationAlan Baldwin1,2,3,5

Richmond B. Clover4

Stephen Nachtsheim4

Eastman Kodak CompanyRajinder P. Khosla2,5

Teh-Hsuang Lee4

David L. Losee3

LSI Logic CorporationConrad J. Dell’Oca2

Monolithic Memories, IncorporatedGeorge Kern5

William E. Moss4

Michael Rynne2,3

Monsanto CompanyRobert A. CravanHarold W. Korb1,2,3

Motorola, IncorporatedL. David Sikes1,2,3

National Science FoundationBernie Chern1,2,4

Donald J. Silversmith3

National Semiconductor CorporationJames Harris5

Court Skinner1 , 2 , 3

The Perkin-Elmer CorporationDonald R. Herriott2

Harry Sewell3

RCA CorporationNorman Goldsmith3

Robert D. Lohman2

William M. WebsterRockwell International CorporationMoiz E. Beguwala5

Frank Micheletti2 , 5

SEMI, ChapterJohn Doherty3

Larry A. Kolito2

William Snow5

Semiconductor Research CorporationRobert M. Burger1,2

Silicon Systems, IncorporatedSteven CoopersGary Kelson1,2,4

Greg WinnerSperry CorporationStephen Campbell2,3

Ash Patel4

Texas Instruments IncorporatedDennis D. Buss4

David A. Peterman, Sr.5

G. R. Mohan Rao1,2,3*

Union Carbide CorporationWilliam F. BeachRaymond P. Roberge2,5

Varian Associates, IncorporatedLarry L. Hansen1,2

Jon ThompkinsIra WeissmansWestinghouse Electric CorporationWilliam S. CorakMichael Michael2 , 5

Xerox CorporationDavid Franco4

James C. Vesely2

1TAB Executive Committee2TAB Representative3Microstructure Sciences Subcommittee4Design Sciences Subcommittee5Manufacturing Sciences Subcommittee6Subcommittee Chairman

UNIVERSITY ADVISORY COMMITTEEProfessor David A. Hodges, ChairmanUniversity of California at BerkeleyProfessor Charles E. BackusArizona State UniversityProfessor Stephen W. DirectorCarnegie-Mellon UniversityProfessor David DuminClemson UniversityProfessor Robert M. HexterUniversity of Minnesota

Professor John G. LinvillStanford UniversityProfessor Noel MacDonaldCornell UniversityProfessor Nino A. MasnariNorth Carolina State UniversityProfessor James L. MerzUniversity of California at Santa BarbaraProfessor Paul Penfield, Jr.Massachusetts Institute of Technology

Professor Joseph StachMassachusetts Technology Park Corp.Professor Andrew J. StecklRensselaer Polytechnic InstituteProfessor Ben G. StreetmanUniversity of Texas at AustinProfessor Timothy TrickUniversity of IllinoisProfessor Ken D. WiseUniversity of Michigan

BOARD OF DIRECTORSGeorge M. Scalise, ChairmanAdvanced Micro Devices,

IncorporatedMichael J. CallahanMonolithic Memories,

IncorporatedJon E. CornellHarris CorporationEugene J. Flath*Intel Corporation

Gregory HarrisonNational Semiconductor

Corporation

*Chairman June-November, 1984.

SRC STAFFLarry W. SumneyPresidentRichard D. AlbertsStaff Vice President for Policy and

PlanningRobert M. BurgerStaff Vice President for ResearchRalph K. Cavin IIIDirector, Design SciencesWilliam C. HoltonDirector, Microstructure SciencesD. Howard PhillipsDirector, Manufacturing SciencesBenjamin J. Agusta*(Resident from IBM Corporation)Program Manager, Microstructure

SciencesJeffrey A. Coriale(Resident from Harris Corporation)Program Manager, Microstructure

Sciences

Bob J. JenkinsMotorola, IncorporatedJeffrey C. KalbDigital Equipment CorporationBrian A. HegartyHoneywell, IncorporatedJohn W. LaceyControl Data CorporationPaul R. LowIBM CorporationCarmelo J. SantoroSilicon Systems, Incorporated

John J. Cox(Resident from E. I. du Pont de Nemours

& Company)Program Manager, PackagingJames R. Key(Resident from Control Data Corporation)Program Manager, Technology TransferRichard Lucic*(Resident from Hewlett-Packard

Company)Program Manager, Manufacturing

SciencesPatrick W. Wallace(Resident from E. I. du Pont de Nemours

& Company)Program Assistant, PackagingRalph E. Darby, Jr.Director, AdministrationMichael D. ConnellyManager, Information SystemsBrian T. N. StokesInformation Systems Analyst

Fred SchwettmannHewlett-Packard CompanyTim B. SmithTexas Instruments IncorporatedLarry W. SumneySemiconductor Research

CorporationRichard D. AlbertsSRC (Secretary to the Board,

January-August, 1984)Ralph E. Darby, Jr.SRC (Secretary to the Board

beginning September, 1984)

Richard D. LaScalaContract AdministratorWayne M. WagonerFinancial AdministratorCheryl TaylorFinancial AssistantMarian U. ReganPublications CoordinatorSuzanne C. GwynnePublications CoordinatorKimberly A. OlivePublications CoordinatorKaren A. SpruillTravel and Conference CoordinatorSandra D. ThomasAdministrative AssistantShirley R. FallinSecretary/Word ProcessorTonya R. JohnsonSecretary/Word ProcessorKrista A. SaharicReceptionist/Word Processor

*Returned to company August 1, 1984.

Cover Photos: Microelectronics Center ofN.C., General Electric Co., UC. at SantaBarbara.

Design: Art Works, Inc.Research Triangle Park, North Carolina

COOPERATIVERESEARCH

SEMICONDUCTOR RESEARCH CORPORATION4501 ALEXANDER DRIVE, SUITE 301

POST OFFICE BOX 12053RESEARCH TRIANGLE PARK, NC 27709

(919) 541-9400

SRC Publication No. S85005