1999_MODELING_ENVIRONMENT_HDT

MOD_ENV 3.2 Training Course

Version 1.0 HDT proprietary

MOD_ENV 3.2 T

A I N

G

I N

Version 1.0

May 1999

The contents of this training course are proprietary data of High Design Technology. Use or

disclosure of the information contained in this document is allowed only under written

authorization of High Design Technology.

High

Design

Technology

Copyright 1999 High Design Technology.

All rights reserved.

R



Training course outline 1 MOD_ENV important concepts

2 Creating a model with MOD_ENV

3 Models validation

4 Skeleton file

5 Delay evaluation

1-1



MOD_ENV important concepts

• PRESTO electrical model architecture

• PRESTO models

• Electrical model types

• MOD_ENV electrical modeling


1-2



PRESTO Electrical Model Architecture

1-3

• The models are described as .SUBCKT circuits in SPRINT syntax (spice-like).

• The model architecture is user-definable.

• A set of default architectures is available for typical situations.

• All SPRINT primitives can be utilized within the model and in particular:

– resistors, inductors, capacitors;

– non linear resistors

– time/voltage/current controlled resistors (switches)

– independent or voltage/current dependent sources

– dynamic or static transfer functions

– transmission lines

– time domain scattering parameters (including measure-based data).

• PRESTO allows the definition of hierarchical modeling (max. two nesting levels).



Version 1.0 HDT proprietary 1-4

PRESTO models

• Driver/Receiver – 4-pin models

– Suitable for ICs/PLDs/CONNECTORS I/O descriptions

– Selectable package

• R,L,C,Diodes, nonlinear resistors, voltage generators – 2-pin models

– Suitable to model 2-pin passive components, IC power pins (to simulate the behavior of supply nets, voltage power supply, etc)

• Special Components (SC) – n-pin (n >= 1) models.

– utilized to model the behavior of a whole device, for example a resistive array or an operational amplifier.

– allows the creation of complete electrical/logic/timing descriptions of simple components.




Electrical model types

There are two types of electrical model syntax:

• Sprint model syntax

• MOD_ENV compatible model syntax (A Sprint model Syntax where parameters are replaced by variables that can be

modified within the MOD_ENV environment)


Both models are supported by PRESTO

electrical libraries in same manner

1-5



MOD_ENV electrical modeling

• Allows the definition of PRESTO models in a controlled way starting from a pre-defined set of model architecture without knowledge of SPRINT syntax.

• Models architectures are organized in skeleton files

• Expert users can build-up own model architectures

• Driver/Receiver/Bidir models can be validated within the MOD_ENV environment

• Models can be saved in library and can be, at any time, modified


1-6



Training course outline

2-1

1 MOD_ENV important concepts


3 Models validation

4 Skeleton file

5 Delay evaluation



Mod_env main window

Creating a model with MOD_ENV

Picture related to the

model

Models parameters

Intrinsic model

propagation delay

Input fields (single

value or tables)

Properties of the

model parameters Messages

2-2



Creating a model

The Model->Create command opens a window with the list of the model structures already available in MOD_ENV (skeleton files).

Just select the model (a detailed list is available on MOD_ENV manuals) and press OK to start modeling


2-3



Models parameters

0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 1.80 2.00

TIME[nS]

-1.00 #

-0.80 #

-0.60 #

-0.40 #

-0.20 #

-0.00 #

0.20 #

0.40 #

0.60 #

1MA

2MA

5MA

10MA

20MA

I/O static characteristics. For convention, all

characteristics have the voltage on X axis

Output dynamic characteristics Behavioral characteristics (TDR)

Numbers or strings

•Voltage, currents, impedance, ecc

•filename


2-4



Model scheme example


Example of CMOS driver

Each skeleton model has a

scheme associated to it. The

variable names and a graph

showing the variable shape

are also shown for reference

Static 1-logic characteristic (voltage is on X axis). For

convention the current is negative if sourcing from

the DUT (the driver in this case).

Static 0-logic characteristic (voltage is on X axis). For

convention the current is negative if sourcing from

the DUT (the driver in this case).

Unloaded rising output

waveform (time is on X axis)

Unloaded falling output

waveform (time is on X axis)

Scattering parameter (TDR

analysis) of the output

Default output waveform amplitude (5V for

CMOS, 3.3V for LV, etc)

2-5



Static characteristics • V/I curve with voltage along X axis (for internal

convention)

• Properties available in the skeleton file. Used for an automatic check to avoid conceptual errors: – min/max allowed X

– min/max allowed Y

– sign of samples (positive/negative/any)

– monotonic (positive/negative)


Example of CMOS input Example of CMOS output Example of ECL output

Measurement

scheme

2-6



Dynamic characteristics

• Voltage curve with time along X axis (for internal convention)

• Properties settable in the skeleton file. Used for an automatic check to avoid conceptual errors: – min/max allowed X



– first/last Y value (to force the starting or ending point)


Example of CMOS output

2-7



Behavioral characteristics • TDR (Time Domain Reflectometer) response

(Reflectometer coefficient versus time)

• Properties settable in the skeleton file. Used for an automatic check to avoid conceptual errors: – min/max allowed X



– first/last Y value (to force the starting or ending point)


Measurement

scheme

TDR

BIAS

DUTlaunchcable

biasprobe

power supply

control 0.40 0.60 0.80 1.00 1.20 1.40 1.60 1.80 2.00 2.20 2.40 2.60

TIME[nS]

-1.00 #

-0.80 #

-0.60 #

-0.40 #

-0.20 #

-0.00 #

0.20 #

0.40 #

0.60 #

0.80 #

1.00 ##RHO

A

B

C

D

Example of

CMOS input

behavior

2-8



Data input for electrical modeling

Data can be collected from: – datasheets of components

» technology information

» power supply voltage

» electrical characteristics of component or family

-> Technical experience required

– Measurements

» static characteristics

» dynamic characteristics

» (TDR characteristics)

-> Technical and Laboratory experience required

– Spice models simulated -> Sprint macromodel

» Use of Spice to simulate the measurement setups

-> Spice and Laboratory experience required


2-9






3 Models validation

4 Skeleton file

5 Delay evaluation

3-1



Models validation

Model validation

Before to be saved in library (or in ascii file), a model can be simulated for:

static “0” logic V/I characteristic for drivers;

static “1” logic V/I characteristic for drivers;

dynamic output waveform (unloaded/loaded) for drivers;

• input V/I characteristic for receivers

NOTE: The validation procedure is available for digital Driver, Bidir, 3-state,

Open collector and Receiver only

3-2



Driver validation scheme

Models validation

PDIP14

PDIP16

…

SOIC14

...

Technology:

Cmos 5V

Cmos 3.3V

TTL

ECL

1. Select the Technology (CMOS,

TTL,etc)

2. Select the package

3. Setup test conditions

4. Run simulation

5. View results

3-3



Receiver validation scheme

Models validation

1. Select the Technology (CMOS, TTL, etc)

2. Select the package

3. Setup test conditions

4. Run simulation

5. View results

3-4



View validation results

• Driver: there are three graphical files – stat0.g 0 logic V/I static char.

– stat1.g 1 logic V/I static char.

– dynam.g output waveform

• Receiver: there is only one graphical file: – stat0.g V/I static char.

At the end of the simulation, the graphical window of Sights appears: just

load the file and plot.

NOTE: To display the static characteristics, the Voltage vector must be

assigned to X-axis of Sights (default is Time)

Models validation

3-5



Training course outline 1 MOD_ENV important concepts


3 Models validation

4 Skeleton file

5 Delay evaluation

4-1



Basic concept

Skeleton file

PRESTO models are based on

subcircuits in SPRINT syntax

(Spice-like). This is very flexible,

but requires additional skills in

SPRINT syntax

Models must be easy to

understand and easy to modify by

all users, not only by the person

that wrote the model

SKELETON FILE: a Subcircuit

declaration expressed in SPRINT

meta-syntax

4-2



Skeleton file structure

Skeleton file

Subcircuit

topology

S_MODEL = DRIVER;

DESCRIPTION = CMOS driver with S-param;

RISE_DRVR_DELAY= ;

FALL_DRVR_DELAY = ;

BEGIN_FUNCTION

BITMAP: "cmos_dr_bout.bm"

%PVCC: STATICPWL(SIGN=ANY, SHAPE=MONOTONE_P,

COMMENT="1-logic static char.", XMIN="0",XMAX="10", YMIN="-

500m",

YMAX="500m", NSAMPLE=20, UNITX="Volt", UNITY="Ampere");

…

END_FUNCTION

BEGIN_SUBCKT

*************** CMOS DRIVER BEHAVIOURAL MODEL ***********

.SUBCKT CMOS_DR_BOUT 1 3 10 20

* in out VCC GND

* TDR output behaviour

ASOUT 2 3 30

BOUT 30 0 S11=PWL( %BOUT ) Z0=50 TD=0

* 0-1 waveform

RSWVCC 7 2 1 0 PWL(0V 1e6 0.5V 50 1V .1 2V .1) .3N C=2P

PVCC 7 8 %PVCC C=2P

…

…

.ENDS CMOS_DR_BOUT

*************************************

END_SUBCKT

Variables

of the

model and

properties

The subcircuit topology is

written in Sprint syntax

where the parameters are

defined with variables that

are described in the section

above. The models is stored

in library and the variables

are replaced automatically

before using the model

Type of model and comment

Intrinsic delay of driver (Vih and

Vil for receiver models)

Bitmap associated to the

models showing its

architecture

4-3



Skeleton files

Skeleton file

New model structures can be defined by the user:

• A skeleton file to be placed in:

“installation”/mod_env/rel_32/com/skl”

• A bitmap file to be placed in:

SUN/HP -> “installation”/mod_env/rel_32/com/bmp/unix”

NT -> “installation”/mod_env/rel_32/com/bmp/nt”

NOTE: PRESTO electrical models can be defined directly in SPRINT syntax without

using a MOD_ENV meta-model. It can be useful to build up custom Special Component

that will not be modified in future. Of course these models cannot be modified inside

MOD_ENV environment.

4-4




5-1



3 Models validation

4 Skeleton file

5 Delay evaluation



Model intrinsic delays

Delay evaluation

Intrinsic model

propagation delay

These parameters are not mandatory,

but required to run a successfully PIN-

TO-PIN delay analysis in PRESTO • Applies for

Driver/bidir/opencollector/3-state

models only

• These delays represent the internal

delays of the model between the

digital stimulus application (to the

driver model) and the time when the

output of the model reaches the 50%

of its swing (unloaded conditions)

5-2



Delays calculations

Delay evaluation

CMOS 5V

CMOS 3.3V

TTL

etc

During the Save_in_Lib or Save_in_File procedure, it will be asked to evaluate the

intrinsic delay. Choose YES to start the procedure (suggested). The following

window appears:

Select the model technology and then press RUN

5-3



Delays calculations

Delay evaluation

Output waveform

Driver stimulus

Sights will appear and the file DELAY.g must be loaded

The two delays are represented in

picture and can be evaluated with

the function EVAL available in

SIGHTS

0V

0.5V

1V

threshold

tpLH tpHL

Driver

stimulus

Output

waveform

5-4

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