1January 18, 2006 irk

Rich Katz, Grunt EngineerNASA Office of Logic Design

Some SEE Testing Considerations

for the

RTAX-S Series Devices

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VPUMP

• Can use internal charge pump or external bias– Internal: Ground VPUMP pin

– External: 3.0V ≤ VPUMP ≤ 3.6V

VPUMP Supply Voltage (External Pump)

In low-power mode, VPUMP will be used to access an external charge pump (if the user desires to bypass the internal charge pump to further reduce power). The device starts using the external charge pump when the voltage level on VPUMP reaches 3V. In normal device operation, when using the internal charge pump, VPUMP should be tied to GND.

When VPUMP = 3V, it shuts off the internal charge pump.

3January 18, 2006 irk

Devices

• Test All Devices– RTAX250S (4 small tiles)

– RTAX1000S (9 regular tiles)

– RTAX2000S (16 regular tiles)

– RTAX4000S (when available)

• The devices’ layout is not the same.– In particular, consider the clock distribution system.

– The RTAX250S consists of 4 small tiles, different than the other models.

4January 18, 2006 irk

Clock Testing

• Test All Devices (previous slide)• Many Types of Clocks

– HCLK (4 per chip)• Single Ended• Differential (LVDS or PECL)• Voltage Referenced

– Routed Array Clock (4 per chip)• Single Ended• Differential (LVDS or PECL)• Voltage Referenced

• Use all parts of the chip– Software will disable clock distribution branches that are not used.

• Real-time monitoring required for clock upset detection.

5January 18, 2006 irk

Carry Chain• RTAX-S Introduced Carry Chain

– Hardwired logic

• Very high speed– Any input to carry chain output (FCO): 0.7 ns max for a -1 speed grade

• Must measure propagation of transients through this structure.

RTAX-S Two-Bit Carry Logic

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RTAX-S SuperCluster

RTAX-S architectural elements to be tested.

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I/O UpsetsNon-hardened I/O Cell’s except for clock

“The RTAX-S single-ended, differential, and voltage-referenced I/O structures are not radiation-tolerant and are subject to SEE.”

Source: “RTAX-S Radiation-Tolerant Features andMitigation Techniques,” January 2005, Actel Corporation.

Note: Flip-flops in the I/O Cells are SEU hardened.

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I/O Upsets, 3.3V CMOSNon-hardened I/O’s except for clock

RTAX-S Device

Two stages of a I/O weave using unbonded I/O’s.N pulses will be propagated through the chain and the counters will instrument for upsets on rising and falling edges. On-chip monitors provide sensitive I/O upset detection (although in the radiation environment).

Counter Counter

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Differential I/O Connections

LVDS and PECL use the same circuit topology.

OUTPUT_PECL

INPUT_PECL

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I/O Upsets, DifferentialNon-hardened I/O’s except for clock

RTAX-S Device

Two stages of a differential I/O weave using bonded I/O’s.

N pulses will be propagated through the chain and the counters will instrument for upsets on rising and falling edges. On-chip monitors provide sensitive I/O upset detection (although in the radiation environment).

Counter Counter

Board-level resistors, 4 per differential pair, not shown. Specific resistor values will support either PECL or LVDS I/Os with an identical topology.

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I/O Upsets, Flip-Flops

RTAX-S I/O Cluster

I/O Modules contain input, output, and enable flip-flops. Unbonded I/Os will be used to test the InReg and OutReg flip-flops. EnReg will not initially be tested. These flip-flops are designed with TMR and it’s expected that they are SEU hard.

Like the supercluster, the I/O Cluster also contains TX, RX, and B modules.

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Clock Management

AX instrumentation chip provides both single endedand differential clocks to the RTAX-S DUT.

3.75 ns total delay250 ps steps

CLK2

CLK1

20 MHzProgrammable

Divider Mux

Multiply(1 to 64)

DIVj

Mux

Mux

DUT

DUT

AX PLL

150 MHz 6.7 ns

FREQUNCIES LOW HIGH

/2 10 20 x1/4 5 40 x2 etc. 60 x3 80 x4 100 x5 120 x6 140 x7 160 x8