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Pipelining

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CharacterizePipelines

1) Hardware or software implementation

pipelining can be implemented in eithersoftware or hardware.

2) Synchronous or asynchronous flow Asynchronous pipeline operates like anassembly line: at a given time, each station isprocessing some amount of information. Aasynchronous pipeline, allow a station toforward information at any time.

3) Buffered or unbuffered flow

One stage ofpipeline sends data directly to another one or abuffer is place between each pairs of stages.

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What is Pipelining

A technique used in advanced microprocessors wherethe microprocessor begins executing a second instructionbefore the first has been completed.

- A Pipeline is a series of stages, where some work is doneat each stage. The work is not finished until it haspassed through all stages.

With pipelining, the computer architecture allows thenext instructions to be fetched while the processor is

performing arithmetic operations, holding them in abuffer close to the processor until each instructionoperation can performed.

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How Pipelines Works

The pipeline is divided into segments andeach segment can execute it operationconcurrently with the other segments.

Once a segment completes an operations,it passes the result to the next segment inthe pipeline and fetches the next

operations from the preceding segment.

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Example

Instruction 1 Instruction 2

Instruction 3Instruction 4

X X

XX

Four sample instructions, executed linearly

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Four Pipelined Instructions

IF

IF

IF

IF

ID

ID

ID

ID

EX

EX

EX

EX M

M

M

M

W

W

W

W

5

1

1

1

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Instructions Fetch

The instruction Fetch (IF) stage is responsible forobtaining the requested instruction from memory. Theinstruction and the program counter (which is

incremented to the next instruction) are stored in theIF/ID pipeline register as temporary storage so that maybe used in the next stage at the start of the next clockcycle.

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Instruction Decode

The Instruction Decode (ID) stage is responsible fordecoding the instruction and sending out the variouscontrol lines to the other parts of the processor. The

instruction is sent to the control unit where it is decodedand the registers are fetched from the register file.

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Execution

The Execution (EX) stage is where any calculations areperformed. The main component in this stage is theALU. The ALU is made up of arithmetic, logic and

capabilities.

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Memory and IO

The Memory and IO (MEM) stage is responsible forstoring and loading values to and from memory. It alsoresponsible for input or output from the processor. If thecurrent instruction is not of Memory or IO type than theresult from the ALU is passed through to the write backstage.

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Write Back

The Write Back (WB) stage is responsiblefor writing the result of a calculation,

memory access or input into the registerfile.

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Operation Timings

Estimated timings for each ofthe stages:

InstructionFetch

2ns

InstructionDecode

1ns

Execution 2ns

Memoryand IO

2ns

Write Back 1ns

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Advantages/Disadvantages

Advantages: More efficient use of processor Quicker time of execution of large number of

instructions

Disadvantages: Pipelining involves adding hardware to the chip Inability to continuously run the pipeline

at full speed because of pipeline hazardswhich disrupt the smooth execution of thepipeline.

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Pipeline Hazards

Data Hazards

an instruction uses the result of theprevious instruction. A hazard occurs exactly when aninstruction tries to read a register in its ID stage that anearlier instruction intends to write in its WB stage.

Control Hazards the location of an instruction dependson previous instruction

Structural Hazards two instructions need to access thesame resource

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Data Hazards

IF

IF

ID

ID EX

EX M

M

WB

WB

ADD R1, R2, R3

SUB R4, R1, R5

Select R2 and R3 forALU Operations

ADD R2 and R3 STORE SUM INR1

Select R1 and R5 for

ALU Operations

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Stalling

Stalling involves halting the flow of instructions untilthe required result is ready to be used. Howeverstalling wastes processor time by doing nothing whilewaiting for the result.

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IF

IF

ID

ID EX

EX M

M

WB

WB

ADD R1, R2, R3

SUB R4, R1, R5

IF ID EX M WBSTALL

IF ID EX M WBSTALL

IF ID EX M WBSTALL

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Type of Pipelining

Software Pipelining

1) Can Handle Complex Instructions

2) Allows programs to be reused

Hardware Pipelining

1) Help designer manage complexity

acomplex task can be divided into smaller,

more manageable pieces.

2) Hardware pipelining offers higher

performance

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Type of Hardware Pipelines

Instruction Pipeline - An instruction pipeline is verysimilar to a manufacturing assembly line.

1st stage receives some parts, performs its assembly task,and passes the results to the second stage;

2nd stage takes the partially assembled product from thefirst stage, performs its task, and passes its work to thethird stage;

3rd stage does its work, passing the results to the laststage, which completes the task and outputs its results.

Data Pipeline data pipeline is designed to pass datafrom stage to stage.

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Instruction Pipelines Conflict

It divided into two categories.

Data Conflicts

Branch Conflicts

When the current instruction changes a register that thenext one needed, data conflicts happens.

When the current instruction make a jump, branch

conflicts happens.

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References

http://www.cs.sjsu.edu/~lee/cs147/fall2003/23147L25Pipelining.ppt

http://murray.newcastle.edu.au/users/students/1999/c9311421/pipe.html#s5

http://www.cs.sjsu.edu/~lee/cs147/fall2003/23147L25Pipelining.ppthttp://www.cs.sjsu.edu/~lee/cs147/fall2003/23147L25Pipelining.ppthttp://murray.newcastle.edu.au/users/students/1999/c9311421/pipe.htmlhttp://murray.newcastle.edu.au/users/students/1999/c9311421/pipe.htmlhttp://murray.newcastle.edu.au/users/students/1999/c9311421/pipe.htmlhttp://murray.newcastle.edu.au/users/students/1999/c9311421/pipe.htmlhttp://murray.newcastle.edu.au/users/students/1999/c9311421/pipe.htmlhttp://www.cs.sjsu.edu/~lee/cs147/fall2003/23147L25Pipelining.ppthttp://www.cs.sjsu.edu/~lee/cs147/fall2003/23147L25Pipelining.ppthttp://www.cs.sjsu.edu/~lee/cs147/fall2003/23147L25Pipelining.ppt