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Parallel Adder Recap To add two n-bit numbers together, n full-adders should be
cascaded.
Each full-adder represents a column in the long addition.
The carry signals ripple through the adder from right to left.
Full Adder
B A CIN
COUT SUM
Full Adder
B A CIN
COUT SUM
Full Adder
B A CIN
COUT SUM
B1A1 B0A0B2A2
CIN= 0
Q1 Q0Q2
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Propagation Delay
All logic gates take a non-zero time delay to respondto a change in input.
This is the propagation delay of the gate, typicallymeasured in tens of nanoseconds.
X Y
time
X1
0
Y1
0
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Carry Ripple
A and B inputs change, corresponding changes to CINinputs ripple through the circuit.
Full Adder
B A CIN
COUTSUM
Full Adder
B A CIN
COUTSUM
Full Adder
B A CIN
COUTSUM
B1 A1 B0 A0B2 A2
CIN= 0
Q1 Q0Q2
t = 0, A & B change
t = 30 ns, Adder 0outputs respond
t = 60 ns, Adder 1outputs respond
t = 90 ns, Adder 2outputs respond
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Carry-Look-Ahead
The accumulated delay in large paralleladders can be prohibitively large.
Example : 16 bits using 30 ns full-adders :
Solution : Generate the carry-input signals
directly from the A and B inputs rather thanusing the ripple arrangement.
ns480ns3016 !v
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Designing a Carry-Look-Ahead Circuit
B A CIN
COUT SUM
B A CIN
COUT SUM
B A CIN
COUT SUM
Q2 Q1 Q0
Carry-look-ahead logic
B2A2 B1A1 B0A0
? A 11110000
11111
12
BABABABAC
BABAC
CC
IN
IN
OUTIN
!
!
!
CIN
0000
01
BABAC
CC
IN
OUTIN
!
!
ININCC !
0
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Practical Carry-Look-Ahead Adder The complexity of each CIN term increases with each
stage.
To limit the number of gates required, a compromisebetween carry-look-ahead and ripple carry is oftenused.
Example : 8-bit adder using two four bit adders withcarry-look-ahead.
A0-3 B0-3 CIN4-bit adder
COUT S0-3
A0-3 B0-3 CIN4-bit adder
COUT S0-3
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Overflow What happens when an N-bit adder adds two
numbers whose sum is greater than or equal to 2N?
Answer: Overflow. Example: 6+4 using a three-bit adder.
(6)10 = (110)2 and (4)10 = (100)2
1 1 0
1 0 0
0 1 0 (COUT = 1)
+
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Modulo-2NArithmetic In fact, the addition is correct if you are using
modulo-2N arithmetic.
This means the output is the remainder from dividingthe actual answer by 2N.
An N-bit adder automatically uses modulo-2N
arithmetic.
Example : 3-bits -> modulo-8 arithmetic
523 ! 5remainder085 !z
1046 ! 2remainder1810 !z
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Using Modulo-2NArithmetic
0 1 2 3 4 5 6 7
Conventional arithmetic
Subtracting 2 is equivalent to adding 6Subtracting x is equivalent to adding 8-x
0
1
2
34
5
6
7
163
123710
017
!
!
!
!
Example Sums
+-
Modulo-8 arithmetic
+-
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Twos Complement Using N bits, subtracting x is equivalent to adding 2N-x.
This implies that the number x should be represented as 2N-x.
NB. To avoid ambiguity, when using signed binary numbers,
the range of possible values is:
3 bit example:
122 )1()1( ee NN x
Binary Digits 000 001 010 011 100 101 110 111UnsignedDecimal
0 1 2 3 4 5 6 7
SignedDecimal
0 1 2 3 -4 -3 -2 -1
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Signed Arithmetic Binary arithmetic rules are exactly the same.
Now, however, overflow occurs when the answer is
bigger than 3 or less than -4
0
1
2
3-4
-3
-2
-1
+-
000
001
010
011100
101
110
111 Example: 3 - 1
(3)10 = (011)2
(-1)10
= (111)2
0 1 1
1 1 1
1 1 0 (carry bits)
0 1 0 (sum bits)
+
1
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Signed and Unsigned Numbers
All arithmetic operations can be performed inthe same way regardless of whether the
inputs are signed or unsigned. You must know whether a number is signed
or unsigned to make sense of the answer.
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Twos ComplementConversion
A quick way of converting x to 2N-x is tocomplement all the bits and add one.
Why does this work ? 1122 ! xx NN
Eg. N = 8 and x = (45)10 = (00101101)2
1 1 1 1 1 1 1 1 (2N-1 = 255)
0 0 1 0 1 1 0 1 (45)
1 1 0 1 0 0 1 0 (difference, each bit is complemented)
-
0 0 0 0 0 0 0 1
1 1 0 1 0 0 1 1 (211 = 256 45)
+
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A Binary Subtraction Circuit
Full Adder
B A CIN
COUT SUM
Full Adder
B A CIN
COUT SUM
Full Adder
B A CIN
COUT SUM
B1 A1 B0 A0B2 A2
CIN= 1
Q1 Q0Q2
To calculate A-B, all the bits in B must becomplemented and an extra one added using CIN
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Comparison Whenever the result of an addition passes zero, a
COUT signal is generated.
This can be used to compare unsigned numbers.
BAC
BAC
C
C
OUT
OUT
OUT
OUT
!
u!
!!
u!!
0
1
320132
1211120
1
2
34
5
6
7
+
COUTgenerated
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Zero Flag
NORing the result bits together tests whether all thebits are low i.e. the result is zero.
The resulting signal (or flag) is high only when A = B.
BAZC
BAZC
BAC
BAZ
BAZ
OUT
OUT
e!
"!
u!
{!
!!
.
0
1
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Summary
Carry-Look-Ahead
The speed of the parallel adder can be greatly
improved using carry-look ahead logic.
Subtraction
An adder can be simply modified to performsubtraction and/or comparison.
Next Time Circuits that can either add or subtract and
more.