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2102581 Digital Circuit Design

Suree Pumrin, Ph.D.

Chapter 5Combinational Circuit Design

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Topics

Combinational circuit design with gates, MUX, and decoderCombinational circuit design with PLD devicesCombinational circuit design using VHDL

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Design with Multiplexers

Figure 7-1 (a) Block diagram for an 8-to-1 line Multiplexer (MUX); (b) IEEE rectangular-shape symbol for an 8-to-1 line Multiplexer.

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Shannon’s Expansion TheoremDesigning with Multiplexers revolves around applying a theorem called Shannon’s Expansion Theorem. The theorem can be stated as follows.

1 1 : ( 1 , . . . , ) ( 0 , 2 , . . . , ) 1 ( 1 , 2 , . . . , ) 1T a F X X n F X X n X F X X n X= ⋅ + ⋅

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Example 7-1. Design a circuit using a Multiplexer to implement the followingfunction by applying Shannon’s Expansion Theorem T11a with respect to variables A and B.

( , , )F A B C A BC= + Signal list: F, A, B, C

Figure E7-1

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Figure 7-3 Type 0 Multiplexer design.

Figure 7-4 (a), (b) A type 1 MUX design.

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Figure 7-5 (a), (c) A type 2 MUX design.

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Figure 7-5 (b), (d) A type 3 MUX design.

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Example 7-2. Show a realizable implementation for the Boolean function plotted in the Karnaugh map shown in Figure 7-2a:

1. using gate level logic,

2. using a type 1 MUX design, and

3. using a type 2 MUX design.

Figure E7-210

A type 1 MUX design:

Figure E7-2 (continued)

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A type 2 MUX design:

Figure E7-2 (continued)

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Design with DecodersIn this session we will discuss how to implement Boolean functions using general purpose n-to-2n line Decoders/Demultiplexers (DXs).

The equations for the outputs of a Decoder with n inputs and 2n data outputs is

Figure 7-9 (a) Block diagram for a 3-to-8 line Decoder/Demultilexer (DX or DMUX) (b) IEEE rectangular-shape symbol for a 3-to-8 line Decoder/Demultiplexer.

, 0 2 1ni iD m EN i to= ⋅ = −

where mi is a minterm consisting of n input signals that are applied to the data

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Example 7-6. Design a 4-bit binary-to-gray code converter with the following truth table description.

Using binary signals B3 (MSB) B2 B1 B0 (LSB) and gray code signals G3 (MSB) G2 G1 G0 (LSB) we can write the Boolean functions for the outputs of the code converter in terms of the inputs as follows.

3 (8,9,10,11,12,13,14,15) 3

2 (4,5,6,7,8,9,10,11)

1 (2,3,4,5,10,11,12,13)

0 (1, 2,5,6,9,10,13,14)

G m B

G m

G m

G m

= =

=

=

=

∑∑∑∑

where m = m(B3,B2,B1,B0)

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Figure E7-6

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Design with Programmable Logic Devices (PLD)

Figure 7-20 Generalized programmable logic device (PLD) architecture (for combinational PLDs).

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Combinational PLDs

programmableprogrammablePLA

fixedprogrammablePAL

programmablefixedPROM

OR arrayAND arrayDevice

1. To decrease PC board real estate (less PC board area means less cost) by reducing the package count.

2. To shorten design time (compared to application specific – or custom –ICs (ASICs), PLD implementations can be achieved faster).

3. To allow design changes (reprogramming PLDs is less time consuming than redesigning a complete PC board using random logic or MSI logic devices).

4. To improve reliability (fewer packages means fewer interconnections and thus greater reliability).

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Figure 7-21 Circuit symbology summary for programmable logic devices.

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Figure 7-22 Simple 3-input, 4-output (8x4) programmable read only memory (PROM).

Programmable Read Only Memory (PROM)

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Example 7-11 Show a design using PROM to implement the binary to hexadecimal character generator illustrated by the truth table repeated in Fig. E7-11a. The outputs of the character generator are to be connected via current limiting resistors to a common anode seven-segment display. Assume that the outputs D through A are positive logic signals.

Figure E7-11 (a)

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Figure E7-11 (b)

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Figure E7-11 (c), (d)

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Programmable Array Logic (PAL)

Figure 7-23 Simple 3-input, 4-output programmable array logic (PAL).

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Example 7-12

1. Show a simple PAL design for the four functions mapped in Fig. E7-12a. Use the simple 3-input, 4-output PAL in Fig. 7-23 if the equations will fit. If the equations will not fit, draw a PAL large enough. Generate the fuse-map information for the equations manually. Assume that all the signals are positive logic signals, and that each signal is available in its true form (uncomplemented form).

2. Use a PAL16L8 to implement the four functions mapped in Fig. 7-12a. Generate the fuse-map information for the equations manually.

Figure E7-12 (a)24

Figure E7-12 (b)

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Figure E7-12 (c)

Logic Diagram PAL16L8.

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Figure 7-25

Logic Diagram PAL16R4.

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Figure 7-26

Logic Diagram PALC22V10.

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Programmable Logic Array (PLA)

Figure 7-27 Simple 3-input, 4-output programmable logic array (PLA).

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Figure 7-28

Logic Diagram PLS153.

Field-Programmable Logic Array (18x42x10)

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PLA architecture size

o represents the maximum number of signal outputs

p represents the maximum number of product terms (some of these product terms can be three state output control terms)

i represents the maximum number of signal inputs

i x p x o