2003 International Conference on Characterization and ...

2003 International Conference on Characterization and Metrology for ULSI Technology

CHALLENGES OF ELECTRICAL MEASUREMENTS OF ADVANCED GATE DIELECTRICS IN METAL-

OXIDE-SEMICONDUCTOR DEVICES

Eric M. Vogel¶ and George A. Brown*¶National Institute of Standards and Technology, Semiconductor Electronics Division

*International SEMATECH

March 27, 2003

Material in this presentation is Non-Confidential

4/3/2003 11:40 AM j:\stndpres\template\ISMT.ppt - 2

Overview• Introduction

• C-V Measurement Challenges

• EOT Extraction Challenges

• Interface State Density Measurements

• Extrinsic Defect Density

• Reliability Evaluation Challenges

• Summary


Introduction

• Lots of effects and unknowns, only four terminals! (two on capacitors!)

• We will need many well-chosen measurements to extract our required parameters.


C-V Measurement Challenges• Capacitance measurements with an LCR meter provide two output parameters, an energy-storage component (L or C) and an energy loss component (R or G).

• These are expressed in terms of either a series or parallel equivalent circuit.

A Primer of Capacitive Impedance Measurements

Rs

Cs

Series Circuit Parallel Circuit

CpRp

• They are truly equivalent:

Cs = Cp * (1 + D2)

D = ωRsCs = 1/ωRpCp = 1/Q

• D is called the Dissipation Factor

• Q is called the Quality Factor

• They express the magnitude and phase of the sample’s response to the applied signal.


C-V Measurement Challenges

-1-0.8-0.6-0.4-0.2

00.20.40.60.8

1

0 1 2 3 4 5 6

applied voltagepure capacitor responselossy capacitor responsepure conductance response

Time t = 0

Cp

Gp

Θδ

Θδωt =

Gp CpY = Gp + jωCp

D = Dissipation Factor = tan δ

Applied voltage

• Ideal resistors have a response exactly in phase with the applied voltage (like the green curve).

• Ideal capacitors have a response completely out of phase with the applied voltage (like the pink curve).

• Lossy capacitors, like ultra-thin oxides or some high-k dielectrics, are somewhere in between (like the blue curve).


C-V Measurement ChallengesMeasurement Conditions and Errors

• Applied ac voltages should be close to the thermal voltage (25 mV at room temperature) to maintain the small-signal approximation.

• Open and short-circuit (and perhaps calibrated load) zeroing must comprehend test fixture and cabling. Probe station resonance effects may become important at higher frequencies.

• Light and ambient shielding will be important for some measurements.

• Even with great care taken, errors are an inherent part of all measurements.


C-V Measurement ChallengesMeasurement Conditions and Errors

Frequency (Hz)102 103 104 105 106

Cap

acita

nce

Erro

r (+/

- %)

10-2

10-1

100

101

102

103

104

105

C = 10-11 F, G = 10-3 SC = 10-11 F, G = 10-6

SC = 10-10 F, G = 10-6 S

• A calculation of relative measurement accuracy of the widely used Agilent 4284A LCR meter has been done. It depends upon the measurement frequency and the nominal capacitance and conductance of the sample under test.

• The relative capacitancemeasurement accuracy of an LCR meter decreases with:

→ decreasing frequency→ increasing conductance→ decreasing capacitance

• For some conditions, errors can truly dominate the measurement!


Relationship of LCR Meter Output to Sample Parameters

• In general, we can’t count on LCR meter output parameters to relate directly to our sample parameters.

• Only in the simplified case shown here of a high-quality-factor, low leakage insulator on a resistive substrate can we hope to identify Cs with Coxide, Rs with Rsubstrate in a series-mode measurement.

substrate

oxide

gate

Rs

Cs


Evolution of Sample Equivalent Circuits

• For some samples, capacitive and resistive impedances of the insulator may be comparable, but still greater than the series resistance of the substrate or connections. Here, the parallel equivalent circuit output mode will provide a valid description of the sample.• Eventually, however, all three may become of comparable size, and none can be ignored. We then need a 3-element equivalent circuit.

Gp Cp

Ri

Ci

Rs


Shortcomings of a Two-Element Equivalent Circuit

• Capacitance roll-over is a common consequence of using the two-element Cpmeter output to represent a conductive dielectric on a resistive substrate.

• Use of the three-element model will sometimes yield a valid model of the structure.

0.0E+00

5.0E-07

1.0E-06

1.5E-06

2.0E-06

2.5E-06

3.0E-06

3.5E-06

-2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5Voltage [V]

Spec

ific

Cap

acita

nce

[F/c

m2 ]

A=5.0E-5 cm^2 inv=>accA=5.0E-5 cm^2 acc=>invA = 1.0E-4 cm^2

f = 100 kHz

Go Co

Gs

(Gs + Go)2

Gs2

* Co~~Cp


Shortcomings of a Three-Element Equivalent Circuit

Rs

Ls

-4.0E-11

-3.0E-11

-2.0E-11

-1.0E-11

0.0E+00

1.0E-11

2.0E-11

-2.5 -2 -1.5 -1 -0.5 0 0.5 1Voltage [V]

Cap

acita

nce

[F]

Area = 4.0x10-6 cm2

f = 100 kHzGo Co

• A series inductance in addition to the three-element circuit is necessary to model negative capacitance or capacitance rising above Co.

• The source of the inductance is not clear; it could be a measurement effect or physical phenomenon.


A Distributed Transistor Channel Equivalent Circuit

• This near-ultimate transmission line equivalent circuit was developed by Ahmed, et al.[1] It was used to show that channel lengths less than about 10 µm are needed to assure proper response of devices with 2 nm gate oxides.


Modeling the C-V Measurements with an Equivalent Circuit

• Since a single capacitance measurement yields only two parameters, the real and imaginary parts of the impedance, we will need multiple measurements to solve for the 3, 4, or more elements in our equivalent circuits. Several approaches have been suggested:

• An iterative technique to isolate and evaluate series components [2]

• Use of two measurement frequencies to give four parameters

• For the three-element equivalent circuit [3]

• for the four-element circuit [4]

• Evaluation of transmission line parameters for the distributed equivalent circuit [1]


Determination of EOT and CET• Once an accurate capacitance value representing the dielectric is obtained from the modeling above, values of EOT and CET may be determined.• Definitions:

• EOT (Equivalent Oxide Thickness): The thickness of an SiO2 film having the same specific capacitance as the dielectric film in question, without any effects from quantum confinement or polysilicon depletion in its electrodes.• CET (Capacitance Equivalent Thickness): This thickness determined by computing εSiO2*Area/Cmeaswhere Cmeas is the measured capacitance in inversion or accumulation at some defined voltage.


Significance of EOT, CETEOT:

Because of its independence of device structural effects, this is basically a materials parameter. It is normally evaluated with the device biased in accumulation, where errors involved in its calculation are expected to be minimized.CET:

The simplicity of its calculation suggests that all device-related shortcomings are included in this parameter. It does, however, govern device operating parameters such as drive current. Thus it is usually evaluated in inversion, the operating mode of the device, yielding the parameter CET(inv).


EOT Determination: A Choice of Simulators

Vg (V)-3 -2 -1 0 1 2 3

C ( µ

F/cm

2 )

0.00

0.25

0.50

0.75

1.00

1.25

1.50

UTQuant [30]NIST Schred [32]NCSU [25]NEMO [29]Berkeley [31]

Tox = 2.0 nmNsub = 1018 cm-3

Npoly = 1020 cm-3

n-channel, n-poly gate

• Simulators show a difference of up to 20% in the calculated accumulation capacitance.• This will lead to significant differences in EOT from the same C-V data.• Possible reasons include the use of approximations for quantum effects vs. Schrödinger equation, wave function boundary conditions, and type of carrier statistics. • It is wise to choose one simulator, and always specify it when quoting values.


Interface State Density, Dit

Measurement of interface state density has been one of the greatest challenges in advanced dielectric characterization. This has been because most standard techniques have significant shortcomings for these structures. The standard techniques are1. Terman technique: based on high-frequency C-V stretch-out.

Low sensitivity for thin films, high frequency assumption often not met.

2. High-low frequency C-V: Quasi-static (low frequency) C-V not usually measurable because of high dielectric leakage.

3. AC conductance-frequency: Very sensitive but complicated technique; also leakage-sensitive.

4. Charge pumping: Requires transistor structures, also leakage sensitive, but corrections are possible.


Charge Pumping Measurement

tr tf

Va

Vgbl

0.1 V

• Base-level charge pumping measurement:- fixed amplitude Va, base voltage stepped in 0.1V increments- rise and fall times tr and tf = 100 ns- traps fill from S/D during tr, empty into substrate during tf

• Charge pumping current is given by

f= freq, AG= channel area, Dit= average Dit over ∆E (Ef,inv –Ef,acc)

EDfqAI itGcp ∆=


Leakage Correction: Key to Dit Measurement

• Measure Icp at 1 kHz– “Looks” like DC relative to

1 MHz, 500 kHz, or 100 kHz data

• Subtract 1 kHz Icp data from high frequency Icp data

– Effectively removes DC leakage current

• Use small transistors to reduce leakage current relative to the charge pumping current

– Example: W/L = 10/1 µm

0.E+00

1.E-10

2.E-10

3.E-10

4.E-10

5.E-10

6.E-10

-2 -1.8 -1.6 -1.4 -1.2 -1 -0.8 -0.6Vgbl [V]

Icp

[A]

1MHz100kHz1kHz

0.0E+00

5.0E-11

1.0E-10

1.5E-10

2.0E-10

2.5E-10

3.0E-10

-2 -1.8 -1.6 -1.4 -1.2 -1 -0.8 -0.6Vgbl [V]

Icp

[A]

1MHz-1kHz100kHz-1kHz

0.0E+00

5.0E+09

1.0E+10

1.5E+10

2.0E+10

2.5E+10

3.0E+10

-2 -1.8 -1.6 -1.4 -1.2 -1 -0.8 -0.6Vgbl [V]

Dit [

cm-2

eV

-1]

Dit 1MHz - 1kHzDit 100 kHz - 1 kHz

Cor

rect

edI cp

Dit

2 nm SiO2 gate

Note frequency independence of Dit in the 100 kHz-1MHz range.

Icp


Charge Pumping in High-k DevicesFixed Amplitude-Variable Base Measurement

-1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.20.00.20.40.60.81.01.21.41.61.82.02.22.4

Vpeak = 1.2V

nFET W/L=10/1µmTH75-2072317 #08

1 MHz

100 kHz

10 kHz

Nit [1

010/c

ycle

*cm

2 ]

Vbase [V]

• Frequency dependence of interface state density is a characteristic of many high-k gate stacks.

• It may be interpreted in terms of depth-related time constant variation [5], associated with bulk of interfacial traps.


Extrinsic Defect Density in High-k Films

• Extrinsic defect distributions have been driven to relatively low levels in conventional SiO2 gate dielectrics.•High-k films, because of their structure and deposition conditions, may not have the same low defect densities we have become accustomed to in conventional devices.• In thicker SiO2 films, extrinsic defects are sensed by low oxide breakdown voltage, or early failure on constant-current/voltage stress tests. Such failures are often not easily sensed in high-k films, particularly in large-area devices needed for low defect density resolution.• It has been observed that defects in high-k films often result in a higher level of conductivity over their entire I-V characteristic.


Typical Full-Wafer Current-Voltage Map

• Yield criterion easily identified for a given wafer

Lot/Wafer 1081503-03Area = 5E-3 cm2, 52 units

1E-12

1E-11

1E-10

1E-09

1E-08

1E-07

1E-06

1E-05

0.0001

0.001

0.01

0.1

1

0 0.5 1 1.5 2 2.5 3 3.5 4

VOLTAGE [-V]

CU

RR

ENT

[-A]

DIE 3,1DIE 4,1DIE 5,1DIE 6,1DIE 7,2DIE 6,2DIE 5,2DIE 4,2DIE 3,2DIE 2,2DIE 1,3DIE 2,3DIE 3,3DIE 4,3DIE 5,3DIE 6,3DIE 7,3DIE 8,3DIE 8,4DIE 7,4DIE 6,4DIE 5,4DIE 4,4DIE 3,4DIE 2,4DIE 1,4DIE 1,5DIE 2,5DIE 3,5DIE 4,5DIE 5,5DIE 6,5DIE 7,5DIE 8,5DIE 8,6DIE 7,6DIE 6,6DIE 5,6DIE 4,6DIE 3,6DIE 2,6DIE 1,6DIE 2,7DIE 3,7DIE 4,7DIE 5,7DIE 6,7DIE 7,7DIE 6,8DIE 5,8

71% YIELD

Yield Criterion: Ig(-2V) < -2.0E-6 A


Defect Density Determination: Lot-wafer 1081503-03

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

1.E-06 1.E-05 1.E-04 1.E-03 1.E-02 1.E-01 1.E+00Sample Area [cm2]

Yiel

d Fr

actio

n

Wafer dataPoisson Model

Defect Density = 60 /cm2

Measured Parameter: Gate Current at Vg=-2V52 units/sample area

Extrinsic Defect Density Determination

Poisson Model:Yield = exp -(Area * Defect Density)

D0 = 1/A(0.37)

• Assuming a good fit, defect density equals the inverse of the sample area for which the yield is 37%.

• Preliminary measurements show defect densities ranging from about 1 /cm2 up to as high as 2.7x104 /cm2 or higher. No clear process dependence has yet been established.


Reliability: Defect Distribution in High-k Dielectrics

Time (s)10-6 10-5 10-4 10-3 10-2 10-1 100 101 102

∆Dit/D

it,0

10-3

10-2

10-1

100

CP, F = 104 HzCP, F = 105 HzCP, F = 106 Hz

2.0 nm SiO2

Vg,stress = 4.3 V

Time (s)10-6 10-5 10-4 10-3 10-2 10-1 100 101 102 103

∆D

it/Dit,

0

10-4

10-3

10-2

10-1

100

CP, F = 103 HzCP, F = 104 HzCP, F = 105 HzCP, F = 106 Hz

ZrO2

Vg,stress = 2.75 V

• Interface state density generation under constant voltage stress is compared for ZrO2 and SiO2 FET’s, using charge pumping.• Higher generation rates are observed in the bulk of the ZrO2 film than at its surface; SiO2 shows no frequency (or depth) dependence.• Device parameter drift (e.g. Dit) may be a greater reliability problem in high-k films than dielectric breakdown.


Summary• The low, complex impedance of advanced gate dielectrics forces us to be thorough in our understanding, measurement, and analysis of MIS C-V characteristics.• Multi-element equivalent circuits are required to describe these structures adequately, and parameter extraction requires sophisticated modeling.• Many of our conventional measurement techniques are not applicable to these structures, or detailed correction procedures must be invoked.• The different material properties of high-k dielectrics compared to SiO2 suggest that we may find new primary reliability issues, requiring development of new characterization techniques.


Acknowledgement

The authors would like to thank NIST and International SEMATECH for financial support, and C. Richter, J. Suehle, D. Heh, C.Weintraub, P. Hung, C. Young, and J. Han for valuable discussions.

Certain commercial equipment, instruments, or materials are identified in this paper in order to specify the experimental procedure adequately. Such identification is not intended to imply recommendation or endorsement by the National Institute of Standards and Technology or SEMATECH Inc. d/b/a International SEMATECH, nor is it intended to imply that the materials or equipment identified are necessarily the best available for the purpose.

SEMATECH, the SEMATECH logo, International SEMATECH, and the International SEMATECH logo are registered service marks of SEMATECH, Inc.


References

1. K. Z. Ahmed, E. Ibok, G. C. F. Yeap, Q. Xiang, B. Ogle, J. J.Wortman, and J. R. Hauser, IEEE Trans. Elec. Dev 46, 1650-1655 (1999).

2. E. M. Vogel, W. K. Henson, C. A. Richter, and J. S. Suehle, IEEE Trans. Elec. Dev. 47, 601-608 (2000).

3. K. J. Yang, and C. M. Hu, IEEE Trans. Elec. Dev 46, 1500-1501 (1999).

4. H.-T. Lue, C. Y. Liu, and T. Y. Tseng, IEEE Elec. Dev. Letts. 23, 553-555 (2002).

5. C. Weintraub, E. Vogel, J. R. Hauser, N. Yang, V. Misra, J. J.Wortman, J. Ganem, and P. Masson, IEEE Trans. Elec. Dev. 48, 2754-2762 (2001).

Date post:	02-Oct-2021
Category:	Documents
Upload:	others
View:	1 times
Download:	0 times

2003 International Conference on Characterization and ...

Documents