1
HIGHHIGH--EFFICIENCYEFFICIENCYRF AND MICROWAVE POWER AMPLIFIERS:RF AND MICROWAVE POWER AMPLIFIERS:
HISTORICAL ASPECT AND MODERN TRENDSHISTORICAL ASPECT AND MODERN TRENDS
Dr. Andrei Grebennikov
2009 Radio and Wireless Week
Power Amplifier Symposium
2
HIGHHIGH--EFFICIENCYEFFICIENCYRF AND MICROWAVE POWER AMPLIFIERS:RF AND MICROWAVE POWER AMPLIFIERS:
HISTORICAL ASPECT AND MODERN TRENDSHISTORICAL ASPECT AND MODERN TRENDS
I. POLYHARMONIC CLASS F AND INVERSE CLASS F I. POLYHARMONIC CLASS F AND INVERSE CLASS F POWER AMPLIFIERSPOWER AMPLIFIERS
II. SWITCHEDII. SWITCHED--MODE CLASS E POWER AMPLIFIERSMODE CLASS E POWER AMPLIFIERS
III. III. SWITCHEDSWITCHED--MODE CLASS FE POWER AMPLIFIERSMODE CLASS FE POWER AMPLIFIERS
3
POLYHARMONIC CLASS F AND INVERSE CLASS F POLYHARMONIC CLASS F AND INVERSE CLASS F POWER AMPLIFIERSPOWER AMPLIFIERS
1. Class F: biharmonic and polyharmonic operation modes1. Class F: biharmonic and polyharmonic operation modes
2. Class F with quarterwave transmission line2. Class F with quarterwave transmission line
5. Inverse Class F: biharmonic and idealized operation modes5. Inverse Class F: biharmonic and idealized operation modes
3. Class F : load networks with lumped elements and 3. Class F : load networks with lumped elements and transmission linestransmission lines
4. Class F: LDMOSFET power amplifier design examples4. Class F: LDMOSFET power amplifier design examples
6. Inverse Class F: load networks with lumped elements and 6. Inverse Class F: load networks with lumped elements and transmission linestransmission lines
7. Inverse Class F: LDMOSFET power amplifier design examples7. Inverse Class F: LDMOSFET power amplifier design examples
8. Practical high8. Practical high--efficiency Class F power amplifiersefficiency Class F power amplifiers
4
1. Class F: biharmonic and polyharmonic operation modes1. Class F: biharmonic and polyharmonic operation modes
( ) ∑= −
−−−=N
n ntntt
Iti
,...6 ,4 2
0 1 cos 2 2 cos
32 sin
2 1 ωωωπω
( ) ∑=
+++=N
n ntntt
Vtv
,...7,5 0
sin 4 3sin 34 sin 4 1 ω
πω
πω
πω
rectangular voltage waveform
half-sinusoidal current waveform
Fourier series for:
RL
3f0
f0
Third-harmonic peaking
π 2π ωt
i n = 1, 2
I0
0
π 2π ωt
v n = 1, 3
V0
0
D. C. Prince, “Vacuum Tubes as Power Oscillators, Part III,”Proc. IRE, vol. 11, pp. 527-550, Sept. 1923
5
H. J. Round, “Wireless Telegraph and Telephone Transmission,”U.S. Patent 1,564,627, Dec. 1925
RL
3f0
f0
5f0
1. Class F: biharmonic and polyharmonic operation modes1. Class F: biharmonic and polyharmonic operation modes
π 2π ωt
n = 1, 3, 5
v
π 2π ωt
i
V0
0
I0
n = 1, 2, 4
0
6
For maximally flat waveformscollector current
v/Vc
π
2.0
1.5
1.0
0.5
0 π/2 3π/2 θ
n = 1, 3
cc1 89 VV = cc3
81 VV =
collector voltage
2 .5
i/I0
π
2 .0
1 .5
1 .0
0 .5
0 π /2 3π /2 θ
n = 1 , 2
01 34 II = 02
31 II =optimum values
1. Class F: biharmonic and polyharmonic operation modes1. Class F: biharmonic and polyharmonic operation modes
Voltage harmonic components Current har-monic compo-
nents 1 1, 3 1, 3, 5 1, 3, 5, 7 1, 3, 5, …, ∞
1 1/2 =0.500 9/16 = 0.563 75/128 = 0.586 1225/2048 = 0.598 2/π = 0.637
1, 2 2/3 = 0.667 3/4 = 0.750 25/32 = 0.781 1225/1536 = 0.798 8/3π = 0.849
1, 2, 4 32/45 = 0.711 4/5 = 0.800 5/6 = 0.833 245/288 = 0.851 128/45π = 0.905
1, 2, 4, 6 128/175 = 0.731 144/175 = 0.823 6/7 = 0.857 7/8 = 0.875 512/175π = 0.931
1, 2, 4,…, ∞ π/4 = 0.785 9π/32 = 0.884 75π/256 = 0.920 1225π/4096 = 0.940 1 = 1.000
7
- fundamental current component
1. Class F: idealized operation mode1. Class F: idealized operation mode
2 max
1II =
- fundamental voltage componentπ
cc1
4 VV =
πmaxcc
1 IVP = - fundamental output power
0cc0 IVP = - dc supply power
100% 0
1 ==PPη - collector/drain efficiency
Harmonic impedance conditions:
0
cc2
max
cc11
8 8 I
VIVRZ
ππ===
0 2π
Imax
ωtπ
i
I0
Ideal voltage waveform
Vcc
π 2π0
2Vcc
ωt
v
Ideal current waveform
- dc current componentπmax
0 II =
nZnZ
oddfor even for 0
n
n
∞==
8
v(ωt) = 2Vcc – v(ωt + π)
2. Class F with quarterwave transmission line2. Class F with quarterwave transmission line Cb Vcc
λ/4
vin
R
C0L0
iR
x
l
0
vinciinc
vref iref
iTi
v
- collector voltage
iT(ωt) = iT(ωt + π) = IR⏐sinωt⏐
i(ωt) = IR(sinωt + ⏐sinωt⏐)- collector current
- transmission-line current
Assumptions for transistor:
ideal switch:no parasitic elements
half period is on,half period is off:50% duty cycle
Assumptions for load:
sinusoidal current:ideal L0C0-circuittuned to fundamental
i(ωt) = IR sinωt - load current
iT/I0
1.5
1.0
0.5
0ωt, °30024018012060 0
9
3. Class F: second current and third voltage harmonic peaking3. Class F: second current and third voltage harmonic peaking
L1
Cbypass
C2
Cout
Vcc
L2
Ynet
Matching circuit
with high impedances at harmonics
RL
( ) ( ) 2222
1
222
outnet 1 1 Im
LCLLCLCY
ωωωωω
+−−
−=
out212out
2o
1 512 ,
35 ,
61 CCLLC
L ===ω
( )( )( )
( )( ) 0 9 9 1 9 1
0 4 1
0 1 1
out22022
20out1
20
222201
out22022
20out1
20
=−−−
=+−
=−−−
CLCLCL
LCLL
CLCLCL
ωωω
ω
ωωω
Load network
Circuit parameters
Output reactive admittance:
Three harmonic impedance conditions:
S21 simulation (f0 = 500 MHz)
ImYnet(ω0) = 0
ImYnet(2ω0) = ∞
0.5 1.5 2.0
S21, dB
0
−1
−2
−3
−41.0 f, GHz
0
Qind = 20
ImYnet(3ω0) = 0
10
6 ,
2 31πθπθ ==
θ1
Cbypass
Cout
Vcc
θ2
θ3
Ynet
Matching circuit
with high impedances at harmonics
RL
0.5 1.5 2.0
S21,
0
−10
−20
−30
−401.0 f, G H z
0
Load network
S21 simulation (f0 = 500 MHz)
⎟⎟⎠
⎞⎜⎜⎝
⎛= −
out0
12 3
1tan31
CZ ωθ
Circuit parameters:
Harmonic impedance conditions at collector (drain):
3. Class F: even current and third voltage harmonic peaking3. Class F: even current and third voltage harmonic peaking
ImYnet(ω0) = 0
ImYnet(2nω0) = ∞ImYnet(3ω0) = 0
ideal transmission lines
11
out
L RRm =
Load network with impedance matching
Normalized parameters:
3. Class F: even current and third voltage harmonic peaking3. Class F: even current and third voltage harmonic peaking
3
03
L
ZRq =
333
02out ZCn ω=
λ/4
Cbypass
Cout
Vdd
Z02, θ2
Z03
Znet
RL Rout
λ/12
n 0
5
10
15
20
25
θ2, degree
30
0.2 0.4 0.6 0.8
1.5
3.0
4.5
6.0
7.5
q
m
3
5 7 10
5 7 10m = 3
n 0 60
62
64
66
68
θ2, degree
0.2 0.4 0.6 0.8
q
m = 10
57
m = 5
0.8
1.6
2.4
3.2
70
7
10
12
Drain voltage and current waveforms
4. Class F: LDMOSFET power amplifier design example4. Class F: LDMOSFET power amplifier design example
500 MHz Class F power amplifier with lumped elements
500 Ω
24 V
300 Ω
1.5 kΩ
100 pF
3.5 pF
Pout
1.1 pF6 pF
10 pF
25 nH 2 pF 15 nH
3.6 nH
4.5 nH
Pin
12.5 17.5 20
efficiency, %
10
80
60
20
0 15 Pin, dBm
100
40
22.5
gain, dB 22
20
12
14
16
18
1
2
1
2
0
20
40
vd, V
0 1 2 3 t, nsec
id, A
0.7
0
LDMOSFET:gate length 1.25 umgate width 7x1.44 mm
inductance Q-factor = ∞efficiency - 82% linear power gain > 16 dB
inductance Q-factor = 30efficiency - 71%linear power gain > 14 dB
Output matching
13
500 Ω
24 V
300 Ω
1.5 kΩ
Pout
4.5 pF
50 Ω 45°
100 pF
2.5 pF
Pin
50 Ω 75°
30 Ω90°
30 Ω12°
50 Ω73°
30 Ω30°
50 Ω13°
20
40
vd, V
0 1 2 3 t, nsec
0
1
id, A
12.5 17.5 20
efficiency, %
10
80
60
20
0 15 Pin, dBm
100
40
22.5
gain, dB 22
20
12
14
16
18
500 MHz Class F power amplifier with transmission lines
LDMOSFET:gate length 1.25 umgate width 7x1.44 mm
output power - 39 dBm (8 W)
collector efficiency - 76%
linear power gain > 16 dB
T-matching circuit for output impedance transformation
Drain voltage and current waveforms
Output matching
4. Class F: LDMOSFET power amplifier design example4. Class F: LDMOSFET power amplifier design example
14
Fourier series for:
rectangular current waveform
half-sinusoidal voltage waveform
RL
2f0
f0
Second-harmonic peakingInverse voltage and current
waveforms
5. Inverse Class F: biharmonic and idealized operation modes5. Inverse Class F: biharmonic and idealized operation modes
π 2π ωt
v n = 1, 2
V0
0
π 2π ωt
i n = 1, 3
I0
0 ( ) ∑= −
−−−=N
n ntntt
Vtv
,...6 ,4 2
0 1 cos 2 2 cos
32 sin
2 1 ωωωπω
( ) ∑=
+++=N
n ntntt
Iti
,...7,5 0
sin 4 3sin 34 sin 4 1 ω
πω
πω
πω
A. I. Kolesnikov, “A New Method to Improve Efficiency and to Increase Power of Transmitter (in Russian),” Master Svyazi, pp. 27-41, June 1940
15
Concept of inverse Class F mode was reintroduced for low voltage power amplifiers designed for monolithic applications (less collector current)
- fundamental current
- fundamental voltage
π0max
1 IVP = - fundamental output power
π0max
0cc0 IVIVP == - dc output power
100% 0
1 ==PPη - ideal collector/drain efficiency
I0
π 2π0
2I0
ωt
i
0 2π
Vmax
ωtπ
v
Vcc
ccmax
1 2
2
VVV π==
π0
14 II =Dual to conventional Class F
with mutually interchanged current and voltage
waveforms
Harmonic impedance conditions:
5. Inverse Class F: idealized operation mode5. Inverse Class F: idealized operation mode
0
cc2
0
max11 8
8
I
VI
VRZ ππ===
nZnZ
even for oddfor 0
n
n
∞==
16
5. Inverse Class F with quarterwave transmission line5. Inverse Class F with quarterwave transmission line
Vdd
Z0, λ/4
vin RL
C0 L0
R1 L
20
1 RZR =
quarterwave transmission line as impedance
transformer
sinusoidal current:shunt L0C0-circuittuned to fundamental
RFC
Vdd RL
f0
3f0 5f0 (2n + 1) f0
device is driven to operate as switch
zero impedances at odd harmonic components
quarterwave transmission line as infinite set of series resonant circuits
17
θ1
Cbypass
Cout
Vdd
Z2, θ2
θ3
Matching circuit
with high impedances at harmonics
RL
Ynet
Z3
6. Inverse Class F: second current and third voltage harmonic pe6. Inverse Class F: second current and third voltage harmonic peakingaking
4 ,
3 31
πθπθ ==
0.5 1.5 2.0
S21, dB
0
−10
−20
−30
−401.0 f, G H z
0
S21 simulation (f0 = 500 MHz)
Circuit parameters:
⎥⎥⎦
⎤
⎢⎢⎣
⎡⎟⎠
⎞⎜⎝
⎛ +=−
−1
out 01
2 31 2 tan
21 CZ ωθ
Load network Harmonic impedance conditions at collector (drain):
ImYnet(ω0) = 0
ImYnet(3ω0) = ∞
ImYnet(2ω0) = 0
ideal transmission lines
18
500 Ω
24 V
300 Ω
1.5 kΩ
Pout
6 pF
50 Ω 45°
100 pF
2.5 pF
Pin
50 Ω 75°
30 Ω60°
30 Ω44°
50 Ω63°
50 Ω45°
50 Ω22°
0
20
40
60 vd, V
0 1 2 3 t, nsec-20
1.4
2.1
0.7
0
-0.7
id, A
12.5 17.5 20
efficiency, %
10
80
60
20
0 15 Pin, dBm
100
40
22.5
gain, dB22
20
12
14
16
18
500 MHz inverse Class F power amplifier with transmission lines
Drain voltage and current waveforms
LDMOSFET:gate length 1.25 umgate width 7x1.44 mm
output power - 39 dBm or 8 W
collector efficiency - 71%
Output matching
7. Inverse Class F: LDMOSFET power amplifier design example7. Inverse Class F: LDMOSFET power amplifier design example
500 Ω
24 V
300 Ω
1.5 kΩ
Pout
9 pF
50 Ω63°
100 pF
2 pF
Pin
30 Ω54°
30 Ω65°
30 Ω62°
50 Ω45°
Load network with output matching
19
Optimum load network resistances at fundamental Optimum load network resistances at fundamental for different classes of operationfor different classes of operation
(B)(F)2
1
cc)invF( 2
8
2
RRI
VR πππ===
(B)
1
cc)F( 4 4 RI
VRππ
==Class F :
Inverse Class F :
Class B :
Load resistance in inverse Class F is the highest
(1.6 times larger than in Class B)
Less impedance transformation ratio and easier matching
procedure
1
2cc
1
cc)B(
2
PV
IVR ==
20
Class F GaN HEMT power amplifier with input harmonic control
Class AB biasing with small quiescent current
RC-circuits at the input for stable operation
characteristic impedances Z2 and Z3 are chosen to
provide conjugate impedance matching at fundamental
85% power-added efficiency for 16.5 W at 2 GHz
Input second-harmonic termination circuit is used to provide input quasi-square voltage waveform minimizing device switching time
Pin Pout
Vg 42.5 V
Z2, θ
λ/4
λ/6Z3
λ/4
D. Schmelzer and S. I. Long, “A GaN HEMT Class F Amplifier at 2 GHz with > 80% PAE,” IEEE J. Solid-State Circuits, vol. SC-42, pp. 2130-2136, Oct, 2007.
8. Practical high8. Practical high--efficiency RF and microwave Class F power amplifiersefficiency RF and microwave Class F power amplifiers
characteristic impedance Z2and electrical length θ is
tuned to form third-harmonic tank with output device
capacitance Cds
21
8. Practical high8. Practical high--efficiency RF and microwave Class F power amplifiersefficiency RF and microwave Class F power amplifiers
Inverse Class F LDMOSFET power amplifier with quarterwave line
Class AB biasing with small quiescent current
series L0C0-circuit is tuned to
fundamental
L-type input matching circuit
with shunt variable capacitance
60% drain efficiency for 13 W at 1.78 GHz
F. Lepine, A. Adahl, and H. Zirath, “L-Band LDMOS Power Amplifiers Based on an Inverse Class-F Architecture,” IEEE Trans. Microwave Theory Tech., vol. MTT-53, pp. 2007-2012, June 2005.
Pin
9.85 nH
26 V
Z0 = 13 Ω θ = 90°
Z0 = 50 Ωθ = 4.7°
Pout
0.6-4.5 pF
50 Ω
30 pF
Z0 = 50 Ωθ = 9°
0.4-2.5 pF
C0 L0 Z0 = 50 Ωθ = 46.8°
9.85 nH
3.5 V L-type low-pass output matching circuit
with shunt variable capacitance
22
II. SWITCHEDII. SWITCHED--MODE CLASS E POWER AMPLIFIERSMODE CLASS E POWER AMPLIFIERS
1. Effect of detuned resonant circuit1. Effect of detuned resonant circuit
2. Basic Class E with shunt capacitance2. Basic Class E with shunt capacitance
4. Parallel4. Parallel--circuit Class Ecircuit Class E
6. Class E with quarterwave transmission line6. Class E with quarterwave transmission line
7. Broadband Class E circuit design7. Broadband Class E circuit design
8. Practical RF and microwave Class E power amplifiers8. Practical RF and microwave Class E power amplifiers
3. Generalized Class E load network with finite 3. Generalized Class E load network with finite dcdc--feed inductancefeed inductance
5. Class E approximation with transmission lines5. Class E approximation with transmission lines
23
G. D. Ewing, High-Efficiency Radio-Frequency Power Amplifiers, Ph.D. Dissertation, Oregon State University, June 1964.
RL
1. Effect of detuned resonant circuit1. Effect of detuned resonant circuit
R
L C0
C
E. P. Khmelnitsky, Operation of Vacuum-Tube Generator on Detuned Resonant Circuit (in Russian), Moskva: Svyazizdat, 1962.
anode efficiency of 92-93% for resonant-circuit phase angles of 30-40°: inductive impedance at
fundamental and capacitive at harmonics
resonant frequency f ≈ (1.4-1.5)f0f0 – fundamental frequency
load current lags collector voltageso that series LC0-circuit must appear
inductive at operating frequency
pulsed excitation with highest efficiency for conduction angles
less than 180°
collector efficiency of 94% for 20 W 500 kHz bipolar power amplifier with
50% duty cycle
24
• transistor has zero saturation voltage, zero on-resistance, infinite off-resistance and its switching action is instantaneous and lossless
R C
iC iR i I0
RFC L
v
Vcc
C0L0
Idealized assumptions for analysis:
• total shunt capacitance is assumed to be linear
• loaded quality factor QL of series fundamentally tuned resonant L0C0 -circuit is infinite to provide pure
sinusoidal current flowing into load
• reactive elements in load network are lossless
• for optimum operation 50% duty cycle is used
• RF choke allows only dc current and has no resistance
( ) 0 2 =
= πωω
ttv
( ) 0 2
== πωω
ω
ttdtdv
2. Basic Class E with shunt capacitance2. Basic Class E with shunt capacitance
Idealized optimum or nominal conditions
RFC R
L C0
C
Vcc Vbe vin
L0
25
Optimum circuit parameters :
-1.5 -1
-0.5 0
0.5 1
1.5
60 120 180 240 300
iR/I0
ωt
0
0.5
1
1.5
2
2.5
0 60 120 180 240 300
i/I0
ωt
0 0.5
1 1.5
2 2.5
3 3.5
0 60 120 180 240 300
v/Vcc
ωt
ωRL 1.1525 =
RC
ω1 .18360 =
out
2cc0.5768
PVR =
o945.35 1
tan tan 11 =⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜
⎝
⎛
−−⎟
⎠⎞
⎜⎝⎛= −−
CRRLCR
RL
ωωωωφ
R CV1
L I1 IR
φ
- series inductance
- shunt capacitance
- load resistance
Optimum phase angle at fundamental seen by switch :
Load current
Collector voltage
Collector current
2. Basic Class E with shunt capacitance2. Basic Class E with shunt capacitance
26
Power loss due to non-zero saturation resistance
RC
RFC L
Vcc
C0L0
RC
RFC L
Vcc
C0 L0
rsat
i(τ2)
τ1 τ2
i
2π +τ1
τ
τsw
Rr
VPr
PP sat
2cc
2outsat
dc
sat 365.1 38 ≅≅
12
2sw
dc
sw τ≅
PP
°= 20or 35.0 swτ
Non-ideal switch
For nonlinear capacitances represented by abrupt
junction collector capacitance with γ = 0.5,
peak collector voltage increases by 20%
Power loss due to finite switching time
Nonlinear capacitance
only 1% efficiency loss
For
2. Basic Class E with shunt capacitance2. Basic Class E with shunt capacitance
27
• load network consists of dc-feed inductance L supplying also dc current, shunt capacitor C, series reactance X, bondwire inductance Lb, series
fundamentally tuned L0C0 resonant circuit, and load R
• shunt capacitor C can represent intrinsic device output capacitance and external circuit capacitance
• active device is considered as ideal switch to provide instantaneous device switching between its on-state and off-state operation conditions
( ) 0 2 =
= πωω
ttv
( ) 0 2
== πωω
ω
ttdtdv
Optimum ideal voltage conditions
across switch:
( ) ( ) sin RR ϕωω += tIti - sinusoidal current in load
3. Generalized Class E load network with finite dc3. Generalized Class E load network with finite dc--feed inductancefeed inductance
RL C
Vcc
C0 L0 Lb
jX
• series reactance X can be positive (inductance), zero and negative (capacitive)
28
- second-order differential equation
where
( ) ( )( )
( ) ( ) 0 cos Rcc2
2
b2 =+−−++ ϕωωω
ωωω tLIVtvtd
tvdLCLL
( ) ( ) ( ) ( )ϕωωωω cos 1
1 sin cos 2
2
2 1cc
+−
−++= tqpqtqCtqC
Vtv
( ) , /1 b CLLq += ω
and coefficients C1 and C2 are defined from initial conditions
, cc
R
VLIp ω
=
3. Generalized Class E load network with finite dc3. Generalized Class E load network with finite dc--feed inductancefeed inductance
- dc-feed inductance
- shunt capacitance
- load resistance2
b
out
2cc
22
2 1/ sin cos2 2
2
1 ⎟⎠⎞
⎜⎝⎛ +⎟⎟
⎠
⎞⎜⎜⎝
⎛−+=
LL
PV
pR ϕπϕπ
π
⎟⎟⎠
⎞⎜⎜⎝
⎛−+⎟
⎠⎞
⎜⎝⎛ += ϕϕ
ππω sin cos 2 2
/ 1 b
pLLp
RL
RL
LLqCR ωω 1 / 1 b2 ⎟⎠⎞
⎜⎝⎛ +=
29
q ≤ 0.5: close to Class E with shunt capacitance with positive (inductive) series
reactance (X > 0)
3. Generalized Class E load network with finite dc3. Generalized Class E load network with finite dc--feed inductancefeed inductance
5
10
15
20
0
-5
0
20
40
60
80
-20
p ϕ,°
0.8 1.1 1.4 1.7 q
0.5
1.0
1.25
0.8 1.1 1.4 1.7
0.75
ωCR
0.25
0.5
1.0
1.25
0.75
0.25
q0.5
RPout /Vcc2
Normalized load network parameters versus q = 1/ω√ LC, Lb = 0
0
10
15
-10
-15
0.8 1.1 1.4 1.7
ωL/R
5
-5
1.5
1.0
0.5
0
-0.5
-1.0
-1.5
X/R
q
q = 1.412: parallel-circuit Class E with zero reactance (X = 0) – maximum load resistance R
q = 1.468: maximum shunt capacitance C(maximum operating frequency fmax) with
negative (capacitive) reactance (X < 0)
30
RL C
Vccvin
C0L0 φ
4. Parallel4. Parallel--circuit Class Ecircuit Class E
To define three unknown parameters q, ϕ and p, two ideal optimum conditions and third equation for zero reactive part of fundamental Fourier component are applied resulting to system of three algebraic equations:
412.1 =q
°= 5.1551 ϕ
.2101 =p
( ) 0 2 =
= πωω
ttv ( ) 0
2
== πωω
ω
ttdtdv
0.732 ωRL =
RC
ω685.0 =
out
2cc 1.365
PVR =
Optimum circuit parameters :
- parallel inductance
- parallel capacitance
- load resistance: highest value
in Class E
( ) ( ) ( ) 0 cos 1 2
0X =+−= ∫ tdttvV ωϕωω
π
π
31
-1
0
1
120 ωt
iR/I0
240
-1
0
1
2.5
180
ωt
iC/I0
RC L
IX
IR
VR
φ
°=⎟⎠⎞
⎜⎝⎛ −=⎟⎟
⎠
⎞⎜⎜⎝
⎛= −− 244.34 tan tan 1
R
X1 RCL
RII ω
ωφ
0
1
2.5
180 ωt
i/I0
0
2
3.5
180 ω t
v/V cc
Load current
Collector voltage
Collector current
Current through capacitance
4. Parallel4. Parallel--circuit Class Ecircuit Class E
Inductive impedance at fundamental
32
5. Class E with transmission lines: approximation5. Class E with transmission lines: approximation
( )o49.052 tan 1 net1 jRZ +=
2
π 2π0 ωt
v/Vcc
3
1
3π 4π
RL
Vcc
CbMESFET output l1
l2Cout
Znet
Optimum impedance at fundamental seen by device :
Two-harmonic collector voltage approximation
electrical lengths of transmission lines l1 and l2should be of 45° to provide
open circuit seen by device at second harmonic
transmission-line characteristic impedances
are chosen to provide optimum inductive
impedance seen by device output at fundamental
T. B. Mader and Z. B. Popovic, “The Transmission-Line High-Efficiency Class-E Amplifier,” IEEE Microwave and Guided Wave Lett., vol. 5, pp. 290-292, Sept. 1995.
33
Znet(ω0)
Znet(2ω0)
Znet(3ω0)
0
1
2
0.0 0.2 0.4 0.6 0.8 1.0 t, nsec
vc/Vcc
3
-1
0
1
0.0 0.2 0.4 0.6 0.8 1.0 t, nsec
ic, A
2
3
on off on
30 Ω , 8°
Cout
3.5 V
5 pF 4 pF 50 Ω
50 Ω 12°
50 Ω , 16° 10 pF
Znet
Transmission-line parallel-circuit Class E GaAs HBT
power amplifier for handset application
Collector voltage
Collector current
Current flowing through collector
capacitor
parameters of parallel transmission line is chosen to realize optimum inductive impedance at fundamental
output matching circuit consisting of series
microstrip line with two shunt capacitors should
provide capacitive reactances at second and
third harmonics
5. Class E with transmission lines: approximation5. Class E with transmission lines: approximation
34
( ) 0 2 =
= πωω
ttv
( ) 0 2
== πωω
ω
ttdtdv
Optimum voltage conditions across switch:
R
λ/4
C
Vcc
v
C0L0
L
i
iC
iRiT
iL
vT
( )( )
( ) ( ) 0 sin 2
RC
2
2C
2
=+++ ϕωωωω tItiqtd
tid - second-order differential equation
( ) ( )πωπω RtC 2 iti ==
( )( ) ( )ϕ
ωωω
πω
cos Rcc
t
C IL
Vtdtdi
−==
Boundary conditions:
649.1
sinusoidal load current
50% duty cycle
=q °= 40.8- ϕ.3021 =p
LCq ω/1 =cc
R VLIp ω
=
6. Class E with quarterwave transmission line6. Class E with quarterwave transmission line
35
6. Class E with quarterwave transmission line6. Class E with quarterwave transmission line
1.349 ωRL =
RC
ω2725.0 =
out
2cc 0.465
PVR =
Optimum circuit parameters :
- series inductance
- shunt capacitance
- load resistance
Load current
Collector voltage
Collector current
Current through capacitance
Current through transmission line
0
1.5 2.5
60 180 300 ωt,°
i/I0
-2.0
-1.0
0
1.0
2.0
60 180 300
ωt,°
iR/I0
0
1.5
3.5
60 180 300
v/Vc
ωt,°
-1.5
0
1.5
2.5
60 180 300ωt,°
iC/I0
0
1.0
2.0
60 180 300 ωt,°
iT/I0
36
Optimum impedances at fundamental and harmonics for different Class E load networks
6. Class E with quarterwave transmission line6. Class E with quarterwave transmission line
Class E with shunt capacitance
Class E with parallel circuit
Class E with quarterwave transmission line
f0 (fundamental) Class E load network 2nf0
(even harmonics)(2n+1)f0
(odd harmonics)
C
L
R
C
L
R
C L R
C C
C L C L
C L C
37
Input load network admittance
7. Broadband Class E circuit design7. Broadband Class E circuit design
Rout C L R
C0 L0
Zin
Device output
ω0
ω
2 1
Xin = ImZin
⎟⎟⎠
⎞⎜⎜⎝
⎛′+
++=0
in 1
1
LjRLjCjY
ωωω
1 2
20⎟⎟⎠
⎞⎜⎜⎝
⎛−=′ωωωω 000 /1 CL=ω
( ) 0 Im
0
in ==ωωω
ωdYd
0 2 1 20
2 =−+RL
LC
ω
1.026 0 ωRL =
02
0 1/ LC ω=
Reactance compensation load network
Reactance compensation principle
1 - impedance provided by series L0C0 resonant circuit
2 - impedance provided by parallel LC resonant circuit
summation of reactances with opposite slopes results in constant load phase over broad frequency range
To maximize bandwidth:
Optimum parameters for series resonant circuit in Class E mode
38
7. Broadband Class E circuit design7. Broadband Class E circuit design
20 nH
28 V
50 Ω
1.5 kΩ10 nF
20 pF Pout
10 pF10 pF
10 nF
50 nH 1 nF 64 nH
62 nH
Pin
110 nH10 pF
300 Ω
120 160 180
efficiency, %
100
74
72
70
68140 f, MHz
76gain, dB
9.5
10.0
10.51
2
20
40
60
80
vd, V
0 3 6 9 t, nsec0
1.0
1.5
0.5
0
-0.5
id, A
Broadband Class E power amplifier with reactance compensation
f0 = 120…180 MHz
Drain voltage and current waveforms
LDMOSFET:gate length 1.25 um
gate width 7x1.44 mm
1 - drain efficiency > 71%2 - power gain > 9.5 dB
input power - 1 Winput VSWR < 1.4gain flatness ≤ ± 0.3
39
High power LDMOSFET RF Class E power amplifier
Class B with zero quiescent current
L-type output transformer to match optimum 1.5 Ω output
impedance to 50 Ω load
series inductance and ferrite 4:1 transformer is required to match
device input impedance
70% drain efficiency for 54 W at 144 MHz
Pin
12 nH 24 nH Pout
50 Ω
120 pF
55 pF
MRF183
100 nH
20 V
4:1
100 pF
required value of Class E shunt capacitance is provided by device
intrinsic 38 pF capacitance and external 55 pF capacitance
quality factor of resonant circuit was chosen to be sufficiently low (∼ 5 ) to provide some
frequency bandwidth operation and to reduce sensitivity to resonant circuit parameters
H. Zirath and D. B. Rutledge, “An LDMOS VHF Class-E Power Amplifier Using a High-Q Novel Variable Inductor,” IEEE Trans. Microwave Theory Techn., vol. 47, pp. 359-362, Dec. 1999..
8. Practical RF and microwave Class E power amplifiers8. Practical RF and microwave Class E power amplifiers
40
8. Practical RF and microwave Class E power amplifiers8. Practical RF and microwave Class E power amplifiers
74% power-added efficiency for 11.4 W at 2 GHz
H. G. Bae, R. Negra, S. Boumaiza, and F. M. Ghannouchi, “High-Efficiency GaN Classs-E Power Amplifier with Compact Harmonic-Suppression Network,” Proc. 37th European
Microwave Conf., pp. 1093-1096, 2007.
Pin Pout
Vg 50 V
λ/4
λ/12Z3
λ/4 TL1
Z2 λ/8
Transmission-line low-harmonic GaN HEMT Class E power amplifier
Class C biasingπ-type
low-pass input
matching
short transmission line TL1provides required series
inductive reactance
output open-circuit stubs are tuned to be quarterwave
at 2nd and 3rd harmonics and capacitive at
fundamental
characteristic impedances Z2and Z3 are chosen to provide load matching together with
series line TL1
Input second-harmonic termination circuit is used to provide input quasi-square voltage waveform
minimizing device switching time
41
III. SWITCHEDIII. SWITCHED--MODE CLASS FE POWER AMPLIFIERSMODE CLASS FE POWER AMPLIFIERS
1. Basic load network and operation principle1. Basic load network and operation principle
2. Load network parameters and voltage and current 2. Load network parameters and voltage and current waveformswaveforms
3. Design approximations with second3. Design approximations with second--harmonic control harmonic control (Class EF(Class EF22) and third) and third--harmonic control (Class E/Fharmonic control (Class E/F33))
42
1. Basic load network and operation principle1. Basic load network and operation principle 2Vcc
C0
R
Cb
L0
C
C
L
Vcc
C0
R
Cb
L0
Z0, λ/4
C
L
( ) 0 2 =
= πωω
ttv
( ) 0 2
== πωω
ω
ttdtdv
Idealized optimum conditions
transistor has zero saturation voltage, zero on-resistance, infinite off-resistance and its switching action is instantaneous and lossless
Class E idealized optimum conditions applied to Class F mode affected by shunt parasitic
capacitance, with added series inductancesymmetrizing action of shunt quarterwave line provides
its voltage inverter mode resulting in similar waveform as in Class D or Class DE: it stores voltage waveform in
traveling wave along its length which returns delayed by one-half fundamental period and inverted due to reflection
from short-circuited end
Class DE Class FE
43
1. Basic load network and operation principle1. Basic load network and operation principle
C
iC iR
iT L
Vcc
C0 L0
VR
VL
v
i
Sw R
λ/4
0 ωt
0
iC/I0
ωt
0 ωt
0 ωt
π 0 ωt 2π
τd τd
iT/I0
i/I0
3.0
2.0
1.0
v/Vcc
1.0
2.0
π 2π
1.5 1.0
0.5
π 2π
2π
π
1.5 1.0
0.5
iR/I0
-0.5
-1.0 -1.5
C
iC iR
iT L
Vcc
C0L0
VR
VL
v
i
Sw R
λ/4
switch is turned on
switch is turned off
dead time during charging or discharging process when current flow through shunt
capacitance
zero initial phase and duty cycle D < 0.5
half-wave symmetry of transmission-line current waveform: line attempts to do same
work in first and second halves of cycle
44
2. Load network parameters and voltage and current waveforms2. Load network parameters and voltage and current waveforms
Class E with shunt capacitance
Class F with quarterwave line
f0 (fundamental) High-efficiency mode 2nf0
(even harmonics)(2n+1)f0
(odd harmonics)
C L
R C C
R short open
C L
R Cshort Class FE with quarterwave line
Vcc
C0
R
Cb
L0
Z0, λ/4
C
L
RC
ωπτ 1 sin d
2
=
ωττττ RL
d2
dd d
sincossin −
=
( )out
2cc
2
2dcos 1 2
PVR
πτ+
=
timedead - dτ
- series inductance
- shunt capacitance
- load resistance
Optimum circuit parameters :
Optimum impedances at fundamental and
harmonics for Class F, Class E and Class FE
load networks
45
Class E2F (or F2E) power amplifier
Vdd C
C0
R
L0 L
L2
C2
v
i I0
0 ωt
π 0 ωt
i/I0
4.0
2.0
v/Vdd
1.0
2.0
π 2π
2π
( ) 0 2 =
= πωω
ttv
( ) 0 2
== πωω
ω
ttdtdv
Idealized optimum conditions
transistor has zero saturation voltage, zero on-resistance, infinite
off-resistance and its switching action is instantaneous and lossless
ideal Class E load network with shunt capacitance
series resonant L2C2 circuit tuned to second harmonic
3. Design approximations with second3. Design approximations with second--harmonic control harmonic control (Class EF(Class EF22) and third) and third--harmonic control (Class harmonic control (Class E/FE/F33))
D = 0.35
Z. Kaczmarczyk, “High-Efficiency Class E, EF2 and E/F3 Inverters,” IEEE Trans. Industrial Electronics, vol. IE-53, pp. 1584-1593, Oct. 2006
46
Class E/F3 power amplifier
3. Design approximations with second3. Design approximations with second--harmonic control harmonic control (Class EF(Class EF22) and third) and third--harmonic control (Class harmonic control (Class E/FE/F33))
( ) 0 2 =
= πωω
ttv
( ) 0 2
== πωω
ω
ttdtdv
Idealized optimum conditions
transistor has zero saturation voltage, zero on-resistance, infinite
off-resistance and its switching action is instantaneous and lossless
ideal Class E load network with shunt capacitance
series resonant L3C3 circuit tuned to third harmonic
Vdd
Z. Kaczmarczyk, “High-Efficiency Class E, EF2 and E/F3 Inverters,” IEEE Trans. Industrial Electronics, vol. IE-53, pp. 1584-1593, Oct. 2006
C
C0
R
I0
L
L3
C3
v
i
0 ωt
π 0 ωt
v/Vdd
1.0
2.0
π 2π
2π
3.0
1.0
i/I0
D = 0.55
47
ReferencesReferences
Andrei Grebennikov and Nathan O. Andrei Grebennikov and Nathan O. SokalSokalSwitchmode RF Power AmplifiersSwitchmode RF Power Amplifiers
NewnesNewnes 20072007
Andrei GrebennikovAndrei GrebennikovRF and Microwave Power Amplifier DesignRF and Microwave Power Amplifier Design
McGrawMcGraw--Hill 2004Hill 2004