Date post: | 24-Jun-2015 |
Category: |
Technology |
Upload: | piero-belforte |
View: | 126 times |
Download: | 0 times |
Piero Belforte April 18th 2012
Copyright Piero Belforte 2012
1
Trasmission Line approximation using LC cells
This Application Note analyzes the effect of approximating with lumped LC
cells an ideal TL (Z0=50 ohm, TD=1ns) terminated at the ends to 50 ohm and
connected to a pulse generator of amplitude 2Volts and rise time 200ps
(linear rise). This kind of approximation is often used by traditional (Spice
)simulators to model an ideal TL. DWS doesn't need this approximation
because TLs are the most efficient circuit element of DWS set. In this AN
DWS has been also utilized to model the fully LC lumped circuits used in
Spice models.
Three different situations are analyzed using DWS:
1) Transmission Line modeled as a cascade of 10 equal LC cells :
The following is the DWS netlist of case 1. The circuit is described using the
.CELL and the .CHAIN statements of DWS for automatic generation of the
cascade of 10 cells.
Piero Belforte April 18th 2012
Copyright Piero Belforte 2012
2
2) Transmission Line modeled as a cascade of 100 equal LC cells
The following is the DWS netlist of case 2. The circuit is described using the
.CELL and the .CHAIN statements of DWS for automatic generation of the
cascade of 100 cells.
The values of parameters L and C of each cell are set 1/10 of the previous
case because the number of cells is higher of a factor of 10.
Piero Belforte April 18th 2012
Copyright Piero Belforte 2012
3
3) Transmission Line modeled as an ideal TL
The following is the DWS netlist of case 3. The circuit is described directly
using element T of DWS related to an ideal TL.
Piero Belforte April 18th 2012
Copyright Piero Belforte 2012
4
This can be also the reference case because TLs are modeled in DWS
without approximations (except delay quantization depending on the choice of
simulation TSTEP ). In all previous cases TSTEP is 1PS allowing an exact
modeling of the TL delay of 1ns. In all netlists a maximum number of points
(LIMPTS) is set to 10,000.
All sims run in few microseconds on a Pavilion PC with I7 quad core CPU
utilized at 12.5% of full load. Setting up a lower TSTEP (in the femtosecond
region, an inversely proportional increase of sim times is obtained,but there is
no significant variations of the result).
Piero Belforte April 18th 2012
Copyright Piero Belforte 2012
5
Results
In the following the simulation output plots are shown:
Case 1
Case 2
Case 3 (reference)
Piero Belforte April 18th 2012
Copyright Piero Belforte 2012
6
Comparative plots (1,2 and 3):
Detailed plots:
Piero Belforte April 18th 2012
Copyright Piero Belforte 2012
7
Worst Case Eye diagrams at 1Gbps
Piero Belforte April 18th 2012
Copyright Piero Belforte 2012
8
The followings are Worst Case Eye Diagram (WCED) contours derived from
the previous simulations , showing the distortion effects due to the
approximation of lumped LC model of TL. The exact model of TL (DWS)
generates the best contour without no distortion. These WCEDs are created
using the companion viewer of DWS (DWV) used to display the waveforms of
this AN.
1Gbps WCEDs
4 Gbps WCEDs
From the previous WCED plots it is evident that the 10-cell model has serious
distortion problems at 1Gbps and at 4Gbps the eye is practically closed.
Piero Belforte April 18th 2012
Copyright Piero Belforte 2012
9
The 100-cell model is good up to 4Gbps if the generator rise time is in the
order of hundred of picoseconds as in this case. The problem arise from the
complexity because 200 circuital elements are required to model a single TL.
To investigate the distortion due to 100-cell approximation, the following
situation has been simulated:
Here the pulse generator has a rise time of 10ps and the simulation time step
is set to 10femtoseconds on a window of 10ns (1 Million calculated points ).
In the following the results compared to the ideal case. With respect the
previous simulations, the ringing due to lumped circuit approximation is more
evident at both ends, as espected.
Piero Belforte April 18th 2012
Copyright Piero Belforte 2012
10
Generator rise time:10ps , ideal TL vs 100 LC cells
Comparison to Circuit Lab results
Piero Belforte April 18th 2012
Copyright Piero Belforte 2012
11
The following is a comparison of the plots from Circuit Lab and DWS with
similar settings of the input generator and for the 10 LC cells situation.
The comparison has to be made between the falling edge of CL and the rise
edge of DWS to get the same ISI (Inter Symbol Interference) amount due to
previous transitions.
In this case the simulation time of CL was about 2 minutes compared to 30
milliseconds of DWS.
Obviously DWS is far more efficient when dealing with ideal TL.