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MC9211 –

Computer OrganisationUnit 2: Combinational and Sequential

Circuits

Lesson 3 of 3 : Register and Counters

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Registers A register is a group of binary cells suitable for 

holding binary information

 A group of flip-flops constitutes a register 

 An n-bit register has a group of n flip-flops and

is capable of storing n bits

In addition to flip-flops, a register may have

combinational gates that perform certain data

processing tasks

Definition: A register consists of a group of flip-flops and gates that affect their transition

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4 bit Register is the simplest possible

register consisting of only D Flip-Flops

Information present at a data input D istransferred to the Q output when the

clock pulse CP is 1 and when

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4-bit Register 

4 bit Register is the simplest possible

register consisting of only D Flip-Flops

Information present at a data input D is

transferred to the Q output when the

control pulse CP is 1, when CP is 0 the

information remains as it is

CP

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4-bit Register with parallel load

Transferring new informationin to the register is called

loading of the register 

If all the bits of the register 

are loaded simultaneously

with a single clock pulse,we say that loading is done

in parallel 

Note that clear signal is not

Shown in the circuit

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Shift Registers A register capable of shifting its binary

information either to the right or to the leftis called a sh i f t regis ter 

 A shift register consists of a chain of flip-

flops connected in cascade with theoutput of one flip-flop connected to the

input of the next flip-flop

 All flip-flops receive a common clock pulse

that causes the shift from one stage to

the next

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Simplest shift register using only flip-flops is shown above

Each clock pulse shifts the contents of the register one bit

position to the right

The serial input  determines what goes in to the left most

flip-flop during the shift

Serial output is taken from the output of the right most

flip-flop prior to the application of the pulse

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Serial and Parallel Transfer 

Serial transfer vs. Parallel transfer 

Serial transfer:

Information is transferred one bit at a time,

shifts the bits out of the source register into the destinationregister 

Parallel transfer:

 All the bits of the register are transferred at the same time

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Example: Serial transfer from reg A to reg B

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Serial addition using D flip-flops

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Serial adder using JK flip-flops

J Q =  x y  

K Q = x  y  = ( x + y ) 

S = x  y  Q 

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Circuit diagram

J Q =  x y  

K Q = x  y  = ( x + y ) 

S = x  y  Q 

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Universal Shift Register Unidirectional shift register: is a register that can

shift in only one direction

Bidirectional shift register: is a register capable of shifting both right and left

Universal shift register: has both direction shifts &

parallel load/out capabilities

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Universal Shift Register

Parallel-in Parallel-out

Serial-in Serial-out

Serial-in Parallel-out

Parallel-in Serial-out

D Q D Q D Q D Q 

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Capability of a universal shift register 1. A clear control to clear the register to 0

2. A c lock input to synchronize the operations3. A shi f t - r ight control to enable the shift right operation

and the serial  inpu t and outpu t lines associated w/ theshift right

4. A shift- left control to enable the shift left operation andthe serial  inpu t and outpu t lines associated w/ the shiftleft

5. A parallel- load control to enable a parallel transfer andthe n parallel  inpu t lines associated w/ the parallel

transfer 6. n parallel  output lines

7. A control state that leaves the information in the register unchanged in the presence of the clock

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Universal Shift Register

D 

Q 

D 

Q 

D 

Q 

D 

Q 

MUX

I 3  I 2  I 1  I 0

Y  S 

1  

S 0 

Q 3

Q 2

Q 1

Q 0

D 1

S 1  

S 0 

CLK  

CLR  

D 0

D 2

D 3

SI 

for 

SR 

SI 

for 

SL

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Example: 4-bit universal shift register 

Parallel outputs

 A3 A2 A1 A0

I3 I2 I1 I0 Parallel inputs

4-bit universal

shift register 

Clear 

s1

s2

Serial

input for 

shift-right

Serial

input for shift-left

CLK

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Function table

Clear s1 s0 A3+ A2

+  A1+ A0

+  (Operation)

0 ×  × 0 0 0 0 Clear 

1 0 0 A3 A2 A1 A0  No change

1 0 1 0 A3 A2 A1 Shift right

1 1 0 A2 A1 A0  0  Shift left

1 1 1 I3 I2 I1 I0  Parallel load

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