2014 CIGRE Paris

Iñigo Ferrero1

Process Bus Implementation on Process Bus Implementation on IEDs: Development ConsiderationsIEDs: Development Considerations

2014 CIGRE Paris

Iñigo Ferrero2

OverviewOverview

•Conventional / Process Bus Substations

•Topology example

•Development of the IED

•SV time alignment

•Sampling frequency change

•Frequency tracking

•Estimation of lost SV

2014 CIGRE Paris

Iñigo Ferrero3

Conventional SubstationConventional Substation

2014 CIGRE Paris

Iñigo Ferrero4

Process Bus SubstationProcess Bus Substation

2014 CIGRE Paris

Iñigo Ferrero5

Process Bus SubstationProcess Bus Substation

2014 CIGRE Paris

Iñigo Ferrero

Network Topology ExampleNetwork Topology Example

Merging Unit

IEC 61850-8-1

IEC 61850-9-2LE / IEC61869-9

Merging Unit

Merging Unit

Telecontrol.

WAN

Maintenance Management

Protection Management

Subestation Bus

Process Bus

IEC 61850-8-1

LEVEL 1(Bay Position)

LEVEL 2(Substation)

LEVEL 0 (Switchgear)

2014 CIGRE Paris

Iñigo Ferrero7

•Currents and Voltages can be measured by several MU

•Each SV has a Sample Counter (smpCnt) used by the IED that receives the frames to make the alignment:

•50 Hz: 0 – 3999

•60 Hz: 0 - 4799

•MU are synchronized (IRIG-B, PPS, IEEE1588). Reception on PPS signal forces the sample number 0, the rest are based on the internal MU clock

•SV from different MU can arrive at different times. Delays due to:

•MU processing time

•Communication network

SV AlignmentSV Alignment

MU works with 80samples/cycle

delay must be considered

2014 CIGRE Paris

Iñigo Ferrero8

SV AlignmentSV Alignment

2014 CIGRE Paris

Iñigo Ferrero

Sampling Frequency ChangeSampling Frequency Change

•Two options to convert a conventional IED into process bus:

•Adapt the filters to work with the new sampling frequency

•Change the sample frequency and use the same filters

Frequency trackingProtection algorithms

MU: 80 s/c

IED: 32 s/c

2014 CIGRE Paris

Iñigo Ferrero10

Frequency Tracking Frequency Tracking

•Sampling frequency of the MU is fixed (80 samples per 50 / 60 Hz cycle) without changing with the frequency

•Frequency tracking: if SV are directly used, errors during off-nominal frequencies will appear.

•The samples must span exactly one cycle.

•Harmonic influence must be also taken into account

Frequency tracking: algorithm that modifies the time between samples based on the frequency measurement to make the DFT window expand exactly one cycle

2014 CIGRE Paris

Iñigo Ferrero11

Estimation of Lost SV Estimation of Lost SV

•SV can be lost

•Lost SV can generate phasor errors during one cycle

•Blocking will delay the operation for too long

Estimation on SV

2014 CIGRE Paris

Iñigo Ferrero12

Estimation of Lost SV Estimation of Lost SV

•SV is consider as lost:

•Delay time

•Quality invalid

•Synchronized flag FALSE

•Estimation. Replaced by:

•Zeros

•Value of last SV

•New SV after lost SV

•Interpolation

2014 CIGRE Paris

Iñigo Ferrero13

•A time delay must be considered when time alignment is performed

•Decision between

•Changing from the MU sampling rate to the conventional relay sampling (allows maintaining the digital filters and protection algorithms)

•Work with the MU sampling rate

•Frequency tracking is needed because of the fixed sampling rate of the MU. Harmonics influence must be taken into account.

•Estimation of lost SV is a must. It should be developed to support SV lost also under harmonics presence.

Conclusions Conclusions

2014 CIGRE Paris

Iñigo Ferrero14

Thank you

Iñigo Ferreroinigo.ferrero@cggloblal.com