21.10.02 ES Seminar 1

Communicating Transaction Processes

P.S. Thiagarajan

National University of Singapore

Joint Work with:

Abhik Roychoudhury; ……

21.10.02 ES Seminar 2

The Main Features

• To support System Level Design– One Level of Abstraction higher than C, C++,

VHDL ..

• UML-compatible– MSCS + Asynchronous control flow– Based on MSCs (Message Sequence Charts)– Sequence Diagrams

21.10.02 ES Seminar 3

Why System Level Design?

• Closer to end-use(r) .• Less detailed and more architecture-neutral.• Easier reuse/adaptaton.• Easier to verify.

– Safety-critical applications need to be correct.– Catch design errors early.– Coupling with a correct-by-construction

synthesis method is an attractive option.

21.10.02 ES Seminar 4

What is Available?

• Data flow graphs.

• Automata of various kinds.

• Petri nets.

• State charts.

• Esterel, Lustre.

• SDL, UML.

21.10.02 ES Seminar 5

Why UML-compatible?

• UML is getting rapidly established as a standard.– Mainly in software engineering projects

– Increasingly so in embedded systems domain.

• Offers a suite of graphical notations:– Multiple views

– Behavioral and structural diagrams.

– Object orientation. Reuse, adaptation

21.10.02 ES Seminar 6

An Idealized Design FlowRequirements

Exec. Specifications.

Intermediate representation

SW/HW Implementation.

High Level Description

21.10.02 ES Seminar 7

Requirements and Exec. Specifications

• Requirements : Message Sequence Charts (MSCs)

• Exec. Specifications :– State charts.

• UML supports both but no clear distinction made.• Other Exec. Spec. :

– Petri nets,

– MPAs (Message Passing Automata), ….

21.10.02 ES Seminar 8

MSCs

• Message Sequence Charts:– Describe scenarios.– A finite pattern of interaction between agents

(object instances,..).– A story

21.10.02 ES Seminar 9

Message Sequence Charts

rq

U1 R

rq

yn

U2

21.10.02 ES Seminar 10

Message Sequence Charts

rq

U1 R

rq

yn

U2

21.10.02 ES Seminar 11

Message Sequence Charts

rq

U1 R

rq

yn

U2

internal action

21.10.02 ES Seminar 12

Message Sequence Charts

rq

U1 R

rq

yn

U2

internal actions

21.10.02 ES Seminar 13

Message Sequence Charts

rq

U1 R

rq

yn

U2

21.10.02 ES Seminar 14

Message Sequence Charts

rq

U1 R

rq

yn

U2

21.10.02 ES Seminar 15

Message Sequence Charts

rq

U1 R

rq

yn

U2

21.10.02 ES Seminar 16

Message Sequence Charts

rq

U1 R

rq

yn

U2

21.10.02 ES Seminar 17

Message Sequence Charts

rq

U1 R

rq

yn

U2

21.10.02 ES Seminar 18

Message Sequence Charts

rq

U1 R

rq

yn

U2

21.10.02 ES Seminar 19

Message Sequence Charts

rq

U1 R

rq

yn

U2

21.10.02 ES Seminar 20

Message Sequence Charts

rq

U1 R

rq

yn

U2

21.10.02 ES Seminar 21

Message Sequence Charts

rq

U1 R

rq

yn

U2

21.10.02 ES Seminar 22

CTPs

• Communicating Transaction Processes.• An executable spec. mechanism.

– Based on MSCs.

• A network of interacting agents.– Agent’s interaction pattern behavior:

Standard distributed system model

– Interaction: Guarded choice of MSCs. Transaction schemes.

21.10.02 ES Seminar 23

Distributed System Models

• Petri nets

• Data flow graphs

• Statecharts

• Distributed transition systems (many kinds!)

• Process algebras (CCS, CSP, …)

21.10.02 ES Seminar 24

PI1 IB1 IB2 PI2

I1

B

I2

P2

21.10.02 ES Seminar 25

PI1 IB1 IB2 PI2

I1

B

I2

P2

21.10.02 ES Seminar 26

PI1 IB1 IB2 PI2

I1

B

I2

P2

21.10.02 ES Seminar 27

PI1 IB1 IB2 PI2

I1

B

I2

P2

21.10.02 ES Seminar 28

PI1 IB1 IB2 PI2

I1

B

I2

P2

21.10.02 ES Seminar 29

PI1 IB1 IB2 PI2

I1

B

I2

P2

But the boxes will have internal structure.

A complex Transaction Scheme.

21.10.02 ES Seminar 30

Transaction Scheme

waitcount2:= waitcount2 + 1

2data.present & B.free 2data.present &

B.free

I2 B

reqy

add

data

I2 B

reqn

I2 B

2data.present

21.10.02 ES Seminar 31

PI1 IB1 IB2 PI2

I1

B

I2

reqy

add

data

2data.present & B.free

21.10.02 ES Seminar 32

PI1 IB1 IB2 PI2

I1

B

I2

reqy

add

data

2data.present & B.free

21.10.02 ES Seminar 33

PI1 IB1 IB2 PI2

I1

B

I2

reqy

add

data

2data.present & B.free

21.10.02 ES Seminar 34

PI1 IB1 IB2 PI2

I1

B

I2

reqy

add

data

2data.present & B.free

21.10.02 ES Seminar 35

PI1 IB1 IB2 PI2

I1

B

I2

reqy

add

data

2data.present & B.free

21.10.02 ES Seminar 36

PI1 IB1 IB2 PI2

I1

B

I2

reqy

add

data

2data.present & B.free

21.10.02 ES Seminar 37

PI1 IB1 IB2 PI2

I1

B

I2

reqy

add

data

2data.present & B.free

21.10.02 ES Seminar 38

P11

I1

1data.present

no-op

1data.present

1data.present

no-data

1data.present

1data.present

data

1data.present

P11 Transaction Scheme

I1

21.10.02 ES Seminar 39

Analysis Issues

• Determine whether a CTP is bounded.

• Determine if a CTP can deadlock.

• Determine if a CTP is well-formed.

Current Status

The CTP Model

SMV ES Representation

Verilog

AnalysisVerification

Simulation;

Synthesis

Case Studies

Modeling

Current Status

The CTP Model

SMV ES Representation

Verilog

AnalysisVerification

Simulation;

Synthesis

Case Studies

Modeling

Pankaj Jain

Nikhil Jain

Kamrul Hasan Talukdar

Tran Tuan Anh

Ge Zhiguo

21.10.02 ES Seminar 42

Future Work

• Add multiple instances of a process.– Object features

• Add timing constraints.• Develop the computational model.

– Interactions with environment (sense, actuate)– Computational steps (control law)– Schedulability is a key issue.

• HW/SW Partitioning; Architectural mapping; Synthesis?