218 IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING … · 2010. 1. 20. · COLGAN et al.: PRACTICAL...

218 IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES, VOL. 30, NO. 2, JUNE 2007

A Practical Implementation of Silicon MicrochannelCoolers for High Power Chips

Evan G. Colgan, Senior Member, IEEE, Bruce Furman, Michael Gaynes, Willian S. Graham, Nancy C. LaBianca,John H. Magerlein, Senior Member, IEEE, Robert J. Polastre, Mary Beth Rothwell, R. J. Bezama, Member, IEEE,

Rehan Choudhary, Kenneth C. Marston, Hilton Toy, Jamil Wakil, Jeffrey A. Zitz, and Roger R. Schmidt

Abstract—This paper describes a practical implementation ofa single-phase Si microchannel cooler designed for cooling veryhigh power chips such as microprocessors. Through the use ofmultiple heat exchanger zones and optimized cooler fin designs, aunit thermal resistance 10.5 C-mm2 W from the cooler surfaceto the inlet water was demonstrated with a fluid pressure drop of

35 kPa. Further, cooling of a thermal test chip with a micro-channel cooler bonded to it packaged in a single chip modulewas also demonstrated for a chip power density greater than300 W/cm2. Coolers of this design should be able to cool chipswith average power densities of 400 W/cm2 or more.

Index Terms—High power density, liquid cooling, microchannelcooling.

I. INTRODUCTION

MORE than 20 years ago, Tuckerman and Pease first de-scribed the use of microchannel cooling for very high

power densities [1]. They demonstrated cooling of 790 W/cmwith a temperature increase of 71 C for a flow rate of 0.52 lpmwith a pressure drop of 214 kPa where the 0.3-mm deep chan-nels were fabricated on the opposite side of an 0.4-mm thickwafer from a 1 cm 1 cm thin film resistor. However, thecoolers could not be fabricated easily and pressure drops werevery high. As chip power densities are now increasing beyondair cooling limits, it is necessary to address a number of practicalissues for implementing microchannel cooling. Recent progressin high-rate reactive ion etching (DRIE) of Si [2] has greatlysimplified the fabrication of microchannel coolers from silicon.Also a number of methods of reducing the pressure drop havebeen reported including subdividing the flow into multiple heatexchanger zones with shorter channel lengths [3] and mani-fold designs with large cross-sectional area (i.e., equal, or largerthan, the channel cross-sectional area) [4]. In addition, staggeredfins in microchannel coolers have been found to increase theheat transfer coefficient compared to continuous fins [5]. This

Manuscript received July 18, 2005; revised November 22, 2005. This workwas recommended for publication by Associate Editor J. Parry upon evaluationof the reviewers comments.

E. G. Colgan, B. Furman, M. Gaynes, W. S. Graham, N. C. LaBianca,J. H. Magerlein, R. J. Polastre, and M. B. Rothwell are with the IBMT. J. Watson Research Center, Yorktown Heights, NY 10598 USA (e-mail:[email protected]).

R. J. Bezama, K. C. Marston, H. Toy, J. Wakil, and J. A. Zitz are with IBMEast Fishkill, Hopewell Junction, NY 12533 USA.

R. Choudhary is with the Business Performance Services Team, IBM Corpo-rate Headquarters, Somers, NY 10589 USA.

R. R. Schmidt is with IBM, Poughkeepsie, NY 12601 USA.Digital Object Identifier 10.1109/TCAPT.2007.897977

is one of a number of thermal enhancement techniques whichhave been proposed for microchannel coolers [6].

To use microchannel coolers in an application such as a serverrack, it is desirable to have the pressure drop in the microchan-nels be 35 kPa ( 5 psi). This number is based on the pressureavailable from compact and reliable pumps reduced by the pres-sure drops in other system components such as heat exchangers,connectors, filters, and distribution piping. It is also necessary tominimize the flow through the microchannel cooler. If water isused as the coolant, corrosion inhibiters, biocide/algaecide etc,are required in addition to appropriate filtration.

For a practical implementation of microchannel cooling, it iscritical that the cooler be easy to integrate with the chip pack-aging. High performance chips are typically mounted active sidedown on a first-level package substrate using an area array ofsolder balls. The assembly is subsequently attached to a printedcircuit board or second level package by a solder ball grid array(BGA). With chips mounted active side down, the back sides ofthe chips are available for the cooling solution. Given the costof high-performance processor chips, it is not practical to formthe microchannels directly on the back surface of the chip. In-stead, a separate microchannel cooler is bonded to the back ofthe chip with materials having as low a thermal resistance aspossible. If the microchannel cooler is fabricated from silicon, arigid bonding means such as silver-filled epoxy or solder can beused. If a copper microchannel cooler were used [7], accommo-dating the different thermal expansion coefficients of Si and Cuwould require a compliant thermal interface material, possiblylimiting the thermal performance.

This paper first describes the design, fabrication, and testingof individual Si microchannel coolers and presents measure-ment results for coolers with both staggered and continuousfins. A practical integration method for packaging microchannelcoolers into single chip modules (SCMs) is then described alongwith measurement results for these packaged coolers.

II. MICROCHANNEL DESIGN, FABRICATION, AND TESTING

The design and assembly of the silicon microchannel coolerscan be understood with reference to Figs. 1–3. The cooler con-sists of a manifold chip shown in Fig. 1(a) and a channel chipshown in Fig. 1(b) bonded together. Each chip is 20 20 mm insize and there is a 0.7-mm wide seal region around the perimeterwith no microchannels. Magnified images of the two chips areshown in Fig. 2. Fig. 2(a) shows the side of the manifold chipwhich faces the channel chip, while Fig. 1(a) shows the otherside. The view in Fig. 2(a) shows distribution channels whichare etched 0.25 mm deep into the Si to help redistribute the

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COLGAN et al.: PRACTICAL IMPLEMENTATION OF SILICON MICROCHANNEL COOLERS 219

Fig. 1. Image of manifold chip from (a) gasket side and (b) channel chip.Each is 20 mm � 20 mm in size. The etched microchannels in (b), which arenot visible in the photograph, run vertically.

Fig. 2. Magnified images of manifold chip from (a) side facing the channelsand (b) channel chip.

Fig. 3. 3-D rendering of assembled microchannel cooler.

flow from or to the fluid vias. As shown in Fig. 2(b), the mi-crochannel fin segments are removed from the regions under thefluid vias and the manifold redistribution channels to aid furtherin the redistribution of the flow at the fluid vias.

A 3-D rendering of the assembled microchannel cooler isshown in Fig. 3, where the manifold chip is on top and shownsemi-transparent. In operation, alternate lines of fluid vias areused as inlets and outlets (see Fig. 1), so the microchannel cooleris divided into six parallel-fed heat exchanger zones and the flowlength between the inlets and outlets is 3 mm. The fluid vias inthe manifold chip were formed as zigzagged arrays of circularopenings instead of elongated slots to reduce the likelihood ofthe manifold chips breaking during fabrication and assembly.

The microchannel coolers described in Section III were fab-ricated on 200-mm wafers 0.725-mm thick using photolithog-raphy and deep Si reactive ion etching. For the channel chips,

Fig. 4. Heater and sensor resistor pattern for (a) thermal testing and (b) mi-crochannel thermal test station.

the channels were about 180 m deep and the regions whichaligned to the fluid vias were about 230 m deep. Several dif-ferent staggered fin configurations were fabricated. The pitchwas kept constant at 100 m, but the channel width was ei-ther 65 or 75 m, referred to as “narrow” or “wide.” Thefin length was either 210 or 250 m where there was a 40 mgap between rows of fins when the length was 210 m. Thesharpness of the ends of the fins was also varied. The image inFig. 2(b) is from a sample with a 65 m channel, no gap betweenthe rows of fins, and a blunt end. For the manifold chips, thefluid vias were formed first and etched to a depth of 0.5 mm;the manifold channels were than etched on the opposite side ofthe wafer to a depth of 0.25 mm. The manifold and channelchips were joined together using a very thin (5–15 m) adhesivelayer applied to the manifold chip.

For thermal testing of these microchannel coolers, a heaterand a temperature sensor resistor shown in Fig. 4(a) wereformed by etching a 0.5–1.5 m thick copper film on a thininsulator layer on the back surface of the channel chip. Thetwo large pads in the upper corners were used for poweringthe heater resistor and the two small pads in the lower cornerswere used for connecting to the sensor resistor. The heaterresistor was designed to cover as much of the 20 20 mmchannel chip area as possible. The sensor resistor was locatedwithin the 0.2-mm wide gaps between the serpentines of theheater resistor, which were open towards the bottom edge ofthe chip. The sensor resistor was 22-mm long and 15 mwide. The samples were measured using the test station shownin Fig. 4(b), where the water flow could be varied while mea-suring the differential pressure across the microchannel cooler,the inlet and outlet water temperatures, the sensor resistorvalue, and the power applied to the heater resistor. The sensorresistor was calibrated by varying the water temperature whilemeasuring the sensor resistor value.

III. MICROCHANNEL COOLER RESULTS AND DISCUSSION

Fig. 5 shows test results for a microchannel cooler with 25025 m staggered blunt fins and 75 m wide 195 m deep

channels for various flow conditions with more than 1.1 kWapplied to the heater resistor (275 W/cm ). The power (linewithout symbols and right axis) was turned off while stabilizingdifferent flow conditions. The temperature difference betweenthe average chip temperature measured by the sensor resistorand the inlet water is plotted with square symbols and the watertemperature rise between outlet and inlet is plotted with cir-cular symbols and indicated on the left axis. Note that there will



Fig. 5. Microchannel cooler with staggered 250� 25�m fins and 75-�m wide,195-�m deep channels for various flows and >1.1-kW power.

Fig. 6. Friction coefficient for microchannels with different fin geometry.

be a systematic variation in the chip temperature between theinlet and outlet regions, so the maximum chip temperature willbe approximately equal to the average chip temperature plushalf of the total increase in the fluid temperature, or

2. In an actual application, it is desirableto align the microchannel inlet regions with the highest powerdensity regions on the chip to minimize the maximum junctiontemperature. The differential pressure, flow, and unit thermal re-sistance values are indicated on Fig. 5. As expected, the tem-perature differences, and unit thermal resistances, decreased asthe flow rate was increased. Note that the flow rate was not in-creased, or decreased, monotonically. The unit thermal resis-tance values (C-mm W) were calculated as

(1)

where the chip area was the full area of the 20 20 mmchip, not just the active area of the microchannels. Note thatthis is an average value and the 0.5-mm thick silicon sub-strate of the channel chip contributes 4 C-mm /W to themeasured unit thermal resistance. This compares favorable tothe 9.0 C-mm W thermal resistance reported in the work of

Fig. 7. Nusselt number for microchannels with different fin geometry.

Tuckerman and Pease [1] where the silicon substrate belowthe channels was only 0.1-mm thick and the pressure drop wasmuch higher. Thermal conduction of the complete structurewas simulated numerically using a commercially availableCFD code and found that a unit resistance of 10.5 C-mm Wcorresponds to an average heat transfer coefficient for themicrochannels of 130 000 W/m -C and 12.0 C-mm W corre-sponds to 105 000 W/m -C.

Figs. 6 and 7 show flow and thermal performance for a va-riety of microchannel configurations as indicated by the symboltype. Blunt and sharp ended fin results were similar and are notdistinguished. The number of samples of each type is also indi-cated. The channel chips were all from three wafers with similaretch depths in the regions which aligned to the fluid vias.

To display all the flow results on the single graph shown inFig. 6, the differential pressure was converted into an apparentfriction factor, -app, using an effective wetted fin length ,fluid density , channel average fluid velocity , and channelhydraulic diameter using the expression

(2)

where the effective fin length of a continuous channel was setequal to the 3000- m nominal channel length, . Since the av-erage hydraulic diameter for the channels is about 100 m andthe Reynolds number ranges between 26 and 282, the flow ina continuous channel is expected to become fully developedafter Re/20 diameters [8], or within the first 1000 m along thechannel. However, the flow with the staggered fins cannot befully developed because of the significantly shorter length (210or 250 m). Therefore, the pressure drop data analysis is doneusing the channel dimensionless hydrodynamic entry-length

as a metric of the fluid flow characteristics for a givenchannel flow and geometry where is the nominal channellength. The value of (f-app ) for a fully developed flow in arectangular channel with aspect ratio (height/width) of 3 is ap-proximately 17, and increases to 24 for very large aspect ratios[8]. Fig. 6 shows the pressure data collected for both continuousand staggered fins, and the data analysis suggests an asymp-totic value for (f-app ) of 32. This somewhat higher than



expected value is probably due to the fact that the experimen-tally measured differential pressure values include contributionsfrom both the microchannels and the inlet and outlet manifolds.Thus the contribution of the microchannels alone cannot easilybe determined.

Since the thermal data was collected using water (Prandtlnumber, 7), we do not expect fully developed thermal pro-files in any of the samples since fully developed thermal profilesrequire approximately /20 diameters of channel length[8]. The calculated average convective heat transfer coefficient

(based on the effective fin length, ) was used to calcu-late an average Nusselt number using the channel hydraulic di-ameter . Similar to the pressure drop evaluation above, thethermal data analysis was done using a dimensionless thermalentry-length as a metric of a given experi-mental test condition. For a channel with aspect ratio of 3 andfully developed laminar flow, the Nusselt number is expected toasymptotically approach 4. The expected value is 9 for80.

The experimental thermal data in Fig. 7 shows a higheraverage Nusselt number than expected from laminar flowtheory [8]. This deviation is expected because the microchannelentrance hydrodynamics does not correspond directly to the as-sumptions used to develop the theoretical values. Furthermore,3-D computational fluid dynamics simulations of a typicalmicrochannel geometry assuming laminar flow conditionssupport a higher heat transfer coefficient than expected fromtheory. Since the theory for turbulent heat convection insidea tube and laminar heat convection over an external surfacesupports a direct relationship between the Stanton number

and the friction coefficient f-app, usually inthe form

(3)

a plot of versus f-app should result in a linear relationship.Fig. 8 shows that the data departs somewhat from the expectedlinear relationship. The model proportionality constant of0.08 is lower, as expected, than the value predicted from (3)for 7, mainly because the pressure data includes bothmicrochannel and flow manifolds effects as stated above. Thesystematic deviation from linearity at higher friction factorvalues can be attributed to the expected different dependencyof pressure drop and water velocity in these two flow zones,where a quadratic dependency is expected only in the inlet andoutlet manifolds while the channel section will show a variabledependency between linear and quadratic depending on thechannel Reynolds number and channel length.

The thermal data also shows that continuous and staggeredfins with different channel width and fin geometry will followthe given semi-empirical relationship with a deviation below7% (see Fig. 7). Within the range studied, the Nusselt numberfollows a square root dependency on the Reynolds number,hence providing higher heat transfer with increasing fluidvelocity or decreasing microchannel hydraulic diameter. Forsamples with equivalent geometries, the presence of the 40 mgap (i.e., shorter ) between rows of staggered fins was foundto reduce the thermal performance for both the narrow and widechannel cases. Note that in this section, there are no sampleswhich allow a direct comparison of continuous and staggered

Fig. 8. Stanton number and friction coefficient relationship for microchannelswith different fin geometries.

fin with the same channel geometry. The next section providessuch direct comparisons and staggered fins provide improvedperformance, mainly because the staggered fins effectivelyreduce the thermal diffusion distance between the wall and theflow centerline.

IV. SINGLE CHIP MODULE ASSEMBLY AND RESULTS

The microchannel coolers which were integrated into singlechip modules were very similar to those described above, butwere fabricated on 150-mm wafers 0.675-mm thick. Themanifold and channel chips were fusion bonded together ratherthan joined with adhesive. Four cooler designs similar to thosedescribed above were used. Both continuous and staggeredfins with a 75- m pitch and 45- m channel width as wellas a 100- m pitch and 60- m channel width were used. Thechannel depths were about 254 m and 262 m for the twopitches. For the staggered fins, there was no gap between rowsof fins.

A test station similar to that described above for individualmicrochannel coolers was used for testing the single chip mod-ules. The differential pressure measurements were not correctedfor the 4 kPa pressure drop measured in the test station whenthe SCM was replaced with a short hose segment. The thermaltest chip in the SCM was 18.5 18.6 mm in size and the pow-ered area was 3 cm . The uncertainty in the measured thermalperformance is 5%, due mainly to the uncertainty in the sensorcalibration and the small amount of heat which does not flowthrough the microchannel cooler.

When packaging a chip with a microchannel cooler in apractical module configuration, there are many constraintswhich must be considered. Since a first level package maycontain more than one chip and frequently contains passivecomponents such as capacitors around the chip, the externalfluid manifold for the microchannel cooler must not interferewith such passive components. The fluid connection shouldprovide mechanical decoupling between the cooler and thefluid inlet/outlet manifold to prevent excessive stress on thesolder balls which attach the chip to the package substrate. Fora normal BGA assembly processes, the microchannel coolerand associated manifold should be compatible with a eutectic( 225 C) or Pb-free ( 245–260 C) reflow and the total



Fig. 9. Schematic cross-section of microchannel cooler integrated in a singlechip module.

Fig. 10. Components for assembly of microchannel SCM.

weight low enough to enable self alignment during reflow. Wehave designed a microchannel cooled SCM assembly shown inFig. 9 to meet these requirements.

The components used in a microchannel cooled SCM areshown in Fig. 10. A two piece manifold block, Fig. 10(a)–(c),which was molded from a high-temperature plastic, transformeda single inlet and outlet into alternating inlet and outlet zones.A 18.5 18.6 mm thermal test chip was mounted with solderballs onto a ceramic module and underfilled, Fig. 10(d). The mi-crochannel cooler, Fig. 10(e), was bonded to the thermal chipusing a Ag epoxy or In solder. A flexible gasket, Fig. 10(e), wasplaced between the microchannel cooler and the manifold block.The bottom perimeter of the manifold block was bonded to theceramic package. A completed microchannel SCM is shown inFig. 10(f).

Fig. 11 shows results for a microchannel SCM with 30 mfins and 45 m channels for various flow conditions when morethan 900 W was applied to the heater resistors. The poweredarea was 3 cm , so the power density was 300 W/cm . Thepower (line without symbols and right hand axis) was turnedoff while stabilizing different flow conditions. The temperaturedifference between the chip (determined from the average ofthe two chip center sensors) and the inlet water is plotted withsquare symbols and between the outlet and inlet water is plottedwith circular symbols and indicated on the left axis. For the con-ditions used, the increase in the water temperature was around10 C, so there is no possibility of boiling, even at substantiallyhigher power levels. The thermal conduction in the test mod-ules was simulated numerically using a commercially availableCFD code to relate the measured thermal resistance ( C/W) tothe unit thermal resistance (C-mm W) indicated on Fig. 11.

Fig. 11. Microchannel SCM with 30-�m fins and 45-�m channels for variousflows and >0.9-kW power.

Fig. 12. Thermal resistance for a large group of SCM microchannel coolerswith four different microchannel designs at a water flow rate of 1.25 lpm.

Note that the unit thermal resistance values in Fig. 11 are largerthan those in Fig. 5 because the measurement includes a thermalchip (0.725-mm thick) and the Ag epoxy layer used to join themicrochannel cooler to the chip.

The results for a number of microchannel SCMs with the fourdifferent microchannel configurations are shown in Fig. 12. Thetotal unit thermal resistance includes the thermal chip, the Agepoxy, and the microchannel cooler. The unit thermal resistanceis indicated by the squares and the left axis and the differentialpressure by the circles and the right axis. These measurementswere made with four inlets and three outlets where the chipcenter sensors were closer to the fluid inlet than to the outlet.With a flow of 1.25 lpm, reversing the flow direction causesthe measured thermal resistance to increase by 3%. Therefore,the average thermal resistance, (i.e., midway between the inletand outlet) is about 1.5% larger than the values plotted. The mi-crochannel cooler was bonded to the back side of the thermalchip using an Ag epoxy. All the SCMs, except for three whichare indicated by “X” on the plots, used the same material. Use ofan alternate Ag epoxy reduced the total unit thermal resistanceby about 1.6 C-mm W. From the above measurements, it isnot possible to determine the contribution from the individualcomponents to the total unit thermal resistance.

The results of 3-D computational fluid dynamic simulationsfor the 100 m pitch staggered (a,b) and continuous (c,d) mi-crochannels with 60 m channels 260 m deep are shown in



Fig. 13. Calculated temperature and velocity for 100-�m pitch staggered andcontinuous fins with 1.0 lpm flow.

Fig. 13. The calculated temperature profiles Fig. 13(a), (c) andvelocity profiles, Fig. 13(b), (d) shown are for a plane midwaybetween the top and bottom of the channels. The lowest temper-ature is 22 C (black) and the maximum is 37 C (white), andthe maximum velocity is 1.7 m/s (white). Note that the contin-uous fin is hotter than the staggered fins at equivalent distancesalong the channel, indicating the improved heat transfer with thestaggered fins, Fig. 13(a), (c). The apparent heat transfer coef-ficient, , midway between the inlet and outlet, with a flowof 1.25 lpm, was calculated to be 150 000 W/m -K for 100- mpitch continuous fins and 190 000 W/m -K for 100- m pitchstaggered fins as described above. From these value and thethickness of the thermal chip (0.725 mm, 5.6 C-mm /W) andthe microchannel cooler base (0.425 mm, 3.3 C-mm /W), theunit thermal resistance of the Ag epoxy used can be estimatedas 7.5 C-mm W. The thermal resistance of the alternate Agepoxy is about 5.9 C-mm W.

For the 75- m pitch staggered fin results shown in Fig. 12,the average total unit resistance was 20.7 C-mm W. If weassume that the Ag epoxy unit thermal resistance is about7.5 C-mm W, and allowing for the thermal resistance ofthe chip and the microchannel cooler base, then the averageapparent heat transfer coefficient is about 210 000 W/m -K.

Fig. 14 shows graphically the approximate contributionsof the various components to the total unit thermal resis-tance which was measured for the 75 m pitch staggered fins(Fig. 12). The total thermal resistance can be further reducedto permit operation at higher power densities by using thealternate Ag epoxy (reduction of 1.6 C-mm /W), by thin-ning the chip from 725 m to 400 m and the base of themicrochannel cooler from 425 m to 250 m (additional re-duction of 3.8 C-mm /W), and by using a thin In solder bondinstead of Ag epoxy (additional reduction of 3.4 C-mm /W).We have found that such an In solder joint between two siliconchips has a unit resistance of about 2.5 C-mm W.

The maximum power density which can be cooled with thistechnology may be estimated from the values in Fig. 14 by as-suming a of 63 C, i.e., 22 C and 85 C,and increasing the values by 1.5% so they correspond to the unitthermal resistance from the inlet water to a point midway be-tween the inlet and outlet manifolds. A total unit resistance of21.0 C-mm W would correspond to 300 W/cm , as demon-strated in Fig. 11. For the thin Si case with the alternate Agepoxy, having a thermal resistance of 15.7 C-mm W, a powerdensity of 400 W/cm could be cooled midway between the inletand outlet. As an approximation, for a 2 2 cm chip with a flow

Fig. 14. Estimated thermal resistance with 75-�m pitch staggered fins and ex-tensions to higher powers.

of 1.25 lpm, would be about 19 C at 400 W/cm , soin the regions aligned to the inlet and outlet, power densities of

460 W/cm and 340 W/cm , respectively, could be cooledwhile maintaining 85 C. The temperature gradient be-tween the inlet and outlet can be reduced by increasing the flow,but if there is a chip hot spot which is smaller in one directionthan the channel length, the increased cooling capacity near theinlet can be taken advantage of by aligning the microchannelinlet regions to the chip hot spot. This approach might be ex-tended to even higher power densities by using a solder layer tojoin the microchannel cooler to the chip and by using finer pitchstaggered fins.

V. CONCLUSION

A practical implementation of a single-phase silicon mi-crochannel cooler bonded to a high power chip and extendableto power densities of 400 W/cm or more has been described,and cooling of 300 W/cm in an SCM demonstrated. A 22 cm microchannel cooler with a resistive heater on the back ofthe channel chip with six heat exchanger zones demonstrateda thermal resistance of 10.5 C-mm W with a reasonable flowrate and a pressure drop in the microchannel cooler of 35 kPa.The performance of 75- or 100- m pitch silicon microchannelcoolers with staggered fins was shown to be superior to con-tinuous fin designs with equivalent geometries. This work hasshown that a silicon microchannel cooler can be integrated witha single chip module in a simple and practical manner whileproviding excellent thermal performance at very high powerlevels.

ACKNOWLEDGMENT

The authors wish to thank: B. Kane, W. Lam, D. Lisounenko,K. McCollough, R. Meyer, J. Newbury, A. Niera, R. Nunes,R. Owen, D. Patsy, D. Posillico, C. Scerbo, M. Steen, C. Tsang,J. Vichiconti, and B. White, IBM Yorktown MicroelectronicsResearch Laboratory, for fabrication of the silicon wafers;S. Bradley and F. Pompeo, for chip joining; and B. Humphrey,RC Molding, and L. Mabbott, Micralyne, for technical supportin the fabrication of the plastic manifold blocks and the fusionbonded microchannel coolers.



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[3] G. M. Harpole and J. E. Eninger, “Micro-channel heat exchanger opti-mization,” in Proc. 7th IEEE Semi-Therm Symp., 1991, pp. 59–63.

[4] R. L. Webb, “Effect of manifold design on flow distribution in parallelmicro-channels,” presented at the International Electronic PackagingTechnology Conference (IPACK’03), 2003, unpublished.

[5] T. Kishimoto and S. Sasaki, “Cooling characteristics of dia-mond-shaped interrupted cooling fins for high power LSI devices,”Electron. Lett., vol. 23, no. 9, pp. 456–457, 1987.

[6] M. E. Steinke and S. G. Kandlikar, “Single-phase heat transfer en-hancement techniques in microchannel and minichannel flows,” inProc. 2nd Int. Conf. Microch. Minich., 2004, pp. 141–148.

[7] P. Prechtl and O. Kurtz, “Efficient liquid cooling technologies forcomputer systems,” in Proc. Adv. Technol. Workshop Thermal Manag.(IMAPS ATW) Conf., Palo Alto, CA, Oct. 25–27, 2004, [CD ROM].

[8] W. M. Kays, Convective Heat and Mass Transfer. New York: Mc-Graw-Hill, 1966, ch. 6, 8, and 9.

Evan G. Colgan (M’87–SM’06) received the B.S.degree in applied physics from the California Insti-tute of Technology (Caltech), Pasadena, in 1982 andthe Ph.D. degree in materials science from CornellUniversity, Ithaca, NY, in 1987.

He joined IBM, Hopewell Junction, NY, in 1987and worked on silicides, selective CVD-W, diffusionbarriers, and both Cu- and Al-based chip wiring.He transferred to IBM Research as a Research StaffMember in 1995 to manage the TFT ProcessingDepartment, and subsequently worked on a number

of display related projects. He joined the Packaging Area in 2001 to work onoptical packaging and is currently working on high performance liquid cooling.He has 100 technical publications and 65 issued U.S. patents.

Dr. Colgan and is a member of APS and MRS.

Bruce Furman received the Ph.D. degree in chem-istry from Cornell University, Ithaca, NY, in 1980.

He then joined Charles Evans and Associatesdoing materials characterization of semiconductors.In 1982, he joined IBM GTD (Technology Division),Poughkeepsie, NY. In 1985, he moved to the Re-search Division of IBM to work in thin film materialdevelopment for packaging applications. During his20 plus years at IBM, he has worked on numerouspackaging and silicon programs. Currently, he isworking in an Optoelectronic and MEMs Packaging

Group. Projects include bonding applications for silicon, optoelectronic, andMEMS fabrication and integration.

Michael Gaynes received the B.S. degree in chem-ical engineering from Brigham Young University,Provo, UT.

He joined IBM in 1979. He has held technicalleadership positions that cover a wide spectrumof electronic packaging in manufacturing anddevelopment. These include ceramic chip carriercircuitization, failure analysis, reliability test andmodel development, flip chip organic packagingdesign and process development, adhesive develop-ment, and adhesion science. From 1990 to 2003, he

directed materials and process development efforts for applications that requirethermally and electrically conductive adhesives, die attach adhesives, and flipchip underfills. Since 2003, he has been with IBM Research, Yorktown Heights,NY, where he is providing leadership in developing advanced adhesives andadhesion improvements that are needed for next generation flip chip structures.He is a Senior Engineer with 30 technical publications and 87 U.S. patentsissued.

William S. Graham is a Staff Engineer at theIBM Thomas J. Watson Research Center, YorktownHeights, NY. He joined IBM in 1982. Presently, he isworking on the development of FEOL RIE processesfor advanced CMOS technologies. Previously, hehad worked on thin-film transistor processing for flatpanel displays, mainframe packaging, contaminationcontrol, and superconductor technology.

Nancy C. LaBianca is an Advisory Engineer inthe Applied Polymer Technology Group, ThomasJ. Watson Research Center, Yorktown Heights,NY. She joined IBM in 1988, working to developgate metal processes for GaAs technology. Herprojects have included a broad range of lithographicand packaging activities, including high-resolutionphotosensitive polyimides for advanced multichipmodules, CGR negative resist, used in manufacturingIBM logic chips, and thermal cooling strategies andmaterials for advanced packaging. She is currently

involved in the application and development of wafer level underfill for flipchip processing.

John H. Magerlein (M’93–SM’06) received theB.A. degree in physics from Kalamazoo College,Kalamazoo, MI, and the M.S. and Ph.D. degreesin physics from the University of Michigan, AnnArbor, in 1973 and 1975, respectively.

He is a Research Staff Member and Managerof the Chip Cooling and RF Passives Department,IBM Thomas J. Watson Research Center, YorktownHeights, NY. He worked at Bell Laboratoriesprior to joining IBM in 1977. While there he hascarried out research on experimental Josephson

junction circuits, GaAs MESFET processing, and electromagnetic modelingof high-performance interconnects prior to assuming his current position in2001. His present research interests include liquid cooling of high power chips,RF MEMS devices, and electrical and optical packaging for high-performancecomputer systems.

Dr. Magerlein is a member of the American Physical Society.

Robert J Polastre received the Associates degreein electronic technology and the B.S. degree fromLaSalle University, Philadelphia, PA.

He is an Advisory Engineer working in the Systemon A Package Group, IBM, Yorktown Heights, NY.He joined the IBM Research Division in 1983. Heis the author or co-author of several papers on au-tomated and thermal testing and is a co-inventor ofpatents in these areas.

Mr. Polastre received Outstanding TechnicalAchievement Awards in 1990 and 1999 and an IBM

Corporate Award in 1993 for his work on array testing of thin film transistors.

Mary Beth Rothwell received the B.S. degree inchemistry from Pace University, Pleasantville, NY.

She joined the IBM Research Division, YorktownHeights, NY, in 1985. She first worked in an Electron-Beam Lithography Group and then in 1991, joinedthe TFT Processing Group. In 2001, she was an In-tegration Engineer for the offline packaging facility.She is currently an Advisory Integration Engineer forthe Microelectronics Research Laboratory (MRL) ofthe Research Division.



R. J. Bezama (M’01) received the B.S. degree inchemical engineering from the University of Chile,Santiago, in 1978 and the M.E. and Ph.D. degrees inchemical engineering from University of Utah, SaltLake City, in 1980 and 1983, respectively.

In 1983, he joined IBM, East Fishkill, NY, as aStaff Engineer to work on the development of glassceramic MLC products. At IBM, he specialized inprocess simulation and optimization of productiontools for different development and manufacturingsectors like ceramic processing, thin films pro-

cessing, C4 plating, and chip processing. He is currently a DistinguishedEngineer in the Package Development Group, Hopewell Junction, NY. Heholds 38 U.S. patents and has authored and co-authored 15 technical papers.His current activities include SCM and MCM microelectronic packagingresearch and development, research and development of high performancecooling devices, and providing CFD modeling support to both developmentand manufacturing engineering groups.

Dr. Bezama is a member of AIChE and Tau Beta Pi.

Rehan Choudhary received the B.S. degree inchemical engineering and the B.A. degree in eco-nomics from the University of Maryland at CollegePark and is currently pursuing the MBA from theState University of New York at New Paltz.

He has held positions as a Manufacturing Engineerand a Technology Development Engineer at IBMSystems and Technology Group, Hopewell Junction,NY. He is currently part of the Business Perfor-mance Services Team, IBM Corporate Headquarters,Somers, NY. His present Assignment is focused on

Identifying and developing initiatives aimed at Strengthening IBM’s revenuegrowth.

Kenneth C Marston received the B.E. degree inmechanical engineering from the State Universityof New York (SUNY), Stony Brook and the M.S.degree in mechanical engineering (with a focus onthermal sciences) from the University of Minnesota,Minneapolis, in 1991.

He is an Advisory Engineer with IBM Micro-electronics, East Fishkill, NY. He has been withIBM since 1991 and has 15 years of experiencein product development and advanced modulemanufacturing, including thermal/mechanical pack-

aging development for organic and ceramic packages; project managementfor several high-end products manufactured in the IBM Poughkeepsie BATline; development of temperature control systems in module test and burn inequipment; and manufacturing process responsibilities for temperature-relatedstress, solder reflow operations, and encapsulation.

Hilton Toy received the B.S. degree in mechanicalengineering from the Polytechnic Institute of NewYork, Brooklyn, NY.

He joined IBM in 1982 and is currently workingin Thermal and Mechanical Design Group, IBM,East Fishkill, NY. Since 1990, he has been workingin product development on module encapsulationand cooling solutions for electronic packaging. Hehas co-authored several technical papers and holds28 patents.

Jamil Wakil received the B.S. degree in mechanicalengineering from Texas A&M University, CollegeStation, the B.S. degree in electrical engineeringfrom the University of Texas at Dallas, and theM.S. degree in mechanical engineering from TheUniversity of Texas at Austin.

He is currently working on package thermal devel-opment for IBM microelectronics, focusing on firstlevel thermal enhancement for organic packages.He has been with IBM for six years and has severalpatents and publications.

Jeffrey A. Zitz received the B.S.M.E. and M.S.M.E.degrees from Rensselaer Polytechnic Institute, Troy,NY.

He is a Senior Packaging Engineer with IBM,East Fishkill, NY. During his 20 years with IBM, hehas applied his diverse engineering expertise in theareas of materials, mechanical, thermal, statisticalmodeling, reliability, and manufacturing to IBM’sceramic and organic chip carriers, and computersystems. He lead the development of both bare-dieflip-chip ceramic carriers and the direct lid attach

(DLA) package utilized by IBM and other flip-chip package manufacturers. Hisinnovations appear across IBM’s ASIC and PowerPC die product offerings, andhave been key drivers to higher package performance at lower cost. Recently,he lead the first-level packaging of IBM i/p series POWER4 and POWER5server generations, driving thermal, mechanical and cost performance to meetproduct and market requirements.

Mr. Zitz is a Registered Professional Engineer in the State of New York.

Roger R. Schmidt has over 25 years experiencein engineering and engineering management in thethermal design of IBM’s large scale computers. Hehas led development teams in cooling mainframes,client/servers, parallel processors and test equipmentutilizing such cooling mediums as air, water, andrefrigerants. He has published more than 75 technicalpapers and holds 51 patents in the area of electroniccooling. He is a member of ASME’s Heat TransferDivision and an active member of the K-16 Elec-tronic Cooling Committee. He has been an Associate

Editor of the Journal of Electronic Packaging and is now Associate Editor ofthe ASHRAE Research Journal and the ASME Journal of Heat Transfer. Hehas taught extensively over the past 20 years mechanical engineering coursesfor prospective professional engineers and has given seminars on electroniccooling at a number of universities.

Dr. Schmidt is a Fellow of the ASME and a member of the National Academyof Engineering and the IBM Academy of Technology. He is Vice Chair of theASHRAE TC9.9 Committee on Mission Critical Facilities, Technology Spaces,and Electronic Equipment.


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