Update: 19/02/2020 CTS, BSC, SRT, TSK Page 1/15 2182212 Fundamental of Circuits and Digital Electronics Laboratory Faculty of Engineering, Chulalongkorn University Flip Flop and Counter (FFC) Ekachai Leelarasmee, 19 February 2009 Instructor: Date: Name: 1) ID 2) ID 3) ID A. Objectives 1. To understand the basic of clocked flip flops and their operations. 2. To learn how to construct counters from flip flops. B. Introduction Ever seen a system in which all actions or results are synchronized by one control signal. ? Here are a few examples 1) In a school or university, all class activities are hourly synchronized. 2) In a marching band, the drum’s beat synchronizes the march. 3) In computers, mobile phones and many consumer electronic devices today, their internal processes need a clock signal to synchronize. Note that the clock plays no part in determining what activities or results are to be made.
Transcript
Update: 19/02/2020 CTS, BSC, SRT, TSK Page 1/15
2182212 Fundamental of Circuits and
Digital Electronics Laboratory
Faculty of Engineering, Chulalongkorn University
Flip Flop and Counter (FFC)
Ekachai Leelarasmee, 19 February 2009
Instructor: Date:
Name: 1) ID
2) ID
3) ID
A. Objectives
1. To understand the basic of clocked flip flops and their operations.
2. To learn how to construct counters from flip flops.
B. Introduction
Ever seen a system in which all actions or results are synchronized by one control
signal. ? Here are a few examples
1) In a school or university, all class activities are hourly synchronized.
2) In a marching band, the drum’s beat synchronizes the march.
3) In computers, mobile phones and many consumer electronic devices today, their
internal processes need a clock signal to synchronize.
Note that the clock plays no part in determining what activities or results are to be
made.
Update: 19/02/2020 CTS, BSC, SRT, TSK Page 2/15
Input Output (State)
CLR CLK J K Q (after ) Operation
1 ↓ 0 0 Q (before ) Hold
1 ↓ 0 1 0 Reset
1 ↓ 1 0 1 Set
1 ↓ 1 1 Q (before ) Toggle
1 1, 0, ↑ Don’t Care Can’t Change -
0 Don’t Care 0 Clear
CLK
J Q
K QCLR
A flip flop (FF) is the simplest digital circuit that has a clock input for
synchronizing its output. The clocked JK-FF will be studied in this lab. It has 4 inputs,
i.e. J, K, CLK (CLOCK) and CLR (CLEAR), and one output Q with Q as its
compliment. Its symbol and truth table (or state table) is as follows.
The first 4 rows indicate that the output Q can change only when the clock transits
from HIGH to LOW (indicated by ↓). Thus its response is synchronized with the clock
and depends on the JK inputs. This flip flop is called a negative (or falling) edge
triggered JK flip flop and the output value between consecutive falling edges is called its
state. However, there is one exception when the input CLR is 0, as shown in the last row
of the table, that immediately clear Q to 0 without having to wait for the clock transition,
i.e. its action is asynchronous.
The output (or timing) waveform of a flip flop is usually accompanied by its clock
waveform. For example, when a JK-FF is put in a toggle mode with J=1, K=1 and
CLR =1, its waveform is as follows.
QCLR
Timing waveform of a JK-FF in toggle mode
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Using states, we can conveniently and
concisely express its operation in the form
of a state diagram where the triggering
clock edges are represented as arrows as
shown in the right figure. In this case the
state sequences repeatedly between 0 and
1.
A sequential digital circuit is a clocked circuit that has one or more flip flops
connected together, possibly using combinational gates. Its simplest one is the counter
that has only a clock input. An example is the following two bit binary counter in which
each state consists of two outputs Q2 and Q1. Its state diagram indicates that the counter
sequences from Q2Q1 = 00, 01, 10, 11 and repeats, giving a count up output.
Q1CLR Q2CLR
Q2 Q1
It should be noted that there
are N2 possible states for a circuit
with N flip flops. However, a
counter sequence can be arbitrarily
designed and may not sequence
through all possible states. For
example, we can design a two bit
counter with either one of the
following state diagram. The left
one gives a counter with modulo 3
and the right one is a counter with
a count down output.
Q2 Q1 Q2 Q1
A more complicated form of a sequential circuit is a finite state machine (FSM)
which has additional inputs other than a clock. One example is a counter with has an
Up/Down input to change its counting sequence. A central processing unit (CPU) in a
computer is an example of a complex FSM.
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C. Materials provided in the experiment
1) Breadboard with components and wires already inserted. During each experiment,
you have to add or delete wires to form a circuit. When the lab is done, please
reconnect them back as shown below.
2) Battery interface board. It is attached to the upper left part of the breadboard as
shown above. Plug a 6V battery jack into it to supply 0 and 6Volt to the horizontal
buses on the breadboard from which red and black wires are inserted. Note that red
wires carry 6Volt while black wires carry 0Volt. They energize all ICs on the
