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2310 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 54, NO. 6, DECEMBER 2005

Fault Simulation and Response Compaction in FullScan Circuits Using HOPE

Sunil R. Das, Life Fellow, IEEE, Chittoor V. Ramamoorthy, Life Fellow, IEEE, Mansour H. Assaf, Member, IEEE,Emil M. Petriu, Fellow, IEEE, Wen-Ben Jone, Senior Member, IEEE, and Mehmet Sahinoglu, Senior Member, IEEE

Abstract—This paper presents results on fault simulation andresponse compaction on ISCAS 89 full scan sequential bench-mark circuits using HOPE—a fault simulator developed forsynchronous sequential circuits that employs parallel fault simu-lation with heuristics to reduce simulation time in the context ofdesigning space-efficient support hardware for built-in self-testingof very large-scale integrated circuits. The techniques realized inthis paper take advantage of the basic ideas of sequence charac-terization previously developed and utilized by the authors forresponse data compaction in the case of ISCAS 85 combinationalbenchmark circuits, using simulation programs ATALANTA,FSIM, and COMPACTEST, under conditions of both stochasticindependence and dependence of single and double line errors inthe selection of specific gates for merger of a pair of output bitstreams from a circuit under test (CUT). These concepts are thenapplied to designing efficient space compression networks in thecase of full scan sequential benchmark circuits using the faultsimulator HOPE.

Index Terms—Built-in self-test (BIST), circuit under test (CUT),detectable error probability estimates, fault simulation usingHOPE, Hamming distance, optimal sequence mergeability, re-sponse compaction, sequence weights, single stuck-line faults,space compactor.

I. INTRODUCTION

WITH continued growth in semiconductor industries anddevelopment of extremely complex systems with higher

levels of integration densities, the real urge to find better andmore efficient methods of testing that ensure reliable opera-tions of chips, a mainstay of today’s many sophisticated dig-ital systems, has become the single most pressing issue to de-sign and test engineers. The very concept of testing has a broadapplicability, and finding highly effective test techniques that

Manuscript received November 11, 2003; revised December 7, 2004. Thiswork was supported in part by the Natural Sciences and Engineering ResearchCouncil of Canada under Grant A 4750.

S. R. Das is with the School of Information Technology and Engineering, Uni-versity of Ottawa, Ottawa, ON K1N 6N5, Canada, and with the Department ofComputer and Information Science, Troy State University-Montgomery, Mont-gomery, AL 36103 USA.

C. V. Ramamoorthy is with the Department of Electrical Engineering andComputer Sciences, Computer Science Division, University of California,Berkeley, CA 94720 USA.

M. H. Assaf and E. M. Petriu are with the School of Information Technologyand Engineering, University of Ottawa, Ottawa, ON K1N 6N5, Canada.

W.-B. Jone is with the Department of Electrical and Computer Engineeringand Computer Science, University of Cincinnati, Cincinnati, OH 45221 USA.

M. Sahinoglu is with the Department of Computer and Information Science,Troy State University-Montgomery, Montgomery, AL 36103 USA.

Digital Object Identifier 10.1109/TIM.2005.858102

Fig. 1. Block diagram of the BIST environment.

Fig. 2. Simulation results of the ISCAS 89 full scan sequential benchmarkcircuits using HOPE under stochastic independence of single and double lineerrors using compacted input test sets.

guarantee correct system performance has been gaining impor-tance [1]–[57]. Consider, for example, medical test and diag-nostic instruments, airplane controllers, and other safety-crit-ical systems that have to be tested before (off-line testing) andduring use (on-line testing). Another application where failurecan have severe economic consequences is real-time transac-tions processing. The testing process in all these circumstancesmust be fast and effective to make sure that such systems operatecorrectly. In general, the cost of testing integrated circuits (ICs)is rather prohibitive; it ranges from 35% to 55% of their totalmanufacturing cost [7]. Besides, testing a chip is also time con-suming, taking up to about one-half of the total design cycle time[8]. The amount of time available for manufacturing, testing,and marketing a product, on the other hand, continues to de-crease. Moreover, as a result of global competition, customersdemand lower cost and better quality products. Therefore, in

0018-9456/$20.00 © 2005 IEEE

DAS et al.: FAULT SIMULATION AND RESPONSE COMPACTION IN FULL SCAN CIRCUITS USING HOPE 2311

Fig. 3. Simulation results of the ISCAS 89 full scan sequential benchmarkcircuits using HOPE under stochastic independence of single and double lineerrors using compacted input test sets.

Fig. 4. Simulation results of the ISCAS 89 full scan sequential benchmarkcircuits using HOPE under stochastic independence of single and double lineerrors using pseudorandom testing.

Fig. 5. Simulation results of the ISCAS 89 full scan sequential benchmarkcircuits using HOPE under stochastic independence of single and double lineerrors using pseudorandom testing.

order to achieve this superior quality at lower cost, testing tech-niques need to be improved.

The conventional testing techniques of digital circuits re-quire application of test patterns generated by a test patterngenerator (TPG) to the circuit under test (CUT) and comparingthe responses produced with known correct circuit responses.

Fig. 6. Simulation results of the ISCAS 89 full scan sequential benchmarkcircuits using HOPE under stochastic dependence of single and double lineerrors using compacted input test sets.

Fig. 7. Simulation results of the ISCAS 89 full scan sequential benchmarkcircuits using HOPE under stochastic dependence of single and double lineerrors using compacted input test sets.

Fig. 8. Simulation results of the ISCAS 89 full scan sequential benchmarkcircuits using HOPE under stochastic dependence of single and double lineerrors using pseudorandom testing.

However, for large circuits, because of higher storage require-ments for the fault-free responses, the test procedures becomevery expensive and hence alternative approaches are sought tominimize the amount of needed storage. Built-in self-testing(BIST) is a design methodology that provides the capability ofsolving many of the problems otherwise encountered in con-ventional testing of digital systems. It combines the concepts of


TABLE IFAULT COVERAGE FOR ISCAS 89 BENCHMARK CIRCUITS USING HOPE (COMPACTED INPUT TEST SETS)

both built-in test (BIT) and self-test (ST) in one. In BIST, testgeneration, test application, and response verification are allaccomplished through built-in hardware, which allows differentparts of a chip to be tested in parallel, thereby reducing therequired testing time, besides eliminating the need for externaltest equipment. As the cost of testing is becoming the majorcomponent of the manufacturing cost of a new product, BISTthus tends to reduce manufacturing, test, and maintenance coststhrough improved diagnosis.

Several companies such as Motorola, AT&T, IBM, AMD,and Intel have incorporated BIST in many of their products [10],[12], [19]–[21]. AT&T, for example, has incorporated BISTinto more than 200 of their chips. The three large programmablelogic arrays and microcode read-only memory (ROM) in theIntel 80 386 microprocessor were built-in self-tested [56]. Thegeneral-purpose microprocessor chip Alpha AXP21164 andMotorola microprocessor 68020 were also tested using BISTtechniques [12], [56]. More recently, Intel, for its PentiumPro architecture microprocessor, with its unique requirementsof meeting very high production goals, superior performancestandards, and impeccable test quality, put strong emphasison its design-for-test (DFT) direction [21]. A set of con-straints, however, limits Intel’s ability to tenaciously explore

Fig. 9. Simulation results of the ISCAS 89 full scan sequential benchmarkcircuits using HOPE under stochastic dependence of single and double lineerrors using pseudorandom testing.

DFT and test generation techniques, i.e., full or partial scanor scan-based BIST [4]. AMD’s K6 processor is a reducedinstruction set computer (RISC) core named enhanced RISC86microarchitecture [20]. K6 processor incorporates BIST intoits DFT process. Each RAM array of K6 processor has its


TABLE IIFAULT COVERAGE FOR ISCAS 89 BENCHMARK CIRCUITS USING HOPE (RANDOM TESTING; INITIAL RANDOM NUMBER GENERATOR SEED = 999)

own BIST controller. BIST executes simultaneously on all ofthe arrays for a predefined number of clock cycles that en-sures completion for the largest array. Hence, BIST executiontime depends on the size of the largest array [4]. AMD usescommercial automatic test pattern generation tool to createscan test patterns for stuck-faults in their processor. The DFTframework for a 500-MHz IBM S/390 microprocessor utilizesa wide range of tests and techniques to ensure superb reliabilityof components within a system [4]. Register arrays are testedthrough the scan chain, while nonregister memories are testedwith programmable RAM BIST. Hewlett-Packard’s PA8500is a 0.25- m superscalar processor that achieves fast butthorough test with its cache test hardware’s ability to performMarch tests, which is an effective way to detect several kindsof functional faults [19]. Digital’s Alpha 21 164 processorcombines both structured and adhoc DFT solutions, for whicha combination of hardware and software BIST was adopted [4].Sun Microsystems’ UltraSparc processor incorporates severalDFT constructs as well. The achievement of its quality perfor-mance coupled with reduced chip area conflicts with a designrequirement that is easy to debug, test, and manufacture [4].

BIST is also widely used to test embedded regular structuresthat exhibit a high degree of periodicity such as memory arrays

(SRAMs, ROMs, FIFOs, and registers). These types of circuitsdo not require complex extra hardware for test generation andresponse compaction. Also, including BIST in these circuits canguarantee high fault coverage with zero aliasing. Unlike regularcircuits, random-logic circuits cannot be adequately tested onlywith BIST techniques, since generating adequate on-chip testsets using simple hardware is a difficult task to be accomplished.Moreover, since test responses generated by random-logic cir-cuits seldom exhibit regularity, it is extremely difficult to ensurezero aliasing compaction. Therefore, random-logic circuits aremost usually tested using a combination of BIST, scan designtechniques, and external test equipment.

A typical BIST environment, as shown in the block diagramrepresentation of Fig. 1, uses a test pattern generator (TPG)that sends its outputs to a circuit under test (CUT), and outputstreams from the CUT are fed into a test data analyzer. A faultis detected if the test sequence is different from the response ofthe fault-free circuit. The test data analyzer is comprised of aresponse compaction unit (RCU), storage for the fault-free re-sponses of the CUT, and a comparator. In order to reduce theamount of data represented by the fault-free and faulty CUT re-sponses, data compression is used to create signatures (short bi-nary sequences) from the CUT and its corresponding fault-free


TABLE IIIFAULT COVERAGE FOR ISCAS 89 BENCHMARK CIRCUITS USING HOPE (COMPACTED INPUT TEST SETS)

circuit. Signatures are compared and faults are detected if amatch does not occur. BIST techniques may be used duringnormal functional operating conditions of the unit under test(on-line testing), as well as when a system is not carrying out itsnormal functions (off-line testing). In the case where detectingreal-time errors is not that important, systems, boards, and chipscan be tested in off-line BIST mode. BIST techniques use pseu-dorandom, or pseudoexhaustive TPGs, or on-chip storing of re-duced test sets. These days, testing logic circuits exhaustively isseldom used, since only a few test patterns are needed to ensurefull fault coverage for single stuck-line faults [12]. Reduced pat-tern test sets can be generated using existing algorithms such asFAN and others. Built-in test generators can often generate suchreduced test sets at low cost, making BIST techniques suitablefor on-chip self-testing.

The primary concern of the current paper is the general re-sponse compaction process of built-in self-testing techniquesthat translates into a process of reducing the test response fromthe CUT to a signature. Instead of comparing bit-by-bit thefault-free responses to the observed outputs of the CUT as inconventional testing methods, the observed signature is com-pared to the correct one, thereby reducing the storage needed for

the correct circuit responses. The response compaction in BISTis carried out through a space compaction unit followed by timecompaction. In general, input sequences coming from a CUTare fed into a space compactor, providing output streams ofbits such that ; most often, test responses are compressedinto only one sequence ( ). Space compaction brings a solu-tion to the problem of achieving high-quality built-in self-testingof complex chips without the necessity of monitoring a largenumber of internal test points, thereby reducing both testingtime and area overhead by merging test sequences coming fromthese internal test points into a single stream of bits. This singlebit stream of length is eventually fed into a time compactor,and finally a shorter sequence of length ( ) is obtainedat the output. The extra logic representing the compaction cir-cuit, however, must be as simple as possible, to be easily em-bedded within the CUT and should not introduce signal delaysto affect either the test execution time or normal functionalityof the circuit being tested. Moreover, the length of the signa-ture must be as short as it can be in order to minimize theamount of memory needed to store the fault-free response signa-tures. Also, signatures derived from faulty output responses andtheir corresponding fault-free signatures should not be the same,


TABLE IVFAULT COVERAGE FOR ISCAS 89 BENCHMARK CIRCUITS USING HOPE (RANDOM TESTING; INITIAL RANDOM NUMBER GENERATOR SEED = 999)

which unfortunately is not always the case.A fundamental problem with compaction techniques is error

masking or aliasing [7], [49], [56] which occurs when the signa-tures from faulty output responses map into the fault-free signa-tures, usually calculated by identifying a good circuit, applyingtest patterns to it, and then having the compaction unit generatethe fault-free references. Aliasing causes loss of information,which affects the test quality of BIST and reduces the fault cov-erage (the number of faults detected, after compaction, over thetotal number of faults injected). Several methods have been sug-gested in the literature for computing the aliasing probability.The exact computation of this aliasing probability is known tobe an NP-hard problem [58]. In practice, high fault coverage,over 99%, is generally required, and thus, any space compres-sion technique that maintains more percentage error coverageinformation is considered worthy of investigation.

This paper specifically deals with the general problem of de-signing space-efficient support hardware for BIST of full scansequential circuits using fault simulation program HOPE [60].HOPE is a fault simulator for synchronous sequential circuitsdeveloped at the Virginia Polytechnic Institute and State Univer-sity and employs parallel fault simulation with several heuristics

to reduce fault simulation time, besides providing many advan-tages over existing simulators. The compaction techniques usedin this paper with simulator HOPE take advantage of certain in-herent properties of the test responses of the CUT, together withthe knowledge of their failure probabilities. A major objectiveto realize in space compaction is to provide methods that aresimple, suitable for on-chip self-testing, require low area over-head, and have little adverse impact on the overall CUT per-formance. With that objective in perspective, compaction tech-niques were developed in the paper that take advantage of somewell known concepts, i.e., those of Hamming distance, sequenceweights, and derived sequences as utilized by the authors earlierin sequence characterization [46], [49], [57], in conjunction withthe probabilities of error occurrence for optimal mergeability ofa pair of output bit streams from the CUT. The proposed tech-niques guarantee simple design and achieve a high measure offault coverage for single stuck-line faults with low CPU simula-tion time and acceptable area overhead, as evident from exten-sive simulation runs on the ISCAS 89 full scan sequential bench-mark circuits with simulator HOPE, under conditions of bothstochastic independence and dependence of single and doubleline output errors.


TABLE VFAULT COVERAGE FOR ISCAS 89 BENCHMARK CIRCUITS USING HOPE (COMPACTED INPUT TEST SETS)

II. BRIEF OVERVIEW OF TEST COMPACTION TECHNIQUES

The choice of a compression technique is mainly influencedby hardware considerations and loss of effective fault coveragedue to fault masking or aliasing. In this section, we first brieflyreview some of the important test compaction techniques inspace for BIST that have been proposed in the literature. Wedescribe these, concentrating only on some of their relevantproperties like the area overhead, fault coverage, error maskingprobability, etc. There also exist a number of efficient time com-paction schemes including ones counting, syndrome testing,transition counting, signature analysis, and others, which arealso considered. Some of the common space compression tech-niques include the parity tree space compaction, hybrid spacecompression, dynamic space compression, quadratic functionscompaction, programmable space compaction, and cumulativebalance testing. The parity tree compactor circuits [36], [39],[46], [49], [50] are composed of only XOR gates. An XOR gatehas very good signal-to-error propagation properties that arequite desirable for space compression. Functions realized byparity tree compactors are of the form .

The parity tree space compactor propagates all errors that ap-pear on an odd number of its inputs. Thereby, errors that appearon an even number of parity tree circuit inputs are masked. Asexperimentally demonstrated, most single stuck-line faults aredetected in parity tree space compaction using pseudorandominput test patterns and deterministic reduced test sets [49], [57].

The hybrid space compression (HSC) technique, originallyproposed by Li and Robinson [38], uses AND, OR, and XOR

logic gates as output compaction tools to compress the mul-tiple outputs of a CUT into a single line. The compaction tree isconstructed based on the detectable error probability estimates

. A modified version of the HSCmethod, called dynamic space compression (DSC), was subse-quently proposed by Jone and Das [41]. Instead of assigningstatic values for the probabilities of single errors and doubleerrors , the DSC method dynamically estimates those valuesbased on the CUT structure during the computation process.The values of and are determined based on the numberof single lines and shared lines connected to an output. A gen-eral theory to predict the performance of the space compression


TABLE VIFAULT COVERAGE FOR ISCAS 89 BENCHMARK CIRCUITS USING HOPE (RANDOM TESTING; INITIAL RANDOM NUMBER GENERATOR SEED = 999)

techniques was also developed. Experimental results show thatthe information loss, combined with syndrome counting as timecompactor, is between 0% and 12.7%. DSC was later improved,in which some circuit-specific information was used to calcu-late the probabilities [42]. However, neither HSC nor DSC doesprovide an adequate measure of fault coverage because theyboth rely on estimates of error detection probabilities. Quadraticfunctions compaction (QFC) uses quadratic functions to con-struct the space compaction circuits, and has been shown to re-duce aliasing errors [40]. In QFC, the observed output responses

of the CUT are processed and compressed in a se-rial fashion based on a function of the type

, where and are blocks oflength , for . A new approach termed pro-grammable space compaction (PSC) has recently been proposedfor designing low-cost space compactors that provide high faultcoverage [37]. In PSC, circuit-specific space compactors are de-signed to increase the likelihood of error propagation. However,PSC does not guarantee zero aliasing. A compaction circuit thatminimizes aliasing and has the lowest cost can only be found byexhaustively enumerating all 2 -input Boolean functions,where represents the number of primary outputs of the CUT.

A new class of space compactors based on parity tree cir-cuits was recently proposed by Chakrabarty and Hayes [56].

The method is based on multiplexed parity trees (MPTs) andintroduces zero aliasing. Multiplexed parity trees perform spacecompaction of test responses by combining the error propaga-tion properties of multiplexers and parity trees through multipletime-steps. The authors show that the associated hardware over-head is moderate, and very high fault coverage is obtained forfaults in the CUT, including even those in the compactor. Quiterecently, a new space compaction approach for IP cores basedon the use of orthogonal transmission functions was suggestedin [47], which provides zero aliasing for all errors with optimalcompaction ratio. Other approaches were given in [52] and [53]that are supposed to reduce test time and test data volume andimprove testability with high compaction ratios, and could beapplicable to several industrial circuits.

We now briefly examine some time compaction methods likeones counting, syndrome testing, transition counting, signatureanalysis, and others. Ones counting [24] uses as its signaturethe number of ones in the binary circuit response stream. Thehardware that represents the compaction unit consists of asimple counter, and is independent of the CUT; it only dependson the nature of the test response. Signature values do notdepend on the order in which the input test patterns are appliedto the CUT. In syndrome counting [27], all the 2 input patternsare exhaustively applied to an -input combinational circuit.


TABLE VIIFAULT COVERAGE FOR ISCAS 89 BENCHMARK CIRCUITS USING HOPE (COMPACTED INPUT TEST SETS. � INDICATES FAULTS

WERE INJECTED INTO CUT + COMPACTOR)

The syndrome , which is given by the normalized number ofones in the response stream, is defined as , with

being the number of minterms of the function being imple-mented by the single-output CUT. Any switching function canbe so realized that all its single stuck-line faults are syndrome-testable. Transition counting [25] counts the number of timesthe output bit stream changes from one to zero and vice versa.In transition counting, the signature length is less than or equalto , with being the length of a response stream. Theerror masking probability takes high values when the signaturevalue is close to 2 and low values when it is close to zero or. In Walsh spectral analysis [28], [29], switching functions are

represented by their spectral coefficients that are compared toknown correct coefficients values. In a sense, in this method, thetruth table of the given switching function is basically verified.The process of collecting and comparing a subset of the com-plete set of Walsh functions is described as a mechanism for datacompaction. The use of spectral coefficients promises higherpercentage of error coverage, whereas the resulting higher areaoverhead for generating them is deemed as a disadvantage.

In parity checking [31], the response bit stream comingfrom a circuit under test reduces a multitude of output data

to a signature of length 1 bit. The single bit signature hasa value that equals the parity of the test response sequence.Parity checking detects all errors involving an odd numberof bits, while faults that give rise to an even number of errorbits are not detected. This method is relatively ineffectivesince a large number of possible response bit streams froma faulty circuit will result in the same parity as that of thecorrect bit stream. All single stuck-line faults in fanout-freecircuits are detected by the parity check technique. Theseobvious shortcomings of parity checking are eliminated inmethods devised based on single-output parity bit signature[31] and multiple-output parity bit signature [32], [34]. Sig-nature analysis is probably the most popular time compactiontechnique currently available [26]. It uses linear feedback shiftregisters (LFSRs) consisting of flip-flops and exclusive-OR

(XOR) gates. The signature analysis technique is based on theconcept of cyclic redundancy checking (CRC). LFSRs areused for generating pseudorandom input test patterns, andfor response compaction as well. The nature of the generatedsequence patterns is determined by the LFSR’s characteristicpolynomial as defined by its interconnection structure. Atest-input sequence is fed into the signature analyzer,


TABLE VIIIFAULT COVERAGE FOR ISCAS 89 BENCHMARK CIRCUITS USING HOPE (RANDOM TESTING; INITIAL RANDOM NUMBER GENERATOR SEED = 999)

which is divided by the characteristic polynomial of thesignature analyzer’s LFSR. The remainder obtained by di-viding by over a Galois field such that .

represents the state of the LFSR, with beingthe corresponding quotient. In other words, represents theobserved signature.

Signature analysis involves comparing the observed signatureto a known fault-free signature . An error is detected

if these two signatures differ. Suppose that is the correctresponse and is the faulty one, where

is an error polynomial; it can be shown that aliasing oc-curs whenever is a multiple of . The masking prob-ability in this case is estimated as 1/2 , where is the numberof flip-flop stages in the LFSR. When is larger than 16, thealiasing probability is negligible. Many commercial applica-tions have reported good success with LFSR-implemented sig-nature analysis.

Different methods for computing and reducing the aliasingprobability in signature analysis have been proposed, e.g., thesignature analysis model proposed by Williams et al. [30] thatuses Markov chains and derives an upper bound on the aliasingprobability in terms of the test length and probability of anerror’s occurring at the output of the CUT. Another approach tothe computation of aliasing probability is presented in [33]. An

error pattern in signature analysis causes aliasing if and only if itis a codeword in the cyclic code generated by the LFSR’s char-acteristic polynomial. Unlike other methods, the fault coveragein signature analysis may be improved without changing the testset. This can be done by playing with the length of the LFSR orby using a different characteristic polynomial . As demon-strated in [35], for short test length, signature analysis detects allsingle-bit errors. However, there is no known theory that char-acterizes fault detection in signature analysis. Testing using twodifferent compaction schemes in parallel has also been exten-sively investigated. The combination of signature analysis andtransition counting has also been analyzed [49], which showsthat using simultaneously both techniques leads to a very smalloverlap in their error masking. As a result of using two differentcompaction schemes in parallel, the fault coverage is improved,while the fault signature size and hardware overhead are greatlyincreased.

III. DESIGNING COMPACTION TREES BASED ON SEQUENCE

CHARACTERIZATION AND STOCHASTIC INDEPENDENCE AND

DEPENDENCE OF LINE ERRORS

The principal idea in space compaction is to compressfunctional test outputs of the CUT possibly into one single test


TABLE IXFAULT COVERAGE FOR ISCAS 89 BENCHMARK CIRCUITS USING HOPE (COMPACTED INPUT TEST SETS)

output line to derive the CUT signature without sacrificing toomuch information in the process. Generally, space compres-sion has been accomplished using XOR gates in cascade or in atree structure. We adopt a combination of both cascade and treestructures (cascade-tree) for our framework with AND (NAND),OR (NOR), and XOR (XNOR) operators. The logic function to beselected to build the compaction tree is determined solely by thecharacteristics of the sequences that are inputs to the gates basedon some optimal mergeability criteria developed earlier by theauthors [46], [49], [57]. The basic theme of the approaches pro-posed is to select appropriate logic gates to merge two candidateoutput lines of the CUT under conditions of stochastic indepen-dence and dependence of single and double line errors, usingsequence characterization and other concepts introduced by theauthors. However, the criteria of selecting a number of CUToutput lines for optimal generalized sequence mergeability werealso developed and utilized in the design of space compressionnetworks, based on stochastic independence of multiple lineerrors, and also on stochastic dependence of multiple line er-rors using the concept of generalized detectable or missed errorprobability estimates [46], [50], [57], with extensive simulationsconducted with ATALANTA, FSIM, and COM PACTEST [59],

[61], [62]; however, optimal generalized sequence mergeabilityis not the concern of this paper, and as such is not discussed .

In the following the mathematical basis of the approaches isbriefly given with the introduction of appropriate notations andterminologies.

A. Hamming Distance, Sequence Weights, and DerivedSequences

Let represent a pair of output sequences of a CUT oflength each, where the length is the number of bit positionsin and . Let represent the Hamming distancebetween and (the number of bit positions in which and

differ).Definition: The first-order one-weight, denoted by ,

of a sequence is the number of ones in the sequence. Simi-larly, the first-order zero-weight, denoted by , of a se-quence is the number of zeroes in the sequence.

Example: Consider an output sequence pair withand . The length of

both output streams is eight ( ). The Hamming dis-tance between and is . The first-order


TABLE XFAULT COVERAGE FOR ISCAS 89 BENCHMARK CIRCUITS USING HOPE (RANDOM TESTING; INITIAL RANDOM NUMBER GENERATOR SEED = 999)

one-weights and zero-weights of and are ,, , and , respectively.

Property: For any sequence , it can be shown that.

For the output sequence given in the ex-ample above, we have found that and

. Therefore, it is obvious that .Definition: Consider an output sequence pair of

equal length . Then the sequence pair derived by discardingthe bit positions in which the two sequences differ (and indi-cated by a dash) is called the second-order derived sequencepair .

In this paper, we will denote the derived sequence of a se-quence by , its first-order one-weight by , and itsfirst-order zero-weight by .

Example: For given in the example above,. The first-order one-

weights and zero-weights of the derived pair are, , , and .

Property: For any second-order derived sequences ,we have and , i.e.,as shown in the example above, for the same output sequence

pair given above, we have shown thatand .

By the aforesaid property, when no ambiguity arises, we willdenote one- and zero-weights for the derived sequence pair bysimply and , respectively. The length of the derived se-quence pair will be denoted by where .Also, since is always zero, we will simply useto denote .That is, for in the exampleabove, , , , and

. Therefore, and.

Property: For every distinct pair of output sequencesat the output of a CUT, the corresponding derived pairof equal length is distinct.

Two derived sequence pairs may have the same length , butthey are still distinct and not identical.

Property: Two derived sequence pairs andof original output stream pairs and

having the same length are identical. Thereby,if and only if .

Consider , ,, and as four


TABLE XIFAULT COVERAGE FOR ISCAS 89 BENCHMARK CIRCUITS USING HOPE (COMPACTED INPUT TEST SETS)

output sequence streams of a CUT. Let andbe two distinct output pairs and , andtheir corresponding derived sequence pairs, re-

spectively, such that and. Both of the derived se-

quence pairs have the same length , but they are notidentical.

However, in general, it is not expected that any two distinctpairs of sequences at the output of a CUT will be identical andhence the possibility of the corresponding derived pairs beingidentical is also remote.

We can extend the concept of one-weight and zero-weightto deal with sequences readily, but since theconcepts are not used in this paper, their discussions are omitted.

B. Optimal Pairwise Mergeability and Gate Selection

In this section we will briefly summarize the key resultsconcerning optimal pairwise mergeability of response data atthe CUT output in the design of space compactors. These willbe provided in the form of certain theorems without proofsunder conditions of stochastic dependence of line errors, of

which the details could be found in [49] and [57]. In the caseof stochastic dependence of line errors at the CUT output, wecan assign distinct probabilities of error occurrence in differentlines. The gate selection was primarily based on optimal merge-ability criteria established utilizing the properties of Hammingdistance, sequence weights, and derived sequences, togetherwith the concept of detectable error probability estimate [38]for a two-input logic function, under condition of stochasticdependence of single and double line errors at the output of aCUT.

C. Effects of Error Probabilities in Selection of Gates forOptimal Merger

Li and Robinson [38] defined the detectable error probabilityestimate for a two-input logic function given two input se-quences of length as follows: ,where is the probability of single error effect felt at the outputof the CUT; is the probability of double error effect felt at theoutput of the CUT; is the number of single line errors at theoutput of gate if gate is used for merger; and is the numberof double line errors at the output of gate if gate is used formerger.


TABLE XIIFAULT COVERAGE FOR ISCAS 89 BENCHMARK CIRCUITS USING HOPE (RANDOM TESTING; INITIAL RANDOM NUMBER GENERATOR SEED = 999)

Based on the computation of the detectable error probabilityestimates of Li and Robinson as given above, we deduce thefollowing results that profoundly influence the selection of gatesfor optimal merger.

Theorem: For an output sequence pair of lengthand Hamming distance , an AND (NAND) gate is preferableto an XOR (XNOR) gate for optimal merger if

.Theorem: For an output sequence pair of length

and Hamming distance , an OR (NOR) gate is preferable to anXOR (XNOR) gate for optimal merger if

.Theorem: For an output sequence pair of length

and Hamming distance , an AND (NAND) gate is preferable toan OR (NOR) gate for optimal merger if .

Theorem: For two gates and , is preferable to foroptimal merger if and only if .

IV. EXPERIMENTAL RESULTS

To demonstrate the feasibility of the proposed space compres-sion schemes, independent simulations were conducted on var-ious ISCAS 89 full scan sequential benchmark circuits using

HOPE [60], a fault simulation program developed at the Vir-ginia Polytechnic Institute and State University, to generate thefault-free output sequences needed to construct our space com-pactor circuits and to test the benchmark circuits using deter-ministic compacted input test sets, accompanied with randomtest sessions that generate pseudorandom test sets with differentvalues of random number generator seeds.

For each circuit, we determined the number of injected faults,number of applied test vectors (after compaction), CPU simu-lation time, and fault coverage (without space compactors andwith space compactors) by considering only the combinationalpart of the circuit (full scan version) or using the completesequential circuit, assuming either stochastic independenceof single and double line errors or different values of theirfailure probabilities (under condition of stochastic dependenceof single and double line errors ), by running the program onSUN SPARC 5 workstation. The extensive simulation resultsare presented in the form of graphs and tables that follow. TheCPU times needed for simulations of all the different ISCAS89 full scan sequential benchmark circuits on SUN SPARC 5workstation were in the range of 300 ms–23 457 s, though forsome of the largest circuits, simulations could not be completedsince memory, CPU time, and disk usage limits did not permit.


TABLE XIIIFAULT COVERAGE FOR ISCAS 89 BENCHMARK CIRCUITS USING HOPE (COMPACTED INPUT TEST SETS)

The hardware overhead for the designed space compactors isnot given in this paper, though for all the circuits, the overheadwas well within acceptable limits.

Figs. 2 and 4 show fault coverage for all the benchmarkcircuits without compactors when stochastic independenceof single and double line errors was assumed, using deter-ministic compacted input test sets and pseudorandom testing,respectively, whereas Figs. 3 and 5 show CPU simulation timesfor these circuits under identical conditions. The benchmarkcircuits were actually tested here as combinational circuits. Onthe other hand, Figs. 6 and 8 show fault coverage for all thebenchmark circuits, using deterministic compacted input testsets and pseudorandom testing, respectively, for the probabilityvalues of single and double line errors ( , ) being equal to(0.66, 0.33), while Figs. 7 and 9 show their CPU simulationtimes under identical situations. Here the benchmark circuitswere tested as sequential circuits. Tables I–VI show the dif-ferent simulation results for ISCAS 89 benchmark circuitsunder stochastic dependence of single and double line errorswith values of ( , ) being equal to (0.33, 0.66), (0.90, 0.10),and (0.10, 0.90) on application of compacted test sets and underpseudorandom testing for combinational parts of the circuits,while Tables IX–XIV show the same for the different circuits

with all the above values of line errors ( , ) treating themas sequential circuits. Finally, Tables VII and VIII show similarresults for deterministic compacted testing of all the sequentialbenchmark circuits.

V. CONCLUDING REMARKS

The design of space-efficient BIST support hardware in thesynthesis of digital integrated circuits is of great significance.This paper reports compression techniques of test data outputsfor full scan digital sequential circuits that facilitate the designof these kinds of space-efficient support hardware. The pro-posed techniques use AND (NAND), OR (NOR), and XOR (XNOR)gates as appropriate to construct an output compaction tree thatcompresses the functional outputs of the CUT to a single line.The compaction tree is generated based on sequence charac-terization and utilizing the concepts of Hamming distance, se-quence weights, and derived sequences. The logic functions se-lected to build the compaction tree are determined primarily bythe characteristics of the sequences that are inputs to the logicgates. The optimal mergeability criteria were obtained on theassumption of stochastic independence as well as dependence


TABLE XIVFAULT COVERAGE FOR ISCAS 89 BENCHMARK CIRCUITS USING HOPE (RANDOM TESTING; INITIAL RANDOM NUMBER GENERATOR SEED = 999)

of single and double line errors. In the case of stochastic de-pendence, output bit stream selection is based on calculatingthe detectable error probability estimates using an empirical for-mula developed by Li and Robinson [38]. It should be recalledthat the effectiveness of the proposed approaches is criticallydependent on the probabilities of error occurrence in differentlines of the CUT, and this dependence may be affected by thecircuit structure, partitioning, etc., e.g., by the number of in-puts, outputs, internal lines, and types of gates the circuit isdesigned of and the way it is partitioned. In actual situations,the probability values for error occurrence in particular circuitshave to be experimentally determined, that is, these are a pos-teriori probabilities rather than a priori probabilities. If the cir-cuit structure changes, these probability values change, and evi-dently the corresponding compression networks that have to bedesigned based on pairwise optimal mergeability criteria changeas well.

Another point should be considered here as well. Since theempirical formula used for computing the detectable error prob-ability estimates in the gate selection process uses exact valuesof these a posteriori probabilities of error occurrence, unless theformula is modified, whenever only intervals on the probabilityvalues are given rather than their exact values, they cannot beused as such in the gate selection process, except only to provide

two extremes of selections consistent with the probability inter-vals. From the analytical viewpoint, the major issue involves thecomputation of the detectable error probability estimates, whichis rather simple in the present case because of two-line mergers,compared to that in the case of generalized mergeability, wherethe computation is really intensive. Since the major emphasisof the paper is in synthesizing compaction networks that pro-vide improved fault coverage for fixed complexity, realizing atradeoff between coverage and complexity (storage) than con-ventional techniques, the complexity issues were not addressedin depth. Also, zero aliasing compaction [45], [48] was not em-phasized in the present study, but rather an attempt was madesimply to reinforce the connection between the input test setsand their lengths, in their reduction into recommended algo-rithms for the design of space-efficient compaction networks.

ACKNOWLEDGMENT

The authors are extremely grateful to the anonymous re-viewers for their constructive comments that greatly helpedin the preparation of the revised version of the manuscript.The authors are also thankful to the Associate Editor of thisTRANSACTIONS for his helpful suggestions and kind encour-agement.


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Sunil R. Das (M’70–SM’90–F’94–LF’04) receivedthe B.Sc. degree (honors) in physics, the M.Sc.(Tech.) degree, and the Ph.D. degree in radiophysicsand electronics from the University of Calcutta,Calcutta, West Bengal, India.

He is an Emeritus Professor of Electrical andComputer Engineering at the School of Informa-tion Technology and Engineering, University ofOttawa, Ottawa, ON, Canada, and a Professor ofComputer and Information Science, Troy StateUniversity-Montgomery, Montgomery, AL. He

previously held academic and research positions with the University of Cal-ifornia, Berkeley; Stanford University, Stanford, CA (on sabbatical leave);National Chiao Tung University, Hsinchu, Taiwan, R.O.C.; and the Universityof Calcutta. He has published around 300 papers in the areas of switching andautomata theory, digital logic design, threshold logic, fault-tolerant computing,built-in self-test with emphasis on embedded cores-based systems-on-chip,microprogramming and microarchitecture, microcode optimization, appliedtheory of graphs, and combinatorics. He is an Associate Editor of the In-ternational Journal of Computers and Applications, a Regional Editor forInformation Technology Journal, and a member of the Editorial Board anda Regional Editor for Canada of VLSI Design: An International Journal ofCustom-Chip Design, Simulation and Testing. He is a former Associate Editorof SIGDA Newsletter, International Journal of Computer Aided VLSI Design,and International Journal of Parallel and Distributed Systems and Networks.He is a Coeditor (with P. K. Srimani) of Distributed Mutual Exclusion Al-gorithms (Los Alamitos, CA: IEEE Computer Society Press, 1992) and theCoauthor (with C. L. Sheng) of Digital Logic Design (Norwood, NJ: Ablex,to be published).

Dr. Das is a Fellow of the Society for Design and Process Science and theCanadian Academy of Engineering. He is a Member of the IEEE Computer So-ciety, IEEE Systems, Man, and Cybernetics Society, IEEE Circuits and SystemsSociety, and IEEE Instrumentation and Measurement Society. He is a Memberof the Association for Computing Machinery. He received the IEEE ComputerSociety’s Technical Achievement Award in 1996 and its Meritorious ServiceAward in 1997. He became a Golden Core Member of the IEEE Computer So-ciety in 1998. He has received many Certificates of Appreciation from the IEEECircuit and Systems Society. He was on the Technical Program Committees andOrganizing Committees of many IEEE and non-IEEE international conferences,symposia, and workshops, and also acted as Session Organizer, Session Chair,and Panelist. He became a Delegate of Good People, Good Deeds of the Re-public of China in 1981. He was listed in Marquis Who’s Who biographicaldirectory of the computer graphics industry in 1984. He was Managing Ed-itor of the IEEE VLSI TECHNICAL BULLETIN since its inception. He was anExecutive Committee Member of the IEEE Computer Society Technical Com-mittee on VLSI. He was an Associate Editor of the IEEE TRANSACTIONS ON

SYSTEMS, MAN, AND CYBERNETICS from 1991 until very recently. He is cur-rently an Associate Editor of the IEEE TRANSACTIONS ON INSTRUMENTATION

AND MEASUREMENT. He is a former Administrative Committee Member of theIEEE Systems, Man, and Cybernetics Society, and a former Associate Editorof the IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION SYSTEMS

(for two consecutive terms). He was Cochair of the IEEE Computer SocietyStudent Activities Committee from Region 7 (Canada). He was the AssociateGuest Editor of the IEEE Journal of Solid-State Circuits Special Issues on Mi-croelectronic Systems. With R. Rajsuman, he was a Co-Guest Editor of the IEEETRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT Special Section onInnovations in VLSI Test Equipments (October 2003) and Future of Semicon-ductor Test (October 2005). He was a corecipient of the Rudolph Christian KarlDiesel Best Paper Award of the Society for Design and Process Science for apaper presented at the Fifth Biennial World Conference on Integrated Designand Process Technology, Dallas, TX, 2000, and the IEEE 2003 Donald G. FinkPrize Paper Award for a paper published in the December 2001 issue of the IEEETRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT.

Chittoor V. Ramamoorthy (M’57–SM’76–F’78–LF’93) received two undergraduate degrees inphysics and technology from the University ofMadras, Madras, India, two graduate degrees inmechanical engineering from the University ofCalifornia, Berkeley, and M.S. and Ph.D. degreesfrom Harvard University, Cambridge, MA, in ap-plied mathematics (computer science), in 1964. Hiseducation was supported by the Computer Divisionof the Honeywell Inc., Waltham, MA, a company hewas associated with till 1967, last as a Senior Staff

Scientist.He later joined the University of Texas, Austin as a Professor in the De-

partment of Electrical Engineering and Computer Science. After serving as aChairman of the Department, he joined the University of California, Berkeley,in 1972 as a Professor of Electrical Engineering and Computer Sciences, Com-puter Science Division, a position that he still holds as Professor Emeritus. Hesupervised more than 70 doctoral students in his career. He has held the ControlData Distinguished Professorship at the University of Minnesota, Minneapolis,and Grace Hopper Chair at the U. S. Naval Postgraduate School, Monterey, CA.He was also a Visiting Professor at the Northwestern University, Evanston, IL,and a Visiting Research Professor at the University of Illinois, Urbana-Cham-paign. He is a Senior Research Fellow at the ICC Institute of the Universityof Texas, Austin. He served as the Editor-in-Chief of the IEEE TRANSACTIONS

ON SOFTWARE ENGINEERING. He is the founding Editor-in- Chief of the IEEETRANSACTIONS ON KNOWLEDGE AND DATA ENGINEERING, which recently pub-lished a Special Issue in his honor. He is also the founding Co-Editor-in-Chiefof the International Journal of Systems Integration published by Elsevier North-Holland, NY and of the Journal for Design and Process Science published bySDPS, TX. He served in various capacities in the IEEE Computer Society in-cluding as its First Vice President, and a Governing Board Member. He servedon several Advisory Boards of the Federal Government and of the Academiathat include the United States Army, Navy, Air Force, DOE’s Los Alamos Lab,University of Texas, and State University System of Florida. He is one of thefounding Directors of the International Institute of Systems Integration in Camp-inas, Brazil, supported by the Federal Government of Brazil, and for severalyears, was a Member of the International Board of Advisors of the Institute ofSystems Science of the National University of Singapore.

Dr. Ramamoorthy received the Group Award and Taylor Booth Award for ed-ucation, Richard Merwin Award for outstanding professional contributions, andGolden Core Recognition from the IEEE Computer Society . He is the recipientof the IEEE Centennial Medal, and IEEE Millennium Medal. He also receivedthe Computer Society’s 2000 Kanai-Hitachi Award for pioneering and funda-mental contributions in parallel and distributed computing. He is the Fellow ofthe Society for Design and Process Science, from which he received the R. T.Yeh Distinguished Achievement Award in 1997. He also received the Best PaperAward from the IEEE Computer Society in 1987. Three international confer-ences and one UC Berkeley Graduate Student Research Award were organizedin his honor.

Mansour H. Assaf (M’02) received the Honors de-gree in applied physics from the Lebanese Universityin Beirut in 1989 and the B.A.Sc., M.A.Sc., and Ph.D.degrees in electrical engineering from the Universityof Ottawa, Ottawa, ON, Canada, in 1994, 1996, and2003, respectively.

From 1994 to 1996, he was with the Fault-Tol-erant Computing Group of the University of Ottawa,where he studied and worked as a Researcher. Afterworking with Applications Technology, a subsidiaryof Lernout and Hauspie Speech, McLean, VA, in the

area of software localization and natural language processing, he joined theSensing and Modeling Research Laboratory of the University of Ottawa, wherehe currently works on projects in the field of human-computer interaction,three-dimensional modeling, and virtual environments. His research interestsare in the areas of human–computer interactions and perceptual-user interfaces,and in fault diagnosis in digital systems.

Dr. Assaf is a corecipient of the IEEE 2003 Donald G. Fink Prize Paper Awardfor a paper published in the December 2001 issue of the IEEE TRANSACTIONS

ON INSTRUMENTATION AND MEASUREMENT.


Emil M. Petriu (M’86–SM’88–F’01) is a Professorand University Research Chair in the School of Infor-mation Technology and Engineering, University ofOttawa, Ottawa, ON, Canada.

His research interests include robot sensing andperception, intelligent sensors, interactive virtualenvironments, soft computing, digital integratedcircuit testing. He has published more than 200technical papers, authored two books, edited twoother books, and received two patents.

Dr. Petriu is a Fellow of the Canadian Academyof Engineering and the Engineering Institute of Canada. He is a corecipient ofthe IEEE 2003 Donald G. Fink Prize Paper Award for a paper published in theDecember 2001 issue of the IEEE TRANSACTIONS ON INSTRUMENTATION AND

MEASUREMENT and a recipient of the 2003 IEEE Instrumentation and Mea-surement Society Award. He is Chair of TC-15 Virtual Systems and Co-Chairof TC-28 Instrumentation and Measurement for Robotics and Automation andTC-30 Security and Contraband Detection of the IEEE Instrumentation andMeasurement Society. He is an Associate Editor of the IEEE TRANSACTIONS ON

INSTRUMENTATION AND MEASUREMENT and a Member of the Editorial Boardof the IEEE INSTRUMENTATION AND MEASUREMENT MAGAZINE.

Wen-Ben Jone (S’85–M’88–SM’01) was born inTaipei, Taiwan, R.O.C. He received the B.S. degreein computer science and the M.S. degree in computerengineering from National Chiao-Tung University,Hsinchu, Taiwan, in 1979 and 1981, respectively,and the Ph.D. degree in computer engineering andscience from Case Western Reserve University,Cleveland, OH in 1987.

In 1987, he joined the Department of ComputerScience, New Mexico Institute of Mining and Tech-nology, Socorro, where he became an Associate Pro-

fessor in 1992. From 1993 to 2000, he was with the Department of Computer En-gineering and Information Science, National Chung-Cheng University, Chiayi,Taiwan. He was a Visiting Research Fellow with the Department of ComputerScience and Engineering, Chinese University of Hong Kong, in summer 1997.Since 2001, he has been with the Department of Electrical and Computer Engi-neering and Computer Science, University of Cincinnati, Cincinnati, OH. Hewas a Visiting Scholar with the Institute of Information Science, AcademiaSinica, Taiwan, in summer 2002. His research interests include VLSI designfor testability, built-in self-testing, memory testing, high-performance circuittesting, MEMS testing and repairing, and low-power circuit design. He has pub-lished more than 100 papers and has received one U.S. patent. He has served asa reviewer in his research areas in various technical journals and conferences.He has served on the Program Committee of VLSI Design/CAD Symposium(1993–1997, in Taiwan), was the General Chair of 1998 VLSI Design/CADSymposium, served on the Program Committee of 1995, 1996, 2000 Asian TestConference, 1995–1998 Asia and South Pacific Design Automation Conference,1998 International Conference on Chip Technology, 2000 International Sympo-sium on Defect and Fault Tolerance in VLSI Systems, and 2002 and 2003 GreatLake Symposium on VLSI.

Dr. Jone is a member of the IEEE Computer Society Test Technology Tech-nical Committee. He is a corecipient of the IEEE 2003 Donald G. Fink PrizePaper Award for a paper published in the December 2001 issue of the IEEETRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT. He is listed in Mar-quis Who’s Who in the World (1998, 2001). He received the Best Thesis Awardfrom the Chinese Institute of Electrical Engineering in 1981.

Mehmet Sahinoglu (S’78–M’81–SM’93) receivedthe B.S. degree from METU, Ankara, Turkey,and the M.S. degree from UMIST, U.K., both inelectrical and computer engineering. He received thePh.D. degree from Texas A&M University, CollegeStation, in electrical engineering and statistics.

He is the Eminent Scholar for the Endowed Chairof the Alabama Commission of Higher Education. Hehas been Chairman of the Computer and InformationScience Department at TSUM since 1999. Following20 years with METU, he served as the first Dean,

and founding Department Chair, in the College of Arts and Sciences, DEU,Izmir, Turkey (1992–1997). He was a Chief Reliability Consultant to the TurkishElectricity Authority from 1982 to 1997. He became an Emeritus Professor ofMETU and DEU in 2000. He has taught at Purdue University, West Lafayette,IN and Case Western Reserve University, Cleveland, OH, as a Fulbright andNATO scholar, respectively. He is accredited for the “Compound Poisson Soft-ware Reliability Model” to account for the multiple (clumped) failures in pre-dicting the total number of failures at the end of a mission time and the “MESAT:Compound Poisson Stopping Rule Algorithm” in cost-effective digital softwaretesting. He is jointly responsible (with D. Libby) for the original derivation of theG3B (Generalized Three-Parameter Beta) pdf in 1981, also known as Sahinogluand Libby pdf in 1999.

Dr. Sahinoglu is a Fellow of the Society for Design and Process Science, amember of ACM, AFCEA, and ASA, and an elected member of ISI.

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