24.07.2006Cédric Potterat - LPHE Monday Meeting1 PVSS for VELO and TELL1 at EPFL.

24.07.2006 Cédric Potterat - LPHE Monday Meeting

1

PVSS for VELO and TELL1 at EPFL


2

outlines

Introduction to PVSS Introduction to SMI++ and FSM (ECS control) VELO – Hybrid’s Low Voltage TELL1

DIM, fwCcpc, fwHw Present Developments

Outlooks


3

PVSS – CERN

Historically at CERN the control of equipment not used directly for data acquisition has been called "slow control"

In many applications it has become possible to use commercial off-the-shelf (COTS) solutions, with the advantage that the physics community does not need to develop or maintain them.

PVSS (Prozeßvisualisierungs- und Steuerungssystem), from the Austrian company ETM, was selected after a formal tender process in 1999 for use in the slow control systems of the four LHC experiments.

(eng: Process visualization and control system)

CERN provides: A global PVSS Framework

LHCb provides: Specific PVSS components

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4

PVSS Features – Structure

Open Architecture We can write our

own managers It can be

interfaced to anything (FSM, DIM)


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PVSS Features – Distributivity Highly Distributed

130 Systems (PCs) tested No major problem found


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PVSS Features - Datapoint Concept

DP type DP Standard Interface

All data of all sub-systems defined as

Configs


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Building User Interfaces

Static Part Drag & Drop Dynamic part Control Scripts ("C" like)

few useful calls for accessing DPs: dpGet (string dpName, <data_type> value) dpSet (string dpName, <data_type> value) dpConnect (string call-back, string dpName)

few useful calls for accessing Widgets: getValue (string widgetName, string widgetProperty, <widget

dependent data>) setValue (string widgetName, string widgetProperty, <widget

dependent data>)


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Central Hierarchy - ECS

...

To Devices (HW or SW)

Com

mands

Sta

tus

&

Ala

rms

ECS

DCS DAQ

DetDcs1

DetDcsN

SubSys1

SubSys2

Dev1

Dev2

Dev3

DetDaq1

SubSysN

DevN

LHCT.S.

...GAS

DSS

Ab

stra

ct levels


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Central Hierarchy - ECS

VELOADCS

INF DCS HV DAI DAQ HLT LHC

VELOAHV

VELOADAI

VELOADAQ

VELOALV

VELOATEMP

VELOAFEE

VELOATELL1

ECS

VELOCDCS

VELOCHV

VELOCDAI

VELOCDAQ

VELOCLV

VELOCTEMP

VELOCFEE

VELOCTELL1

VELOA VELOC

VELO

TFCL0


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FSM – SMI++

PVSS II does not have tools specifically for: Abstract behavior modeling

Finite State Machines (FSM) Automation & Error Recovery

Expert System

But… FSM (SMI++) does

State Management Interface (SMI++ which was developed for the DELPHI experiment) is used to control the FSM


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FSM – SMI++ Device Level: Proxies

C, C++, PVSS ctrl scripts drive the hardware:

deduce State handle Commands

Abstract Levels: Domains Internal objects Dedicated language Implement the logical model

User Interfaces For User Interaction


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FSM – SMI++ SMI++ - The Language

SML – State Management Language Finite State Logic

Objects are described as FSMstheir main attribute is a STATE

Parallelism Actions can be sent in parallel to several objects.

Tests on the state of objects can block if the objects are still “transiting”

Asynchronous Actions can be triggered by logical conditions on the state of

other objects


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FSM – PVSS basic Panel

ECS

DCS

DAQ

LHC

...... ...


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LV – VELO Project

Aim: Control the Low Voltage Power Supplies for the Hybrids Each Hybrid gets 3 LV Channels (-5.5V, 5.5V and 6V)

LV Devices – CAEN: Crate: SY2527 with a

BranchController (A1676A)

esayCarte: ESAY3000 with five A3009 Boards (12 channels) plugged in


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LV – VELO Project

Main Panel: Control the state,

the voltage of all the hybrids

Hybrid Panel: Control the state,

the voltage of its three channels

Channel Panel: Control the state,

the voltage

FSM

Hie

rarc

hy

Velo_C

Velo_A

Hyb 1 Hyb 2 Hyb N

Channel 1 Channel 2 Channel 3


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LV – FSM

Channel

FSM State: very basic

ERROR

OFF

RAMPING_UP

RAMPING_DOWN

READY

Switch_OFF

Switch_ON

Recover

An error


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LV – VELO Project

This PVSS project: developed with a simulator successfully tested with real hardware waiting for new information about the power

supplies that will be used


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TELL1 – PVSS Project We are attending to a crucial point in Switzerland History and Symbol


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TELL1 – PVSS – Outlines

We focus on the description (DPT, Panels) of a VeLo Tell1. (VeLo TELL1 is now completely described (registers, settings, addresses))

The access to the configuration database and recipe definition interface is finished

We put hands on the FSM (Rules, Panels)


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TELL1 – PVSS Project

Optical Receiver

Optical Receiver

PP-FPGAs

SyncLink-FPGA GBE

ECS Interface

Power

TTC IF


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TELL1 – PVSS Tools

DIM fwDim (C. Gaspar) http://dim.web.cern.ch/dim/

ccserv (S. Koestner) fwCcpc (S. Koestner - R. Fernandes) http://lhcb-online.web.cern.ch/lhcb-online/ecs/PVSS_CCPC/default.html

fwHw (R. Fernandes) http://lhcb-online.web.cern.ch/lhcb-online/ecs/FWHW/default.html


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DIM Distributed Information Management System

Publish/Subscribe mechanism Servers publish Services. Clients subscribe to Services:

On change or at regular intervals

Clients can send commands to Servers

Services A set of data

any type or size Identified by a name

A Name Server Keeps a list of available Services


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DIM Some Characteristics

Transparency DIM clients do not know where their interlocutors are. DIM components can move from one machine to another, all

connections are transparently re-established. Available on mixed environments:

UNIX (HP-UX, Sun-OS, Sun-Solaris, IBM-AIX, DEC-OSF, Linux), Windows, VMS, Real-time OSs (OS9, LynxOS, VxWorks)

API available in “C”, C++ and Java

Easy to Use One “call” and a process can become a server or a client. Monitoring and Visualization Tools Available. Documentation and examples at: http://www.cern.ch/dim


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PVSSDIM FwDIM component:

Server is a DIM Server Client is a PVSS Manager (PVSS00dim) Correspondence: PVSS DPs DIM Services

Can be setup graphically via fwDIM panel Or via a script library

When setup When Server updates Service data goes into DP Writing to DP will send a DIM Command

Documentation at: http://www.cern.ch/lhcb-online/ecs/fw/FwDim.html


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- parallel bus (8/16/32 bits) - I2C bus (4 distinct lines) - JTAG (3 chains)

Server runs on embedded PC (i486 compatible,133 MHz).Access to 3 bus-types via Plx/PCI bridge to gluecard:

Server is built on various software layers with the aim to hide as much as possible hardware complexity.(e.g. no need for users to read the docs of Tell1 components)

- Ccpc server:

A generic DIM server (ccserv)running in a credit-card PC, which allows access to all features of the CCPC/glue card including access to any chips over I2C, JTAG and parallel bus.

CCPC – PVSS Interface: the server (S.Koestner)


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CCPC – PVSS Interface: the Client fwCcpc provides:

Dim client (PVSS00dim)

control panels which can access every CCPC connected to the same Name Server (DIM_DNS_NODE)

Functions for reading, writing the registers of each type (I2C, LBUS,…)


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fwHw(R. Ferrandes)

All the TELL1 components are described as a type

And TELL1 is build up with all these components


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fwHwTELL1address

TELL1 components

structure

Registers

Register’s settings

To subscribe all the registers of the selected component to the server


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fwHw Scripts can be executed

All the TELL1 board is now described in PVSS as a DPT, and complete TELL1’s can be created as DP (correct name, addresses…) according to the “ECS Interface Library User Guide” (H. Gong, A. Gong, H. Lei and G. Haefeli)

(S. Koestner & C. Potterat)


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TELL1 – Setup

~ 500 (commands)

~ 1000 (writings/readings)

Client

>% dns &

Name Server(DIM_DNS_NODE = lphe1pc60)

lph

e1

tell7

TCP/IP

lphe1pc7(windows)

lph

e1

pc6

0 (

linu

x)

Server (ccserv)


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TELL1 – PVSS Goals:

Create FSM to control all the TELL1’s (Rules, Panels) (S.Koestner)

Create Panels which can replace the “console_tell1 ”, which will be called from the FSM panels (C.Potterat)


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FSM - State Diagram DAQ Domains:

RUNNING

ERROR UNKNOWN

READY

NOT_READY

Start

Configure

Stop

Reset

Recover

The possible states of the Tell1: From NOT_READY to READY the configuration of the Tell1 is done a compilation of applying recipes, pulling trigger lines and hardcoded sequences on the server side, which is the main job. The transition from Ready to Running is less massive (e.g. enabling triggers). UNKNOWN appears if ECS control is lost (e.g. server crashes)


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TELL1 – FSM

1st and basic FSM Panel to be used for the 1st test (in development)


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The Actual Rates

console_tell1


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The Event Monitor Counters

console_tell1


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The Pedestals

console_tell1


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console_tell1

The Linear Common Mode Suppression's (LCMS) Average and Slope


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The last 128 MEP in the MEP buffer, and all the information attached to.

console_tell1


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Global information about the TELL1, the server (ccserv) and PVSS components

console_tell1


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Outlook

Continue to create panels to control or monitor the TELL1’s registers PP and SyncLink FPGA (C.Potterat) GBE, TTCRx and FEM (S.Koestner)

Update the DP according to the latest ECS doc (C.Potterat)

Provide a fwTELL1 component including the FSM, the ccpc client and all the current panels

http://lhcb-online.web.cern.ch/lhcb-online/ecs/PVSS_TELL1/default.html (all the current versions and tutorials about fwCcpc, fwHw and TELL1’s FSM are

available on this web page)


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Back up


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CCPC Client : how it works


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PVSS Client (LBUS):

Choose ccpc from the list of running servers

Choose type (width) of local bus 32,16,8 bits

Determines number of words (e.g. 4 bytes for 32 bit bus) to be read or written.‘Data in’ (to be written) must have the exact size.

Masked write operation can be defined (e.g. reset registers on fpga). leave empty if not required

Indicates success of operation


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PVSS Client (GBE):

Gigabit Ethernet card accessed over a 16 bit bus. MAC registers however 32 bits.

Interface to be used as if it were a 32 bit bus.(1 word = 4 bytes)

The addresses to be given in the address field correspond to the addresses given in the Intel MAC data sheet

(same functionalities as LBUS)


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PVSS Client (I2C):

Some hardware can just be written in pages (e.g. EEPROMs on Tell1 with a pagesize of 16 bytes) This will be respected on the server side. Leave empty if no pagesize is required.

Combined:Subaddress and data is written in one go (usual).Separated:Subaddress is written first to pointer register. (it is the one you have to provide in the address field)Shift register:One byte has to be specified. This is shifted then by the server. (periodic pattern)


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PVSS Client (JTAG):

Number of bits to be shifted

Indicates the state of the state machine.

Data is shifted with the least significant bits first.Missing MSBs are replaced by zeros. Data must be a multiple of 2 to represent byte stream.

Select JTAG chain


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PVSS Client (GPIO): Interface to the 9 GPIO lines should be used just by experts only!(click and try could harm hardware)

Declaring and enabling GPIO lines

Apply value to GPIO lines (high, low)

Get current status of GPIO lines


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PVSS Client (Command):

Emulates a shell on the Ccpc:

Commandline tools of the ccpc can be launchedto crosscheck the results obtained from the server.

Everlasting commands like‘ping’ are timed out after 10seconds.

Does not follow change of directories.


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PVSS Client (Advanced): CONTROL scripts using the

PVSS or framework librariescan be edited and executed directly.


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PVSS Client (Advanced): Downloads firmware to

EPC16 (pof and jam is provided) Actions for jam can be propagated.

Loads FPGAs directly from EPC16

Content of the registers and memory blocks is written from the .cfg file to the FPGAs

PS:Jumper can be set such that FPGAs can be programmed directly without EPC16!

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24.07.2006Cédric Potterat - LPHE Monday Meeting1 PVSS for VELO and TELL1 at EPFL.

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