MICROPROCESSOR

SERIAL I NPUT/OUTPUT AS50

s~net~es SERIAL INPUT/OUTPUT

INTRODUCTION

The Sense/Flag capability of the Signetics 2650 micro-processor can be used for serial I/O interfaces. The Sense input pin is directly connected to a bit in the micro-processor's Program Status Word. A high level on the Sense pin appears as a binary one while a low level appears as a binary zero. The Sense bit in the PSW can be stored or tested by the program. The Flag bit in the PSW is a simple latch that drives the Flag output pin. A program can set the Flag bit to a binary one, which causes a high level, one TTL load on the flag output pin. Setting the Flag bit to binary zero causes a low level on the Flag output pin.

APPLICATIONS

The most common use for the Sense/Flag capability would be in interfacing to a keyboard based terminal where the data is received or transmitted as bit serial. All bit manipu-lation and timings such as 8-bit serial-to-parallel conversion

can be done by software running on the 2650. The software

works by storing or setting the two bits in the Program

Status Word which reflect or control the levels at the pins of the chip. External hardware is required simply to interface with line levels. No clock synchronization or address decoding hardware is necessary, since the Sense and Flag pins are independent of the normal I/O bus structure.

Two examples of device interfaces and software are given below; fora 1200 baud RS232-type CRT terminal and for

a 110 baud Teletype. Figure 1 shows the RS232 interface. Half of the Signetics 8T15 dual line driver is used to trans-

mit to the terminal from the Flag pin, while half of a

FIGURE 1 RS-232 INTERFACE

FgOM I/O DEVICE DRIVER

2650 MICROPROCESSOR

APPLICATION MEMO

AS50

Signetics 8T16 dual line receiver is used to receive from the device into the Sense pin. The interface to a Teletype model 33 is shown in Figure I I. A TTL open collector gate is used to provide the 20 milli-amp loop to the TTY

FLAG

sErvsE

FIGURE II TTY MODEL 33 INTERFACE FULL DUPLEX

receiver. For receiving from the TTY a CMOS gate is used to provide the necessary noise immunity.

SOFTWARE

All definitions of baud rate, character formats, and line characteristicsare done in the software. For these examples, communication is asynchronous bit-serial over a full duplex

line. Figure I II shows the format of a 8-bit character (seven

bits plus parity) headed by a start bit and followed by stop bits. The line levels are:

low =start bit or binary zero high =stop bit or binary one

SrfaRT BIT

r —► sroc airs

r r r r r r r r i

e airs oa onra

FIGURE III

LINE

PIP pSSE MHLEN

ADDN LAbL

vER57On 2 LEVEL 1

BI B2 B3 B4 FRRDR SOURCE

R AGG 1

1 2 OOUI P

EOU Z 4 0000 Z

L CUM E t61U OHr02' LDGICAL COMPARE 6 7

0001 OGtlO

CAk t0U SENS EUU

Hr01' M•e0r

C AkRY SENSE

v oozo FLAG t0U !1 EUU

H•40r H•20r

FL 4G

10 11

0020 0004

IDL EOU OYF t0U

H'20r k•04'

~N7EkRU1GITNCARRY OVEFF LUM

12 0001

tUU N1

0

)o 0002 k2 E 401U tuU 3

16 17

000] 0000

UN EUU EU tUU

3 0

Itl 0002 LT EUU 2

20 OOOB YC E EUU HIOBr 21 22

0010 RS EUU OHG

H'lOr N'SOOr

23 24

0500 0502

0500 76 40 75 OB

CH10 PPSU CPSL

FLAG MC

INPUT WITH A BIT BY BIT ECHO

25 26

0504 OS06

O$ 00 06 OB

LUDI.RI LODI .k

0 P

27 28

OSOB 0509

OSOB 12 lA 7D

TEST SPSU BCTR.LT TEST

LOOP TESTS fOk THE START BIT

29 3U

OSOb 050E

f O$ 74 40

29 BSTA.UN CPSU

ULY FL 4G

HALF A DECAY TO MIDDLE OF B1T

31 32

0510 0513

05]0 3F OS 12

2U HIT HSTA.UN $pP$p

DLAY DELAY• THEN kEAO THE NEAT BIT

34 0516 51 80 -

NNk~~RO H'BO'

3S 36

0517 OS1N

61 C1

IONZ SiNZ

Rl R1

37 3B

OS19 OSlB

lA 04 74 40

HCTR.L1 CPSU

ZERO FLAG

ECHO THE BI7

40 OS 1FU OS1F 76 40 2EkD PPSU'UN FLAG 41 42

0521 0523

0521 FA 60 3F OS 2U

NEAT HUNR.R2 BSTA.UN

H17 DLAY

43 44

OS26 052N

45 7f 17

ANDI.RI REIC.UN

M'7fr

4S 46 TIMING DELAY FOH ]200 BAUD RS232 TENMIN4L 47 4B

0529 0528

OS29 04 3A lb G2

ULY LODI .NO BCTkk.UN

Mr3Ar OLI

49 $U

0520 052f

0520 052E

04 59 iB 7E

DLAY LOUI .RU UL1 BURk.NO

Mr59r 3

51 52

0531 17 RETC UN • TIMING U~LAY FON 110 BAUD TELETYPE

PIP ASSE MBLEH VF NSION 2 LEVEL 1

LINE AUUk L4HL H1 B2 H3 B4 ERNDR SDUNCE

Sw 0533 0532

fe 7E SS 0535 FB 7E

57 0539 0537

04 ES Stl OS3B FB 7E

053U 17 60

T OT4L ASSEMHL Ek ERRDkS = 0

T ULA EORZ B URk.RU B DRR.RO

7 DLY BUNR.RU LUDI.RU B URR.RU

E NUC.UN

$a S

H'E5r 8

FIGURE IV

The internal logic of the program shown in Figure IV (the program listing) is to sense each incoming bit of the character and to output the bit in turn for the full duplex line. The Sense input is tested in the loop at'TEST' for the transition to zero indicating the start bit. The program then delays one half of a bit time to the center of the start bit. At this point the echoing of the character starts by clearing the Flag bit which outputs the start bit transition. At'BIT' the program then delays one full bit time to the center of the data bit. The Sense line is tested and that bit value is rotated into register one. The bit value is then used to set or clear the Flag bit for the echo. At 'NEXT' is the test

START BIT SENSE BIT

RAGE 2

that controls the loop to get only eight bits. Figure V is a picture of the levels and timings when echoing a 'U'.

The bit timing is done by a subroutine which simply counts cycles for the appropriate baud rate. The example program shows both a 1200 baud delay at 'DLAY' and a 110 baud delay at'TLAY'. The conversion from instruction cycles to milliseconds is based on a 1MHz clock rate. Clock stability is only moderately important since each character involves only nine sample times and each start bit redefines the base line for all timings.

DATA BITS

" i

T ~ T

DATA BITS

FIGURE V

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