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2D/3D Integration Challenges: Dynamic Reconfiguration and Design for Reuse.

Date post: 13-Dec-2015
Author: dennis-clark
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2D/3D Integration Challenges: Dynamic Reconfiguration and Design for Reuse
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2D/3D Integration Challenges: Dynamic Reconfiguration and Design for Reuse Slide 2 2 OUTLINE 2D/3D INTEGRATION TECHNOLOGY: DESIGN TRENDS AND CHALLENGES DESIGN PRODUCTIVITY GAP SYSTEM LEVEL REQUIREMENTS 2D/3D CIRCUIT DESIGN FLOW DYNAMIC RECONFIGURATION DESIGN FOR REUSE Slide 3 3 2D INTEGRATION TECHNOLOGY DRIVING FORCE: MOORES LAW Slide 4 4 3D INTEGRATION TECHNOLOGY Slide 5 5 DESIGN CHALLENGES Cost of design is the greatest threat to continuation of the semiconductor roadmap (ITRS 2007) Manufacturing: NRE costs: millions of dollars (mask set + probe card) cycle times: weeks, low uncertainty Design and verification: NRE costs: tens of millions of dollars not including frequent re-spins cycle times: months or years, high uncertainty Slide 6 6 DESIGN PRODUCTIVITY GAP capability of technology doubling every 36 months demand for software doubling every 10 months productivity for hardware-dependent software doubling every 5 years ITRS Roadmap Slide 7 7 SYSTEM-LEVEL REQUIREMENT TRENDS Year200920102011201220132014201520162017 Design reuse (% of logic) 38%40%41%42%44%46%48%49%51% Reconfigurability (% of functionality) 30%35%38%40%42%45%48%50%53% Verification engineer productivity (millions of transistor/year) 13.517.623.130.339.852.369.691.8121.0 ITRS Roadmap Slide 8 8 DIGITAL SYSTEM DESIGN FLOW Slide 9 9 RECONFIGURATION ABILITY OF A CIRCUIT TO ADAPT ITS FUNCTIONALITY STATICALLY OR DYNAMICALLY MICROPROCESSOR: FULLY PROGRAMMABLE ASIC: APPLICATION-SPECIFIC FINE-GRAIN RECONFIGURATION BIT-LEVEL (FPGA/CPLD) COARSE-GRAIN RECONFIGURATION WORD LEVEL (ALU) APPLICATION CLASS-SPECIFIC RECONFIGURATION ASIP FLEXIBLE ARCHITECTURES Slide 10 10 ENIAC PRIORITIES: ADVANCED ARCHITECTURES With respect to new chip architectures in the context of Nanoelectronics, R&D is mainly driven by two basic challenges: enormous complexity huge None- Recurring-Engineering (NRE) costs of future nanoelectronic SoCs. Priorities until 2013 Modelling and optimisation of Network-on-Chip architectures Modelling and evaluation of Multi-Core-Architectures Reconfigurable systems Development and evaluation of innovative communication concepts Self-adapting architectures for application-specific requirements Slide 11 11 DESIGN FOR REUSE (1/2) MOST CIRCUIT DESIGNS ARE PREVIOUS REDESIGNS WITH: NEW FEATURES BUGS FIXED IMPROVED PERFORMANCE INTEGRATION INTO A SINGLE SoC AIM OF REUSE: USE OF DESIGN IN MULTIPLE SYSTEMS OF DIFFERENT SPECIFICATIONS WITH LITTLE/NO MODIFICATIONS Slide 12 12 DESIGN FOR REUSE (2/2) ADDITIONAL LOGIC FOR EASY INTEGRATION GENERIC INTERFACE MULTIPLE INTERFACE SUPPORT (COMMUNICATION PROTOCOLS) MULTIPLE VERSIONS WITH DIFFERENT SPECS AND PARAMETERS WORD LENGTH PARALLEL/SERIAL EXECUTION etc. MULTIPLE HDL DESCRIPTIONS VHDL VERILOG MULTIPLE IMPLEMENTATIONS ASIC (VARIOUS TECHNOLOGIES) FPGA (VARIOUS TECHNOLOGIES) VERIFICATION TO A HIGHER LEVEL OF CONFIDENCE DESIGN FOR REUSE REQUIRES 3x DESIGN FOR USE EFFORT Slide 13 13 EUROPEAN EDA ROADMAP PRIORITIES V7: IP Reuse Platform and Emerging NoC Environments Correct and robust design Well-defined and clear design flow with adequate documentation General functionality and easily configurable design to solve a general problem and fit different applications Portability to run with all major commercial simulation tools and multiple technologies Rigorous well-designed and documented verification and validation Well-defined synthesis scripts Slide 14 14 ARTEMIS TECHNOLOGY DOMAINS AND CHALLENGES Slide 15 15 ENIAC PRIORITIES: IP REUSE Priorities until 2013 Technology independent IP-transfer Standards to describe IPs as well as plug-intools for IP interfacing and IP packaging Concepts for automatic integration of IPs in on-chip networks Comprehensive processes for the integration of IP modules from different suppliers Heterogeneous multi-core architectures including software Priorities from 2013 to 2020 Black box and grey box verification of IPs at the system level Strategies for automatic verification of IP integration