3 LECTURE 4 - Introduction to Verilog -EC601-DSD-AD - Lecture 3

8/19/2019 3 LECTURE 4 - Introduction to Verilog -EC601-DSD-AD - Lecture 3

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Verilog-Introduction

Amit Degada Asst Prof, ECIT-NU [email protected] www.adsignals.wordpress.com

Lecture 3

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Presentation Outline

• Detailed Verilog Program structure

• Verilog Lexical Convention

• Verilog – Behavioral Modeling

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Verilog Program Structure

module ();

endmodule

Port Declaration

Data type Declaration

Circuit Functionality

Timing Specification

Begins with keyword module

and ends with endmodule

The is an

identifier that uniquely names

the module. All the rules of C

identifier are applicable. i.e. it

Must start with alphabets,

should not start with numb or

special character. It should not

End with special character

Begins with keywordmodule

and ends withendmodule

The is an

identifier that uniquely names

the module. All the rules of C

identifier are applicable. i.e. it

Must start with alphabets,

should not start with numb or

special character. It should not

End with special character

DSD

Three Ways to Specify the Module1.Behavioral2.Data-flow

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module ();

endmodule

Port Declaration




The is a list ofinput,

inout andoutput ports which

are used to connect to other

modules.

e.g. a,b,c

The is a list ofinput,

inout andoutput ports which

are used to connect to other

modules.

e.g. a,b,c

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module ();

endmodule

Port Declaration




In port declaration region, the

Ports specified inare

Specifically mention as input,

output and inout

e.g input a; output b;

input c;

In port declaration region, the

Ports specified inare

Specifically mention as input,

output and inout

e.g input a; output b;

input c;

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Port Declaration

module ();

endmodule

Port Declaration

DSD

Syntax:

[ port size] port name, port name,…;

inputoutput

inout

• Port size range from [msb:lsb]• Either little endianor big endian

• Max port sizeis 256

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Port Declaration

Examples:

Examples Notes

input a,b,sel;

3 scalar portsoutput [7:0] result; little endian convention

inout [0:15] data_bus; big endian convention

input [15:12] addr; msb:lsb may be any integer

parameter word = 32;

input [word-1:0] addr;

constant expressions may be

used

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module ();

endmodule

Port Declaration




Since the purpose of the purpose

of Verilog HDL is to model digital

hardware, the primary data types

are for modeling registers (reg) andnet. Typical logic values

are0,1, x/Xand z/Z

Since the purpose of the purpose

of Verilog HDL is to model digital

hardware, the primary data types

are for modeling registers (reg) andnet. Typical logic values

are0,1, x/Xand z/Z

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module ();

endmodule


DSD

Data types are classified as:1.register2.net

Syntax:

[size] #( delay ) name, name,…;

delay (optional) may only be specified on net data types

sizeis a range from[msb : lsb](most-significant-bit to least-significant-bit)• Themsb andlsb must be integers•Either little-endian convention (the lsb is the smallest bitnumber) or big-endian convention (the lsb is the largest bitnumber) may be used.

• The maximum vector size is at least 65,536 bits (216

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Rule to Remember

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General Rules For Choosing The Correct Data Type Class when a signal is driven by a module output, a

primitive output, or a continuous assignmentuse anettype

when a signal is assigned a value in a Verilogprocedure use avariable type


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net Vs. reg

2016 DSD 11

net•Net data types are used tomake connections betweenparts of a design•Nets reflect the value and

strength level of the drivers ofthe net or the capacitance ofthe net, and do not have a

value of their own.•Nets have a resolutionfunction, which resolves a final

value when there are multipledrivers on the net.

Variable• Variable data types areused astemporary storage ofprogramming data• Variablescan only be assigned a

value from within an initialprocedure, an always procedure, a task or a function.• Variables can only store logic

values;theycannot store logicstrength.

• Variables are un-initialized atthe start of simulation, and willcontain a logic X until a value isassigned.


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1. register data type

• Register retainslast value(not logic strength) assignedto it

• A variable data typemust be used when the signal ison the left-hand side of a procedural assignment

• In verilog2001, its referred as variable

Keyword Functionality

reg unsigned variable of any bit size

integer signed 32-bit variable

time unsigned 64-bit variable

realor realtimedouble-precision floating point

variable

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2. net data type

• Net data typesconnect structural components together.• Netstransfer both logic values and logic strengths.

• A net data type must be used when: – A signal is driven by the output of some device.

– A signal is also declared as an input port or inout port.

– A signal is on the left-hand side of a continuous assignment.

Keyword Functionality wire or tri Simple interconnecting wire

wor or trior Wired outputs OR together

wand or

triand Wired outputs AND together

tri0 Pulls down when tri-stated

tri1 Pulls up when tri-stated

supply0 Constant logic 0 (supply strength)

supply1 Constant logic 1 (supply strength)

trireg Stores last value when tri-stated (capacitance strength)

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Examples

Data Type Examples Notes

wire a, b, c; 3 scalar nets

tri1 [7:0] data_bus; 8-bit net, pulls-up when tri-stated

reg [1:8] result; an 8-bit unsigned variable

reg [7:0] RAM [0:1023];a memory array; 8-bits wide, with

1K of addresses (1D Array)

wire [7:0] Q [0:15][0:256];a 2-dimensional array of 8-bit

wires

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other data type

Other

TypesFunctionality

parameter

Run-time constant for storing integers, real

numbers, time, delays, or ASCII strings. Parametersmay be redefined for each instance of a module.

specparamSpecify block constant for storing integers, real

numbers, time, delays or ASCII strings

event

A momentary flag with no logic value or data

storage. Often used for synchronizing concurrent

activities within a module.

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Examples

Data Type Examples Notes

parameter [2:0] s1 = 3’b001,

s2 = 3’b010,

s3 = 3’b100;

three 3-bit constants

parameter integer period = 10; an integer constant

localparam signed offset = -5; an 8-bit unsigned variable

event data_ready, data_sent; two event data types

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module ();

endmodule

Port Declaration




Continuous assignmentsuse the

keyword assign whereas

procedural assignments have

the form =

where themust be

a register or memory.

Procedural assignment may only

appear in initial and alwaysconstructs.

Continuous assignmentsuse the

keyword assign whereas

procedural assignments have

the form

=

where themust be

a register or memory.

Procedural assignment may only

appear in initial and alwaysconstructs.

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module ();

endmodule

Port Declaration




This is beyond the scope of the

syllabus, will be explored if time

permits at later part of thesemester

This is beyond the scope of the

syllabus, will be explored if time

permits at later part of thesemester

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module ();

module_port_declarations data_type_declarations module_instances

primitive_instances procedural_blocks continuous_assignments task_definitions function_definitions specify_blocks

endmodule

DSD

We will see each of them in detail

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module (); module_instances primitive_instances procedural_blocksendmodule

DSD

Port list can be specified intwo way1.Implicit2.ExplicitUseful while using moduleinstances, primitive

instances

Implicit Explicit

module module_name

(port_name,

port_name, ... );

module_items

endmodule

module module_name (.port_name(signal_name ), .port_name

(signal_name ), ... );

module_items

endmodule

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Verilog reserved keywords

alwaysandassignattributebeginbuf buf0buf1casecasexcasezcmosdeassigndefaultdefparam

disableedgeelseendendattributeendcaseendfunction

endmoduleendprimitiveendspecifyendtableendtaskeventforforceforeverforkfunctionhighz0highz1if ifnone

initialinoutinputinteger

joinmediummodule

largemacromodulenandnegedgenmosnornot

notif0notif1oroutputparameterpmosposedgeprimitive

pull0pull1pulldownpulluprcmosrealrealtime

regreleaserepeatrnmosrpmosrtranrtranif0rtranif1scalaredsignedsmallspecifyspecparamstrengthstrong0

strong1supply0supply1tabletasktimetran

tranif0tranif1tritri0tri1triand

triortriregunsignedvectoredwaitwandweak0weak1

whilewireworxnorxor

Don’tuse anyKeywordas

identifier name

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Verilog Lexical Convention

DSD

1.White Space Keywords2.Comments3.Case Sensitivity

4.Identifiers(names)5.Logic Values6.Logic Strength7.Literal Integer numbers

8.Literal real numbers

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1. White Space

• blanks, tabs,

• newlines (carriage return),

• formfeeds• EOF (end-of-file).

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2. Comments

// begins a single line comment,terminated by a newline.

/* begins a multi-line comment,terminated by a */

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3. Case sensitivity

• Verilog is case sensitive.

• Lower case letters are unique fromupper case letters

• All keywords we write in small letters

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4. Identifiers (names)

• Must begin with alphabetic or underscorecharactersa-z, A-Z, _

• May contain the charactersa-z, A-Z,0-9, _ and$

Examples Notes

adder legal identifier name

XORuppercase identifier is unique

from xor keyword

\reset*an escaped identifier (must be

followed by a white space)

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Escaped Identifier

Verilog HDL allows any character to be used in an identifier byescaping the identifier. Escaped identifiers provide a means ofincluding any of the printable ASCII characters in anidentifier(the decimal values 33 through 126, or 21 through 7Ein hexadecimal).

– Escaped identifiers begin with the back slash ( \ )

– Entire identifier isescaped by the back slash.

– Escaped identifier isterminated by white space(Characters suchas commas, parentheses, and semicolons become part of theescaped identifier unless preceded by a white space)

– Terminate escaped identifiers with white space, otherwisecharacters that should follow the identifier are considered as partof it.

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Escaped Identifier

// There must be white space after the// string which uses escape character

module \1dff (q, // Q output

\q~ , // Q_out output – scaped !dentifierd, // " input

cl#$, // %&'% input

\reset) // *eset input – scaped identifier

+

input d, cl#$, \reset)

output q, \q~

endmodule28


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5. Logic Values

The Verilog HDL has 4 logic values.

Logic Value Description

0 zero, low, or false

1 one, high, or true

z or Zhigh impedance (tri-stated or

floating)

x or X unknown or uninitialized

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6. Logic Strengths

The Verilog HDL has 8 logic strengths: 4 driving, 3 capacitive, and high impedance (nostrength).

StrengthLeel

Strength !ameSpeci"ication

#e$%ord &ispla$

'nemonic

-uppl. "rie suppl.0 suppl.1 -u0 -u1

-trong "rie strong0 strong1 -t0 -t1

* ull "rie pull0 pull1 u0 u1

+ &arge %apacitie large &a0 &a1

2ea$ "rie wea$0 wea$1 2e0 2e1

- 3ed4 %apacitie medium 3e0 3e1

-mall %apacitie small -m0 -m1

5igh !mpedance high60 high61 5i70 5i71

30 The cap_strength is fortrireg nets only.


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7. Literal Integer Number

Syntax:

0

• size (optional) is the number of bits in thenumber. Unsized integers default to at least32-bits.

• 'base (optional) represents the radix. Thedefault base is decimal.

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Base Symbol Legal Values

binary b orB 0, 1, x, X, z, Z, ?, _

octal o orO 0-7, x, X, z, Z, ?, _

decimal d orD 0-9, _

hexadecimal h orH 0-9, a-f, A-F, x, X, z, Z, ?,

• The? is another way of representing theZ logic value.• An_ (underscore) isignored (used to enhance readability).

• Values are expanded fromright to left (lsb to msb).• Whensize isless than value, theupper bits are truncated.• Whensize islarger than value, and theleft-most bit of value is 0or1, zeros are left-extended to fill the size.

• Whensize islarger than value, and theleft-most bit of value is Zor X, the Z or X is left-extended to fill the size.

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Examples Size Base Binary Equivalent

10 unsized decimal 0...01010 (32-bits)

'o7 unsized octal 0...00111 (32-bits)

1'b1 1 bit binary 1

8'Hc5 8 bits hex 11000101

6'hF0

6 bits hex110000

(truncated)6'hF 6 bits hex 001111 (zero filled)

6'hZ 6 bits hex ZZZZZZ (Z filled)

Examples:

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8. Literal Real Number

Syntax:

. 3

• Real numbers are limited to the values 0-9and underscore.

• There must be a value on either side of the

decimal point.

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8. Literal Real Number

Examples:

Examples Notes

0.5 Value 0.5

must have value on both sides of

decimal point

3e4 3 times 104

(30000)5.8E-3 5.8 times 10-3 (0.0058)

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Verilog-Behavioral Modeling

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Behavioral Modeling

• In complex digital design, somedecision(e.g. trade-offs of various architectureand algorithms)need to be made earlier

• Verilog has thefeature to specify thedesign functionality(or may be calledbehavior) in algorithmic manner

• Behavioral constructs are similar to anyHLL like C, and Verilog has reach behavioral construct

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Learning Objective

• Significance of structured procedures: al%a$s andinitial

• Define blockingandnon-blocking procedural assignment

• Use of

– level-sensitive Timing control – Conditional statements likei" andelse

– Multiway branching, usingcase,case4 andcasez

– Looping statements, such as %hile,"or,repeat and

"oreer• Understand the delay basedtiming control mechanism(regular delays, intra-assignment delay, zero delay)

• Definesequential andparallel blocks

• Naming of blocksanddisabling of named blocks

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Structured Procedures

• Two basic structured procedure statements

al%a$s

initial

– All behavioral statements appear only inside these blocks

– Each always or initial block has a separate activityflow (multithreading, concurrency)

– Start from simulation time 0

– No nesting


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Structured Procedures:initial statement

• Starts at time 0

• Executesonly onceduring a simulation• Multipleinitial blocks, execute in parallel

– All start at time 0 – Each finishes independently

• Syntax:

initial 1egin

// behaioral statements

end


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Structured Procedures:initial statement (cont’d)

module stimulus

reg 8, ., a, b, m

initial

m9 1:b0

initial

begin

;< a91:b1

;=< b91:b0

end

initial

begin

;10 891:b0

;=< .91:b1

end

initial

;


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Initializing variables

• Ordinary style, usinginitial blockreg cloc$ //the cloc$ ariable is defined first

initial cloc$ 9 0 //the alue of cloc$ is set to 0

• Combined declaration and initializationreg cloc$ 9 0 //quaillent of aboe two statements

module adder (

output reg >?@0A sum 9 0, output reg co 9 0,

input >?@0A a, b,

input ci+

444

endmodule


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Structured Procedures:al%a$s statement

• Start at time 0

• Execute the statements in a loopingfashion (Digital Hardware engineerconsider as repeated activity in digitalcircuit)

• Example


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Example 7.5

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Procedural Assignments

• Assignments inside initial andal%a$s

• To update values of “register” datatypes

– The value remains unchanged untilanother procedural assignment updates it

–Compare to continuous assignment(Dataflow Modeling)

P d lA ig t


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Procedural Assignments(cont’d)

• Syntax 5

– can be

• reg,integer,real,time• A bit-select of the above (e.g.,addr>0A)

• A part-select of the above (e.g.,addr>B1@1CA)

• A concatenation of any of the above

– is the same as dataflow modeling

– What happens if the widths do not match?• LHS wider than RHS => RHS is zero-extended• RHS wider than LHS => RHS is truncated (Least significantpart is kept)

Bl kigP d l


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Blocking Procedural Assignments

• The two types of procedural assignments – Blocking assignments – Non-blocking assignments

• Blocking assignments –are executedin order (sequentially) – Example:reg 8, ., 6

reg >1=A 9 1:b1

;10 reg_b>1


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Non-Blocking Procedural Assignments

• Non-blocking assignments – Processing of the next statements isnot blocked for this one – Transactions created sequentially (in order), but executedafter all blocking assignments in the correspondingsimulation cycle

– Syntax: 1=A G9 ;1< 1:b1

reg_b>1


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Non-Blocking Assignments(cont’d)

• Application of non-blocking assignments – Used to model concurrent data transfers

– Example: Write behavioral statements to swap values of two variables

alwa.s H(posedge cloc$+

begin

reg1 G9 ;1 in1

reg= G9 H(negedge cloc$+ in= I inB

regB G9 ;1 reg1

end he old !alue o" re#1 i$ u$ed


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Race Condition

• When the final result of simulating two (or more)concurrent processes depends on their order ofexecution

• Example:

alwa.s H(posedge cloc$+ b 9 a


a 9 b

• Solution:

alwa.s H(posedge cloc$+ b G9 a


a G9 b


begin temp_b 9 b temp_a 9 a

b 9 temp_a

a 9 temp_bend


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Race Condition (cont’d)

• Recommendation

–Concurrent data transfers => racecondition

–Use non-blocking assignments forconcurrent data transfers

–Example: pipeline modelling

–Disadvantage:• Lower simulation performance

• Higher memory usage in the simulator

Bh i lM dli Stt t


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Behavioral Modeling Statements:Conditional Statements

• Just the same asifJelse in C• Syntax:

i" (GexpressionK) true_statement;

i" (GexpressionK) true_statement;

else false_statement;

i" (GexpressionK) true_statement1;else i" (GexpressionK) true_statement=;else i" (GexpressionK) true_statementB;else default_statement;

• True is1 or non-zero• False is0 or ambiguous (8 or6)• More than one statement: 1egin end


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Example 7-18

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Behavioral Modeling Statements:Multiway Branching

• Similar toswitchJcase statement in C

• Syntax:case (Ge8pressionK)

alternatie1@ statement1; alternatie=@ statement=; 444

de"a2lt6 default_statement; // optionalendcase

• Notes: – Ge8pressionK is compared to thealternaties in theorder specified.

– Default statement is optional


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Multiway Branching (cont’d)

• Examples:

To be proided in the class

• Now, you write a 4-to-1 multiplexer.


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• Thecase statements compare and alternatives bit-for-bit

– 8 and6 values should match – See Example 7-20module demultiple8er1_to_L(out0, out1, out=, outB, in, s1, s0+ output out0, out1, out=, outB

input in, s1, s0 alwa.s H(s1 or s0 or in+ case( Ds1, s0E + =:b00@ begin 444 end =:b01@ begin 444 end =:b10@ begin 444 end =:b11@ begin 444 end =:b80, =:b81, =:b86, =:b88, =:b08, =:b18, =:b68@

begin 444 end =:b60, =:b61, =:b66, =:b06, =:b16@ begin 444 end default@ #displa.(MNnspecified control signalsO+ endcaseendmodule


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• case4 andcasez keywords – casez treats allz values as “don’t care”

– case4 treats all4 andz values as “don’t care”

• Example: 7-21

Bh i lM dligStt t


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Behavioral Modeling Statements:Loops

• Loops in Verilog

– %hile, "or, repeat, "oreer

• The %hile loop syntax: %hile (Ge8pressionK+

statement


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while Loop Example

To be proided in the class


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Loops (cont’d)

• The"or loop – Similar to C

– Syntax:

"or( init_e8pr cond_e8pr change_e8pr+ statement

– Example:roided in the class


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Loops (cont’d)

• Therepeat loop – Syntax:

repeat( number_of_iterations + statement

– Thenumber_of_iterations is evaluated only whenthe loop is first encountered

integer count

initial

begin

count 9 0 repeat(1=P+ begin

#displa.(%ount 9 Rd, count+

count 9 count F 1

end

end


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Loops (cont’d)

• The"oreer loop

–Syntax:

"oreer

statement

–Equivalent towhile(1+


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Timing Control

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Objectives of This Topic

• Internal operations of Event-Drivensimulators

• Behavioral Modeling (cont’d)

–Blocking vs. non-blocking assignments

–Race condition

– Timing control by delays, events, and

level –Other features


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Two Types of Simulators

• Oblivious Simulators

–Evaluate outputs repetitively atpredefined time intervals

• Event Driven Simulators

–Evaluate outputs only when an event

occurs on the inputs

InternalOperationsofEvent-


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Internal Operations of Event-Driven Simulators

• Event

• Transaction

• The simulation cycle


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Timing Controls in

ehavioral !odeling


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"ntroduction

• #o timing controls ⇒ #o advance insimulation time

• Three methods of timing control1.delay-based

2.event-based

3.level-sensitive


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1$ %elay&based Timing Controls

• Delay ≡ %uration between encounteringand executing a statement

• %elay symbol' #

• %elay specication syntax'

;< //&ela$ speci"ied 1$ n2m1er;(1@=@B+ //(min6t$p6ma4) dela$ model

%elay&based Timing Controls


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%elay based Timing Controls(cont)d*

• Types of delay&based timing controls – +egular delay control

– "ntra&assignment delay control

–,ero&delay control

• %elay control can be specied by anumber, identifer ormintypmax_expression.


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+egular %elay Control

• -ymbol' non&zero delay before a proceduralassignment

• %elay is specied at .eft of procedural assignment

• /xample' &10$

• The execution o procedural statement is delayedby the number specifed by the delay control

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Regular Delay Control

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Regular Delay Control

2016 DSD 74

"ntra&assignment %elay


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"ntra assignment %elayControl

• -ymbol' non&zero delay to the right ofthe assignment operator

• /xample' &11

• peration se2uence'

1$ Compute the +3- expression at currenttime$

4$ %efer the assignment of the abovecomputed value to the .3- by thespecied delay$



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, % l C t l


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,ero&%elay Control

• -ymbol' ;0

• %i5erent initial6always blocks in the samesimulation time – /xecution order non&deterministic

• 70 ensures execution after all otherstatements – /liminates race conditions (only in simulation*

• !ultiple zero&delay statements – #on&deterministic execution order

4 / t b d Ti i C t l


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4$ /vent&based Timing Control

• /vent – Change in the value of a register or net

– 8sed to trigger execution of a statement

or block (reactive behavior6reactivity*

• Types of /vent&based timing control –

+egular event control – #amed event control

– /vent + control

+ l / t C t l


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+egular /vent Control

• -ymbol' 7( )

• /vents to specify'

– posedge sig• /xecute the statement when the sig chnges withpositive transitions (0 to 19 x or z9 x to 19 z to 1*

– negedge sig• /xecute the statement when the sig chnges with

positive transitions (1 to 09 x or z9 x to 09 z to 0* – sig

• /xecute the statement when9 :ny change in sig value occurs

# d / t C t l


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#amed /vent Control

• ;ou can declare (name* an event9 and thentrigger and recognize it$

•

JKcalc_finished

• =erilog symbol for recognizing' 7()

H(calc_finished+

# d / t C t l


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#amed /vent Control

eent receied_data //&eclare an eent

al%a$s H ( posedge cloc$+ //chec9 at each pos edge

:egin

i" (last_pac$et+ //i" last_pac9et is then

JKreceied_data //triggers the eent named as

//receied_data

end

al%a$sH(receied_data+

1egin

/888&o Something888/

end

/ + l


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/vent + control

• 8sed when need to trigger a block uponoccurrence of any of a set of events$

• The list of the events' sensitivity list

•


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/vent + control

• Simpler syntax – al%a$s H( reset or cloc$ or d+

– al%a$s H( reset, cloc$, d+

– H) and H()+

Level-sensitive Timing


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gControl

• Level-sensitive vs. event-based – event&based' wait for triggering of an

event (change in signal value*

– level&sensitive' wait or a certaincondition (on values/levels o signals

•


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• Some more constructs on BehavioralModeling

–Parallel blocks

–Nested blocks

– disable keyword

• Verilog® Scheduling Semantics

Bl k S tilbl k


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Blocks, Sequential blocks

• Used to group multiple statements• Sequential blocks

–Keywords: 1egin end

–Statements areprocessed in order. – A statement isexecuted only after itspreceding one completes.• Exceptions: non-blocking assignments andintra-assignment delays

– A delay or event is relative to thesimulation time when the previousstatement completed execution

P lllBl k


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Parallel Blocks

• Parallel Blocks – Keywords:"or9, oin

– Statements in the blocks are executedconcurrently

– Timing controls specify the order of execution ofthe statements

– All delays are relative to the time the block wasentered

• The written order of statements is not important

• TheSoin is done when all the parallel statementsare finished

S til P lllBl k


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Sequential vs. Parallel Blocks

initial

1egin

45=1;

* $5=1;

z5?4,$@;

- %5?$,4@;end

initial

"or945=1;

* $5=1;

z5?4,$@;

- %5?$,4@;

oin

DSD 902016

ParallelBlocksandRace


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Parallel Blocks and Race

• Parallel execution⇒ Race conditions mayarise

initial

"or9

45=1;$5=1;

z5?4,$@;

%5?$,4@;

oin

• 6,w can take either=:b01, =:b10or=:b88, =:b88 or othercombinations depending on simulator

SpecialFeaturesofBlocks


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Special Features of Blocks

• Contents –Nested blocks

–Named blocks

–Disabling named blocks

NestedBlocks


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Nested Blocks

• Sequential and parallel blocks can be mixed

initial

1egin

45=1;

"or9

* $5=1;

z5?4,$@;

oin

- %5?$,4@;

end

Namedblocks


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Named blocks

• Syntax:begin@ Gthe_nameKfor$@ Gthe_nameK

end Soin

• Advantages: – Can have local variables (local variables are static)

– Are part of the design hierarchy.

– Their local variables can be accessed usinghierarchical names

– Can be disabled

DisablingNamedBlocks


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Disabling Named Blocks

• Keyword:disable

• Action:

–Similar tobrea$ in C/C++, but can

disableany named block not just theinner-most block.

Loops


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Loops

• A loop is synthesizable if it is static: Thenumber of iterations is fixed and independent ofthe data

• Example:

reg >=@0A i

reg >B@0A out

wire >B@0A a,b

alwa.s H (a or b+

begin

for (i90 iG9B i9iF1+

out>iA 9 a>iA U b>iA

end

endmodule

• Example Unrolled:

out>0A 9 a>0A U b>0A

out>1A 9 a>1A U b>1A

out>=A 9 a>=A U b>=A

out>BA 9 a>BA U b>BA

GenerateStatements


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Generate Statements

Generate Loop• Generate loops can be used to create multiple instances ofinstances within a for loop.

• The for loop in a generate statement is similar to the regular forloop except for the following conditions: – The loop index variable must be agenvar variable, a special integer

variable used in for loops. – The assignments in the loop control must assign to the samegenvar.

– The contents of the loopmust be within a named begin–end block.• Thegenvar variable is a special integer variable used in generateloops, which can be assigned only 0 or positive numbers. Agenvar can only be assigned a value as part of a generate loopstatement. A genvar variable can be defined outside of thegenerate block or within a generate block.If declared outside,the genvar variable can be used by any number of generate

blocks.

ConditionalGenerates


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Conditional Generates• Conditional generates can be created intwo ways:

– if –elsestatements – case statements

• Both of these statements can beused within the generate block.• Here is an example of using a generate statement to control the typeof adder used:

// ifJelsegenerate

if (adder_width G P+

ripple_carr. ; (adder_width+ u1 (a, b, sum+

else

carr._loo$_ahead ; (adder_width+ u1 (a, b, sum+

endgenerate

• Note: The expression inside the if statement must evaluate to a static value.

ConditionalGenerates


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Conditional Generates

• The following example uses thecase statementto determine which adder is used, based on theparameter WIDTH:// case

parameter 2!"T591

generate

case (2!"T5+

1@ adder1 81 (c0, sum, a, b, ci+

=@ adder= 81 (c0, sum, a, b, ci+

default@ adder ; 2!"T5 8B (c0, sum, a, b, ci+endcase

endgenerate


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Behavioral Modeling

-ome /xamples

4to1Multiplexer


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4-to-1 Multiplexer

4-bitCounter


100/120

4-bit Counter

Haveyoulearnedthistopic?


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Have you learned this topic?

• Sequential and Parallel Blocks• Special Features of Blocks

– Nested blocks

– Named blocks

– Disabling named blocks

ObjectivesofThisTopic


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• Use Tasks and Functions for betterstructured code

"ntroduction


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"ntroduction

• >rocedures6-ubroutines6?unctions in-@ programming languages

– The same functionality9 in di5erent

places• =erilog e2uivalence'

– Tasks and ?unctions

– 8sed in behavioral modeling – >art of design hierarchy ⇒ 3ierarchical

name

Functions


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Functions

• Keyword:"2nction, end"2nction

• Can be used if the procedure – does not have any timing control constructs

– returns exactly one single value – has at least one input argument

FunctionDeclarationSyntax


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Function Declaration Syntax

"2nction


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Function Invocation Syntax


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Function Semantics

– much like function in >ascal or C – :n internal implicit reg is declared

inside the function with the same name

– The return value is specied by settingthat implicit reg

– Grange_or_t.peK denes width andtype of the implicit reg

• Gt.peK can be integer or real

• default bit width is 1

Two Function Examples:>arity Aenerator and Controllable


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>arity Aenerator9 and Controllable-hifter

2016 DSD 111

Tasks


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Tasks

•


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Task %eclaration -yntax

tas9 ;

// optional

1egin // if more than one statement needed

end // if begin usedV

endtas9

Task "nvocation -yntax


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Task "nvocation -yntax

;

();

– input and inout arguments are passedinto the task

– output and inout arguments are

passed back to the invoking statementwhen task is completed

"6 declaration in modulest k


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vs$ tasks

– oth use keywords' input, output,inout

– "n modules9 represent ports• connect to external signals

– "n tasks9 represent arguments

• pass values to and from the task

Task /xamples


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as a p es

• Use of input and output arguments

• Use of module local variables

Automatic Tasks andF i


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Functions

• Used for re-entrant code – Task called from multiple locations

–Recursive function calls

• Keyword – automatic

• Examplefunction automatic integer factorial

tas$ automatic bitwise_8or

Automatic Function ExampleF t il


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Factorial


116/120

Tasks and Functions

%i5erences between

Tasks and ?unctions

%i5erences between


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%i5erences between$$$

• ?unctions – Can enable (call* just

another function (nottask*

– /xecute in 0 simulationtime

– #o timing controlstatements allowed

– :t least one input

– +eturn only a single value

• Tasks – Can enable other tasks

and functions

– !ay execute in non&

zero simulation time – !ay contain any timing

control statements

– !ay have arbitraryinput9 output9 or

inout – %o not return any

value

2016 DSD 120

Haveyoulearnedthistopic?


118/120

Have you learned this topic?

• 3ow to dene tasks and functions• @here to use each of them

– The same purpose as subroutines in -@ –

>rovide more readability9 easier codemanagement – :re part of design hierarchy – Tasks are more general than functions

• Can represent almost any common =erilogcode

– ?unctions can only model purelycombinational calculations

Structured Procedure


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Stuctued ocedue

122


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3 LECTURE 4 - Introduction to Verilog -EC601-DSD-AD - Lecture 3

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