General Description The MAX5885 is an advanced, 16-bit, 200Msps digital- to-analog converter (DAC) designed to meet the demanding performance requirements of signal synthe- sis applications found in wireless base stations and other communications applications. Operating from a single 3.3V supply, this DAC offers exceptional dyna- mic performance such as 77dBc spurious-free dynamic range (SFDR) at f OUT = 10MHz. The DAC supports update rates of 200Msps at a power dissipation of less than 200mW. The MAX5885 utilizes a current-steering architecture, which supports a full-scale output current range of 2mA to 20mA, and allows a differential output voltage swing between 0.1V P-P and 1V P-P . The MAX5885 features an integrated 1.2V bandgap reference and control amplifier to ensure high accuracy and low noise performance. Additionally, a separate reference input pin enables the user to apply an exter- nal reference source for optimum flexibility and to improve gain accuracy. The digital and clock inputs of the MAX5885 are designed for CMOS-compatible voltage levels. The MAX5885 is available in a 48-pin QFN package with an exposed paddle (EP) and is specified for the extended industrial temperature range (-40°C to +85°C). Refer to the MAX5883 and MAX5884 data sheets for pin-compatible 12- and 14-bit versions of the MAX5885. For LVDS high-speed versions, refer to the MAX5886/ MAX5887/MAX5888 data sheet. Applications Base Stations: Single/Multicarrier UMTS, CDMA, GSM Communications: LMDS, MMDS, Point-to-Point Microwave Digital Signal Synthesis Automated Test Equipment (ATE) Instrumentation Features ♦ 200Msps Output Update Rate ♦ Single 3.3V Supply Operation ♦ Excellent SFDR and IMD Performance SFDR = 77dBc at f OUT = 10MHz (to Nyquist) IMD = -88dBc at f OUT = 10MHz ACLR = 74dB at f OUT = 30.72MHz ♦ 2mA to 20mA Full-Scale Output Current ♦ CMOS-Compatible Digital and Clock Inputs ♦ On-Chip 1.2V Bandgap Reference ♦ Low Power Dissipation ♦ 48-Pin QFN-EP Package MAX5885 3.3V, 16-Bit, 200Msps High Dynamic Performance DAC with CMOS Inputs ________________________________________________________________ Maxim Integrated Products 1 Ordering Information 19-2786; Rev 1; 12/03 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. PART TEMP RANGE PIN-PACKAGE MAX5885EGM -40°C to +85°C 48 QFN-EP* B12 B13 B15 DGND N.C. N.C. N.C. N.C. N.C. DV DD SEL0 B14 XOR VCLK CLKGND CLKP CLKN CLKGND VCLK PD AV DD AGND B0 B1 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 AGND IOUTN IOUTP AV DD AGND AV DD AGND N.C. DACREF FSADJ REFIO B3 B4 B5 B6 DV DD DGND B7 B8 B9 B11 B10 B2 QFN MAX5885 AGND TOP VIEW 48 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 Pin Configuration *EP = Exposed paddle.
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General DescriptionThe MAX5885 is an advanced, 16-bit, 200Msps digital-to-analog converter (DAC) designed to meet thedemanding performance requirements of signal synthe-sis applications found in wireless base stations andother communications applications. Operating from asingle 3.3V supply, this DAC offers exceptional dyna-mic performance such as 77dBc spurious-free dynamicrange (SFDR) at fOUT = 10MHz. The DAC supportsupdate rates of 200Msps at a power dissipation of lessthan 200mW.
The MAX5885 utilizes a current-steering architecture,which supports a full-scale output current range of 2mAto 20mA, and allows a differential output voltage swingbetween 0.1VP-P and 1VP-P.
The MAX5885 features an integrated 1.2V bandgap reference and control amplifier to ensure high accuracyand low noise performance. Additionally, a separatereference input pin enables the user to apply an exter-nal reference source for optimum flexibility and toimprove gain accuracy.
The digital and clock inputs of the MAX5885 aredesigned for CMOS-compatible voltage levels. TheMAX5885 is available in a 48-pin QFN package with anexposed paddle (EP) and is specified for the extendedindustrial temperature range (-40°C to +85°C).
Refer to the MAX5883 and MAX5884 data sheets forpin-compatible 12- and 14-bit versions of the MAX5885.For LVDS high-speed versions, refer to the MAX5886/MAX5887/MAX5888 data sheet.
ELECTRICAL CHARACTERISTICS(AVDD = DVDD = VCLK = 3.3V, AGND = DGND = CLKGND = 0V, external reference, VREFIO = 1.25V, RL = 50Ω, IOUT = 20mA, fCLK = 200Msps, TA = TMIN to TMAX, unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by designand characterization. Typical values are at TA = +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functionaloperation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure toabsolute maximum rating conditions for extended periods may affect device reliability.
AVDD, DVDD, VCLK to AGND................................-0.3V to +3.9VAVDD, DVDD, VCLK to DGND ...............................-0.3V to +3.9VAVDD, DVDD, VCLK to CLKGND ...........................-0.3V to +3.9VAGND, CLKGND to DGND....................................-0.3V to +0.3VDACREF, REFIO, FSADJ to AGND.............-0.3V to AVDD + 0.3VIOUTP, IOUTN to AGND................................-1V to AVDD + 0.3VCLKP, CLKN to CLKGND...........................-0.3V to VCLK + 0.3VB0–B15, SEL0, PD, XOR to DGND.............-0.3V to DVDD + 0.3V
Thermal Resistance (θJA) ..............................................+37°C/W Operating Temperature Range ...........................-40°C to +85°CJunction Temperature ......................................................+150°CStorage Temperature Range .............................-60°C to +150°CLead Temperature (soldering, 10s) .................................+300°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
STATIC PERFORMANCE
Resolution 16 Bits
Integral Nonlinearity INL Measured differentially ±0.006 %FS
Note 1: Nominal full-scale current IOUT = 32 IREF. Note 2: This parameter does not include update-rate depending effects of sin(x)/x filtering inherent in the MAX5885.Note 3: Parameter measured single ended into a 50Ω termination resistor.Note 4: Parameter guaranteed by design.Note 5: Parameter defined as the change in midscale output caused by a ±5% variation in the nominal supply voltage.
ELECTRICAL CHARACTERISTICS (continued)(AVDD = DVDD = VCLK = 3.3V, AGND = DGND = CLKGND = 0V, external reference, VREFIO = 1.25V, RL = 50Ω, IOUT = 20mA, fCLK = 200Msps, TA = TMIN to TMAX, unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by designand characterization. Typical values are at TA = +25°C.)
XOR Input Pin.XOR = 1 inverts the digital input data.XOR = 0 leaves the digital input data unchanged.XOR has an internal pulldown resistor and may be left unconnected if not used.
4, 9 VCLKClock Supply Voltage. Accepts a supply voltage range of 3.135V to 3.465V. Bypass each pin with a0.1µF capacitor to the nearest CLKGND.
5, 8 CLKGND Clock Ground
6 CLKP Converter Clock Input. Positive input terminal for the converter clock.
7 CLKN Complementary Converter Clock Input. Negative input terminal for the converter clock.
10 PDPower-Down Input. PD pulled high enables the DAC’s power-down mode. PD pulled low allows fornormal operation of the DAC.
11, 21, 23 AVDDAnalog Supply Voltage. Accepts a supply voltage range of 3.135V to 3.465V. Bypass each pin with a0.1µF capacitor to the nearest AGND.
12, 17, 20,22, 24, EP
AGND Analog Ground. Exposed paddle (EP) must be connected to AGND.
13 REFIOReference I/O. Output of the internal 1.2V precision bandgap reference. Bypass with a 0.1µFcapacitor to AGND. Can be driven with an external reference source.
14 FSADJFull-Scale Adjust Input. This input sets the full-scale output current of the DAC. For 20mA full-scaleoutput current, connect a 2kΩ resistor between FSADJ and DACREF.
15 DACREFReturn Path for the Current Set Resistor. For 20mA full-scale output current, connect a 2kΩ resistorbetween FSADJ and DACREF.
16, 25, 26,27, 28, 29
N.C. No connection. Do not connect to these pins. Do not tie these pins together.
18 IOUTNComplementary DAC Output. Negative terminal for differential current output. The full-scale outputcurrent range can be set from 2mA to 20mA.
19 IOUTPDAC Output. Positive terminal for differential current output. The full-scale output current range canbe set from 2mA to 20mA.
30 SEL0Mode Select Input SEL0. This pin has an internal pulldown resistor; it can be left open to disable thesegment-shuffling function (see the Segment Shuffling section).
31, 43 DVDDDigital Supply Voltage. Accepts a supply voltage range of 3.135V to 3.465V. Bypass each pin with a0.1µF capacitor to the nearest DGND.
32, 42 DGND Digital Ground
33 B15 Data Bit 15 (MSB)
34 B14 Data Bit 14
35 B13 Data Bit 13
36 B12 Data Bit 12
37 B11 Data Bit 11
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The MAX5885 is a high-performance, 16-bit, current-steering DAC (Figure 1) capable of operating withclock speeds up to 200MHz. The converter consists ofseparate input and DAC registers, followed by a cur-rent-steering circuit. This circuit is capable of generat-ing differential full-scale currents in the range of 2mA to20mA. An internal current-switching network in combi-nation with external 50Ω termination resistors convertthe differential output currents into a differential outputvoltage with a peak-to-peak output voltage range of0.1V to 1V. An integrated 1.2V bandgap reference,control amplifier, and user-selectable external resistordetermine the data converter’s full-scale output range.
Reference Architecture and OperationThe MAX5885 supports operation with the on-chip 1.2Vbandgap reference or an external reference voltagesource. REFIO serves as the input for an external, low-impedance reference source, and as the output if theDAC is operating with the internal reference. For stableoperation with the internal reference, REFIO should bedecoupled to AGND with a 0.1µF capacitor. Due to itslimited output drive capability, REFIO must be bufferedwith an external amplifier, if heavier loading is required.
The MAX5885’s reference circuit (Figure 2) employs acontrol amplifier, designed to regulate the full-scalecurrent IOUT for the differential current outputs of theDAC. Configured as a voltage-to-current amplifier, theoutput current can be calculated as follows:
IOUT = 32 IREFIO - 1 LSB
IOUT = 32 IREFIO - (IOUT / 216)
where IREFIO is the reference output current (IREFIO =VREFIO/RSET) and IOUT is the full-scale output currentof the DAC. Located between FSADJ and DACREF,
RSET is the reference resistor, which determines theamplifier’s output current for the DAC. See Table 1 for amatrix of different IOUT and RSET selections.
Analog Outputs (IOUTP, IOUTN)The MAX5885 outputs two complementary currents(IOUTP, IOUTN) that can be operated in a single-ended or differential configuration. A load resistor canconvert these two output currents into complementarysingle-ended output voltages. The differential voltageexisting between IOUTP and IOUTN can also be con-verted to a single-ended voltage using a transformer ora differential amplifier configuration. If no transformer isused, the output should have a 50Ω termination to theanalog ground and a 50Ω resistor between the outputs.
Although not recommended because of additionalnoise pickup from the ground plane, for single-endedoperation IOUTP should be selected as the output, withIOUTN connected to AGND. Note that a single-endedoutput configuration has a higher 2nd-order harmonicdistortion at high output frequencies than a differentialoutput configuration.
Figure 3 displays a simplif ied diagram of theMAX5885’s internal output structure.
Clock Inputs (CLKP, CLKN)The MAX5885 features a flexible differential clock input(CLKP, CLKN) operating from separate supplies(VCLK, CLKGND) to achieve the best possible jitterperformance. The two clock inputs can be driven froma single-ended or a differential clock source. For sin-gle-ended operation, CLKP should be driven by a logicsource, while CLKN should be bypassed to AGND witha 0.1µF capacitor.
The CLKP and CLKN pins are internally biased to VCLK/2.This allows the user to AC-couple clock sources directlyto the device without external resistors to define the DClevel. The input resistance of CLKP and CLKN is >5kΩ.
See Figure 4 for a convenient and quick way to apply adifferential signal created from a single-ended source(e.g., HP 8662A signal generator) and a widebandtransformer. These inputs can also be driven from aCMOS-compatible clock source; however, it is recom-mended to use sinewave or AC-coupled ECL drive forbest performance.
Data Timing RelationshipFigure 5 shows the timing relationship between differ-ential, digital CMOS data, clock, and output signals.The MAX5885 features a 1.25ns hold, a 0.4ns setup,and a 1.8ns propagation delay time. There is a 3.5clock-cycle latency between CLKP/CLKN transitioninghigh/low and IOUTP/IOUTN.
CMOS-Compatible Digital Inputs (B0–B15)The MAX5885 features single-ended, CMOS-compatiblereceivers on the bus input interface. These CMOS inputs(B0–B15) allow for a voltage swing of 3.3V.
Segment Shuffling (SEL0)Segment shuffling can improve the SFDR of theMAX5885 at higher output frequencies and amplitudes.Note that an improvement in SFDR can only be achievedat the cost of a slight increase in the DAC’s noise floor.
Pin SEL0 controls the segment-shuffling function. If SEL0is pulled low, the segment-shuffling function of the DAC isdisabled. SEL0 can also be left open, because an internalpulldown resistor helps to deactivate the segment-shuf-fling feature. To activate the MAX5885 segment-shufflingfunction, SEL0 must be pulled high.
XOR Function (XOR)The MAX5885 is equipped with a single-ended, CMOS-compatible XOR input, which may be left open (XORprovides an internal pulldown resistor) or pulled downto DGND, if not used. Input data is XORed with the bitapplied to the XOR pin. Pulling XOR high inverts theinput data. Pulling XOR low leaves the input data nonin-verted. By applying a pseudorandom bit stream to XORand applying data while XOR is high, the bit transitionsin the digital input data can be decorrelated from theDAC output, allowing the user to troubleshoot possiblespurious or harmonic distortion degradation due to dig-ital feedthrough on the PC board.
Power-Down Operation (PD)The MAX5885 also features an active-high power-downmode, which allows the user to cut the DAC’s currentconsumption. A single pin (PD) is used to control thepower-down mode (PD = 1) or reactivate the DAC (PD= 0) after power-down. Enabling the power-down modeof this 16-bit CMOS DAC allows the overall power con-sumption to be reduced to less than 1mW. TheMAX5885 requires 10ms to wake up from power-downand enter a fully operational state.
Applications InformationDifferential Coupling Using a
Wideband RF TransformerThe differential voltage existing between IOUTP andIOUTN can also be converted to a single-ended volt-age using a transformer (Figure 6) or a differentialamplifier configuration. Using a differential transformer-coupled output, in which the output power is limited to0dBm, can optimize the dynamic performance.However, make sure to pay close attention to the trans-former core saturation characteristics when selecting atransformer for the MAX5885. Transformer core satura-tion can introduce strong 2nd-harmonic distortion,especially at low output frequencies and high signalamplitudes. It is also recommended to center tap thetransformer to ground. If no transformer is used, eachDAC output should be terminated to ground with a 50Ωresistor. Additionally, a 100Ω resistor should be placedbetween the outputs (Figure 7).
If a single-ended unipolar output is desirable, IOUTPshould be selected as the output, with IOUTN ground-ed. However, driving the MAX5885 single ended is notrecommended since additional noise is added (fromthe ground plane) in such configurations.
The distortion performance of the DAC depends on theload impedance. The MAX5885 is optimized for a 50Ωdouble termination. It can be used with a transformeroutput as shown in Figure 7 or just one 50Ω resistorfrom each output to ground and one 50Ω resistorbetween the outputs. This produces a full-scale outputpower of up to 0dBm depending on the output currentsetting. Higher termination impedance can be used atthe cost of degraded distortion performance andincreased output noise voltage.
Adjacent Channel Leakage Power Ratio(ACLR) Testing for CDMA- and W-CDMA-Based Base Station
Transceiver Systems (BTS)The transmitter sections of BTS applications servingCDMA and W-CDMA architectures must generate carri-ers with minimal coupling of carrier energy into the adja-cent channels. Similar to the GSM/EDGE model (see theMultitone Testing for GSM/EDGE Applications section), atransmit mask (Tx mask) exists for this application. Thespread-spectrum modulation function applied to the carri-er frequency generates a spectral response, which is uni-form over a given bandwidth (up to 4MHz) for a W-CDMA-modulated carrier.
B0 TO B15
CLKN
CLKP
IOUT
N
DIGITAL DATA IS LATCHED ONTHE RISING EDGE OF CLKP
OUTPUT DATA IS UPDATED ONTHE FALLING EDGE OF CLKP
N + 1 N + 2
N - 5 N - 3 N - 1N - 2N - 4
tSETUP tHOLD
tPD
tCH tCL
N - 1
Figure 5. Detailed Timing Relationship
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A dominant specification is ACLR, a parameter whichreflects the ratio of the power in the desired carrierband to the power in an adjacent carrier band. Thespecification covers the first two adjacent bands, and ismeasured on both sides of the desired carrier.
According to the transmit mask for CDMA and W-CDMAarchitectures, the power ratio of the integrated carrierchannel energy to the integrated adjacent channelenergy must be >45dB for the first adjacent carrier slot(ACLR 1) and >50dB for the second adjacent carrierslot (ACLR 2). This specification applies to the output ofthe entire transmitter signal chain. The requirement foronly the DAC block of the transmitter must be tighter,with a typical margin of >15dB, requiring the DAC’sACLR 1 to be better than 60dB.
Adjacent channel leakage is caused by a singlespread-spectrum carrier, which generates intermodula-tion (IM) products between the frequency componentslocated within the carrier band. The energy at one endof the carrier band generates IM products with theenergy from the opposite end of the carrier band. Forsingle-carrier W-CDMA modulation, these IMD productsare spread 3.84MHz over the adjacent sideband. Fourcontiguous W-CDMA carriers spread their IM productsover a bandwidth of 20MHz on either side of the 20MHztotal carrier bandwidth. In this four-carrier scenario,only the energy in the first adjacent 3.84MHz sidebandis considered for ACLR 1. To measure ACLR, drive theconverter with a W-CDMA pattern. Make sure that thesignal is backed off by the peak-to-average ratio, suchthat the DAC is not clipping the signal. ACLR can thenbe measured with the ACLR measurement function builtinto your spectrum analyzer.
Figure 8 shows the ACLR performance for a single W-CDMA carrier (fCLK = 184.32MHz, fOUT = 30.72MHz)applied to the MAX5885 (including measurement systemlimitations*).
Figure 9 illustrates the ACLR test results for theMAX5885 with a four-carrier W-CDMA signal at an out-put frequency of 30.72MHz and a sampling frequencyof 184.32MHz. Considerable care must be taken toensure accurate measurement of this parameter.
MAX5885
T2, 1:1
T1, 1:1
VOUT, SINGLE ENDED
WIDEBAND RF TRANSFORMER T2PERFORMS THE DIFFERENTIAL TO
SINGLE-ENDED CONVERSION.
50Ω
100Ω
50Ω
IOUTP
IOUTN
B0–B15
16
AVDD DVDD VCLK
AGND DGND CLKGND
Figure 6. Differential to Single-Ended Conversion Using a Wideband RF Transformer
*Note that due to their own IM effects and noise limitations, spectrum analyzers introduce ACLR errors, which can falsify the measure-ment. For a single-carrier ACLR measurement greater than 70dB, these measurement limitations are significant, becoming even morerestricting for multicarrier measurement. Before attempting an ACLR measurement, it is recommended consulting application notes pro-vided by major spectrum analyzer manufacturers that provide useful tips on how to use their instruments for such tests.
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The transmitter sections of multicarrier base stationtransceiver systems for GSM/EDGE usually presentcommunication DAC manufacturers with the difficulttask of providing devices with higher resolution, whilesimultaneously reducing noise and spurious emissionsover a desired bandwidth.
To specify noise and spurious emissions from base sta-tions, a GSM/EDGE Tx mask is used to identify the DACrequirements for these parameters. This mask showsthat the allowable levels for noise and spurious emis-sions are dependent on the offset frequency from thetransmitted carrier frequency. The GSM/EDGE maskand its specifications are based on a single active car-rier with any other carriers in the transmitter being dis-abled. Specifications displayed in Figure 10 supportper-carrier output power levels of 20W or greater.Lower output power levels yield less-stringent emissionrequirements.
For GSM/EDGE applications, the DAC demands spuri-ous emission levels of less than -80dBc for offset fre-quencies ≥6MHz. Spurious products from the DAC cancombine with both random noise and spurious prod-ucts from other circuit elements. The spurious productsfrom the DAC should therefore be backed off by 6dB ormore to allow for these other sources and still avoid sig-nal clipping.
The number of carriers and their signal levels withrespect to the full scale of the DAC are important aswell. Unlike a full-scale sinewave, the inherent nature ofa multitone signal contains higher peak-to-RMS ratios,raising the prospect for potential clipping, if the signallevel is not backed off appropriately. If a transmitteroperates with four/eight in-band carriers, each individ-ual carrier must be operated at less than -12dB FS/-18dB FS to avoid waveform clipping.
The noise density requirements (Table 2) for aGSM/EDGE-based system can again be derived fromthe system’s Tx mask. With a worst-case noise level of -80dBc at frequency offsets of ≥6MHz and a measure-ment bandwidth of 100kHz, the minimum noise densityper hertz is calculated as follows:
SNRMIN = -80dBc - 10 log10(100 103Hz)
SNRMIN = -130dBc/Hz
Since random DAC noise adds to both the spurious tonesand to random noise from other circuit elements, it is rec-ommended reducing the specification limits by about10dB to allow for these additional noise contributionswhile maintaining compliance with the Tx mask values. -120
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ANAL
OG O
UTPU
T PO
WER
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fCLK = 184.32MHzfCENTER = 30.72MHz
ACLR = 74dB
Figure 8. ACLR for W-CDMA Modulation, Single Carrier
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OG O
UTPU
T PO
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fCLK = 184.32MHz, fCENTER = 30.72MHzACLR = 67dB
Figure 9. ACLR for W-CDMA Modulation, Four Carriers
O
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0.2 0.4 0.6 1.2 1.8 6.0
IMD REQUIREMENT: < -70dBc
30kHz 100kHz
MEASUREMENT BANDWIDTH
TRAN
SMIT
TER
EDGE
INBAND OUTBAND
WORST-CASENOISE LEVEL
AMPL
ITUD
E (d
Bc)
FREQUENCY OFFSET FROM CARRIER (MHz)
Figure 10. GSM/EDGE Tx Mask Requirements
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Another key factor in selecting the appropriate DAC forthe Tx path of a multicarrier GSM/EDGE system is theconverter’s ability to offer superior IMD and MTPR perfor-mance. Multiple carriers in a designated band generateunwanted intermodulation distortion between the individ-ual carrier frequencies. A multitone test vector usuallyconsists of several equally spaced carriers, usually four,with identical amplitudes. Each of these carriers is rep-resentative of a channel within the defined bandwidth ofinterest. To verify MTPR, one or more tones areremoved such that the intermodulation distortion perfor-mance of the DAC can be evaluated. Nonlinearitiesassociated with the DAC create spurious tones, someof which may fall back into the area of the removedtone, limiting a channel’s carrier-to-noise ratio. Otherspurious components falling outside the band of inter-est can also be important, depending on the system’sspectral mask and filtering requirements. Going back tothe GSM/EDGE Tx mask, the IMD specification for adja-cent carriers varies somewhat among the different GSMstandards. For the PCS1800 and GSM850 standards,the DAC must meet an average IMD of -70dBc.
Table 3 summarizes the dynamic performance require-ments for the entire Tx signal chain in a four-carrierGSM/EDGE-based system and compares the previous-ly established converter requirements with a new-gen-eration high dynamic performance DAC.
The four-tone MTPR plot in Figure 11 demonstrates theMAX5885’s excellent dynamic performance. The centerfrequency (fCENTER = 31.99MHz) has been removed toallow detection and analysis of intermodulation or spuri-ous components falling back into this empty spot fromadjacent channels. The four carriers are observed overa 12MHz bandwidth and are equally spaced at 1MHz.Each individual output amplitude is backed off to -12dBFS. Under these conditions, the DAC yields an MTPRperformance of -82dBc.
Grounding, Bypassing, and Power-SupplyConsiderations
Grounding and power-supply decoupling can stronglyinfluence the performance of the MAX5885. Unwanteddigital crosstalk may couple through the input, refer-ence, power supply, and ground connections, affectingdynamic performance. Proper grounding and power-supply decoupling guidelines for high-speed, high-fre-quency applications should be closely followed. Thisreduces EMI and internal crosstalk that can significantlyaffect the dynamic performance of the MAX5885.
Use of a multilayer printed circuit (PC) board with sepa-rate ground and power-supply planes is recommend-ed. High-speed signals should run on lines directlyabove the ground plane. Since the MAX5885 has sepa-rate analog and digital ground buses (AGND,CLKGND, and DGND, respectively), the PC boardshould also have separate analog and digital groundsections with only one point connecting the two planes.Digital signals should be run above the digital groundplane and analog/clock signals above the analog/clockground plane. Digital signals should be kept as faraway from sensitive analog inputs, reference inputsense lines, common-mode input, and clock inputs aspractical. A symmetric design of clock input and analogoutput lines is recommended to minimize 2nd-order
NUMBER OFCARRIERS
CARRIERPOWER LEVEL
(dB FS)
DAC NOISE DENSITYREQUIREMENT
(dB FS/Hz)
2 -6 -146
4 -12 -152
Table 2. GSM/EDGE Noise Requirementsfor Multicarrier Systems
SPECIFICATIONSYSTEM TRANSMITTER
OUTPUT LEVELSDAC REQUIREMENTS WITH
MARGINSMAX5885 SPECIFICATIONS
SFDR 80dBc 86dBc 85dBc*
Noise Spectral Density -130dBc/Hz -152dB FS/Hz -155dB FS/Hz
IMD -70dBc -75dBc -79dBc
Carrier Amplitude N/S -12dB FS -12dB FS
Table 3. Summary of Important AC Performance Parameters for Multicarrier GSM/EDGESystems
*Measured within a 15MHz window.
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harmonic distortion components and optimize theDAC’s dynamic performance. Digital signal pathsshould be kept short and run lengths matched to avoidpropagation delay and data skew mismatches.
The MAX5885 supports three separate power-supplyinputs for analog (AVDD), digital (DVDD), and clock(VCLK) circuitry. Each AVDD, DVDD, and VCLK inputshould at least be decoupled with a separate 0.1µFcapacitor as close to the pin as possible and theiropposite ends with the shortest possible connection tothe corresponding ground plane (Figure 12). All threepower-supply voltages should also be decoupled at thepoint they enter the PC board with tantalum or elec-trolytic capacitors. Ferrite beads with additional decou-pling capacitors forming a pi network could alsoimprove performance.
The analog and digital power-supply inputs AVDD,VCLK, and DVDD of the MAX5885 allow a supply volt-age range of 3.3V ±5%.
The MAX5885 is packaged in a 48-pin QFN-EP (package code: G4877-1), providing greater designflexibility, increased thermal efficiency**, and optimizedAC performance of the DAC. The EP enables the userto implement grounding techniques, which are neces-sary to ensure highest performance operation. The EPmust be soldered down to AGND.
In this package, the data converter die is attached to anEP lead frame with the back of this frame exposed at thepackage bottom surface, facing the PC board side of thepackage. This allows a solid attachment of the packageto the PC board with standard infrared (IR) flow solderingtechniques. A specially created land pattern on the PCboard, matching the size of the EP (5mm 5mm),ensures the proper attachment and grounding of theDAC. Designing vias*** into the land area and imple-menting large ground planes in the PC board designallow for highest performance operation of the DAC. Anarray of at least 3 3 vias (≤0.3mm diameter per via holeand 1.2mm pitch between via holes) is recommended forthis 48-pin QFN-EP package.
Integral nonlinearity is the deviation of the values on anactual transfer function from either a best straight line fit(closest approximation to the actual transfer curve) or aline drawn between the end points of the transfer func-tion, once offset and gain errors have been nullified.For a DAC, the deviations are measured at every indi-vidual step.
Differential Nonlinearity (DNL)Differential nonlinearity is the difference between anactual step height and the ideal value of 1 LSB. A DNLerror specification of less than 1 LSB guarantees nomissing codes and a monotonic transfer function.
Offset ErrorThe offset error is the difference between the ideal andthe actual offset point. For a DAC, the offset point is thestep value when the digital input is at midscale. Thiserror affects all codes by the same amount.
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FOUR-TONE MULTITONE POWER RATIO PLOT (fCLK = 150MHz, fCENTER = 31.9885MHz)
fOUT (MHz)
OUTP
UT P
OWER
(dBm
)
AOUT = -12dB FS
fT1 fT2 fT3 fT4
fT1 = 29.9744MHzfT2 = 30.9998MHz
fT3 = 32.9773MHzfT4 = 33.8196MHz
Figure 11. 4-Tone MTPR Test Results
**Thermal efficiency is not the key factor, since the MAX5885 features low-power operation. The exposed pad is the key element toensure a solid ground connection between the DAC and the PC board’s analog ground layer.
***Vias connect the land pattern to internal or external copper planes. It is important to connect as many vias as possible to the analogground plane to minimize inductance.
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Gain ErrorA gain error is the difference between the ideal and theactual full-scale output voltage on the transfer curve,after nullifying the offset error. This error alters the slopeof the transfer function and corresponds to the samepercentage error in each step.
Settling TimeThe settling time is the amount of time required from thestart of a transition until the DAC output settles its newoutput value to within the converter’s specified accuracy.
Glitch EnergyA glitch is generated when a DAC switches betweentwo codes. The largest glitch is usually generatedaround the midscale transition, when the input patterntransitions from 011...111 to 100...000. The glitch energyis found by integrating the voltage of the glitch at themidscale transition over time. The glitch-energy is usuallyspecified in pV-s.
Dynamic Performance ParameterDefinitions
Signal-to-Noise Ratio (SNR)For a waveform perfectly reconstructed from digital sam-ples, the theoretical maximum SNR is the ratio of the full-scale analog output (RMS value) to the RMS quantizationerror (residual error). The ideal, theoretical maximum SNRcan be derived from the DAC’s resolution (N bits):
SNRdB = 6.02dB N + 1.76dB
However, noise sources such as thermal noise, refer-ence noise, clock jitter, etc., affect the ideal reading;therefore, SNR is computed by taking the ratio of theRMS signal to the RMS noise, which includes all spec-tral components minus the fundamental, the first fourharmonics, and the DC offset.
FERRITE BEAD
AVCC
1µF 10µF 47µFANALOG POWER-SUPPLYSOURCE
FERRITE BEAD
DVCC
1µF 10µF 47µFDIGITAL POWER-SUPPLY SOURCE
FERRITE BEAD
VCLK
1µF 10µF 47µFCLOCK POWER-SUPPLY SOURCE
AVDD
AGND
MAX5885
B0–B15
16
0.1µF
DGND
0.1µF
VCLK
CLKGND
0.1µF
OUTP
OUTN
DVDD
BYPASSING—DAC LEVEL BYPASSING—BOARD LEVEL
Figure 12. Recommended Power-Supply Decoupling and Bypassing Circuitry
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3.3V, 16-Bit, 200Msps High DynamicPerformance DAC with CMOS Inputs
Spurious-Free Dynamic Range (SFDR)SFDR is the ratio of RMS amplitude of the carrier fre-quency (maximum signal components) to the RMSvalue of their next-largest distortion component. SFDRis usually measured in dBc and with respect to the car-rier frequency amplitude or in dB FS with respect to theDAC’s full-scale range. Depending on its test condition,SFDR is observed within a predefined window or to Nyquist.
Two-/Four-Tone Intermodulation Distortion (IMD)
The two-tone IMD is the ratio expressed in dBc (or dB FS)of either input tone to the worst 3rd-order (or higher) IMDproducts. Note that 2nd-order IMD products usually fall atfrequencies that can be easily removed by digital filtering;therefore, they are not as critical as 3rd-order IMDs. Thetwo-tone IMD performance of the MAX5885 was testedwith the two individual input tone levels set to at least -6dB FS and the four-tone performance was testedaccording to the GSM model at an output frequency of32MHz and amplitude of -12dB FS.
Adjacent Channel Leakage Power Ratio (ACLR)
Commonly used in combination with W-CDMA, ACLRreflects the leakage power ratio in dB between themeasured power within a channel relative to its adja-cent channel. ACLR provides a quantifiable method ofdetermining out-of-band spectral energy and its influ-ence on an adjacent channel when a bandwidth-limitedRF signal passes through a nonlinear device.
Chip InformationTRANSISTOR COUNT: 10,721
PROCESS: CMOS
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Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses areimplied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
Package Information(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses areimplied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
Package Information(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,go to www.maxim-ic.com/packages.)
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