“Asymmetrical Cascaded

H-Bridge Multilevel Inverter”

Authors- Dr. S. S. Bharatkar

Mr. R. R. Bhoyar

Mr. S. A. Khadtare1

OUTLINE OF PRESENTATION-

Abstract Introduction Concept of CHB MLI 5-Level CHB MLI 7- Level Symmetrical CHB MLI 7- Level Asymmetrical CHB MLI 9- Level Asymmetrical CHB MLI Result Conclusion

2

ABSTRACT- The inverter can be categorized as two level conventional inverter and

multilevel inverter (MLI). These two level (conventional) inverters have many drawbacks particularly for high voltage and high power applications.

The MLI is able to provide more number of levels in the output. The

harmonics are greatly reduced with increase in levels and output voltage waveform approaches to sine wave.

The MLI requires more components to produce more number of levels

in the output.

This paper deals with, the study of Asymmetrical configuration for seven level and nine level H-bridge multilevel inverter. The simulations for five level symmetrical, seven level symmetrical and asymmetrical and nine level asymmetrical configurations are carried out in MATLAB. It is observed that, asymmetric MLI has ability to provide more pure output without increasing the structure compared to symmetrical MLI.

3

INTRODUCTION-

INVERTER

MULTILEVEL

CHB MLI

ASYMMETRICAL

CHB MLI

SYMMETRICAL

CHB MLI

FLYING CAPACITOR

MLINCP MLI

TWO LEVEL

4

Fig. 1 Structure of m-cells cascaded multilevel inverter

Concept of CHB MLI-

5

Fig. 2 H-bridge cell structure6

5-LEVEL CHB MLI-

S1

S2

S3

S4

S5

S6

S7

S8

S9

S10

S11

S12

S13

S14

S15

S16

S17

S18

S19

S20

S21

S22

S23

S24

N

A B C

V d c V d c

V d c

V d c

V d c V d c

7

7-LEVEL SYMMETRICAL CHB MLI-

S1

S2

S3

S4

S5

S6

S7

S8

S13

S14

S15

S16

S17

S18

S19

S20

S21

S22

S23

S24

A B C

V d c V d c

V d c

V d c

V d c V d c

V d cV d cV d c

S9

S10

S11

S12

S25

S26S28

S27

S30S32

S31S29

S34S36

S35S33

N

8

7-LEVEL ASYMMETRICAL CHB MLI-

9

Fig. 3 Seven level Asymmetrical cascaded H-bridge MLI for Phase A 10

LEVELS SWITCHES

3VdcS1, S5

2VdcS1

VdcS5

0 S1, S3, S5, S7 (OFF) & S2, S4, S6, S8 (ON)

-VdcS7

-2VdcS3

-3VdcS3, S7

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9-LEVEL ASYMMETRICAL CHB MLI-

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Result- For 5 level Inverter

0 0.08 0.16 0.24 0.32 0.4 0.48 0.56 0.64 0.72 0.8-400

-300

-200

-100

0

100

200

300

400

Time(Sec)

Ph

ase V

olt

ag

e(V

olt

s)

0 0.08 0.16 0.24 0.32 0.4 0.48 0.56 0.64 0.72 0.8-800

-600

-400

-200

0

200

400

600

800

Time(Sec)

Lin

e V

olt

ag

e(V

olt

s)

13

For 7- Level Symmetrical Inverter

0 0.08 0.16 0.24 0.32 0.4 0.48 0.56 0.64 0.72 0.8-400

-300

-200

-100

0

100

200

300

400

Time(Sec)

Ph

ase

Vo

lta

ge(V

olt

s)

0 0.08 0.16 0.24 0.32 0.4 0.48 0.56 0.64 0.72 0.8-800

-600

-400

-200

0

200

400

600

800

Time(Sec)

Lin

e V

olt

ag

e(V

olt

s)

14

For 7- Level Asymmetrical Inverter

0 0.08 0.16 0.24 0.32 0.4 0.48 0.56 0.64 0.72 0.8-400

-300

-200

-100

0

100

200

300

400

Time(Sec)

Ph

ase

Vo

lta

ge(V

olt

s)

0 0.08 0.16 0.24 0.32 0.4 0.48 0.56 0.64 0.72 0.8-800

-600

-400

-200

0

200

400

600

800

Time(Sec)

Lin

e V

olt

ag

e(V

olt

s)

15

For 9- Level Asymmetrical Inverter

0 0.08 0.16 0.24 0.32 0.4 0.48 0.56 0.64 0.72 0.8-400

-300

-200

-100

0

100

200

300

400

Time(Sec)

Ph

ase

Vo

lta

ge(V

olt

s)

0 0.08 0.16 0.24 0.32 0.4 0.48 0.56 0.64 0.72 0.8-800

-600

-400

-200

0

200

400

600

800

Time(Sec)

Lin

e V

olt

ag

e(V

olt

s)

16

THD and Vdc values for output line voltage of 400V

TYPE VOLTAGE (volts) THD (%)

5-LEVEL SYMMECTRICAL

163.5 17.12

7-LEVEL SYMMETRICAL

109 10.63

7-LEVEL ASYMMETRICAL

109 10.63

9-LEVEL SYMMETRICAL

79 7.90

9-LEVEL ASYMMETRICAL

79 7.90

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COMPARISON OF MLI-Type of Inverter No. of Switches No. of DC Sources

5-level symmetrical

24 6

7-level symmetrical

36 9

9-level symmetrical

48 12

7-level Asymmetrical

24 6

9-level Asymmetrical

24 6

18

CONCLUSION-

From the simulation results it is concluded that, by taking different geometric progression factor the output levels of Asymmetrical MLI can be increased without any increased in components. So the output of ACMLI has very less amount of harmonic content i.e., the output is smoother. As compare to SCMLI, the numbers of bridges, DC sources required in ACMLI are less for attaining same number of levels. So the problem of requirement of more components to achieve more number of output levels are eliminated with proposed ACMLI topology. 19

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THANK YOU!

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