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3D FD-TD algorithm Thermal Model -...

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    F . Pardo

    3D FD-TD algorithmThermal Model

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    Out l ine

    FD-TD algorithm and applications Landmine detection Description of the hardware FD-TD FPGA implementation

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    FD-TD and app l i cat ions

    FD-TD useful to solve PDE equations Spatial discretization:

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    FD-TD and app l i cat ions

    Temporal discretization: computation in discrete time steps


    T t

    2T x2


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    FD-TD and app l i cat ions

    Temporal discretization:

    Spatial discretization

    T r ,t t

    Tm1T m


    2T r , t x2

    T i1 jkT i1 jk2Tijk

    x 2

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    FD-TD and app l i cat ions

    Applications: Discrete Scattering: scattering of EM in

    discrete objects Antenna Design GPR and thermal simulation Medical studies (effects of radiation on

    bodies) Digital circuit packaging on multilayer circuits

    boards ......

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    FD-TD and app l i cat ions

    Main drawback: high memory and power calculation calculation consume

    Not widely used until 90's The first hardware implementation 1996

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    Landmine detect ion

    Plastic antipersonnel mines

    Metal detectors does not work

    Infrared images of the soil

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    Landmine detect ion

    Thermal processes

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    Landmine detect ion

    Heat Equation:

    Boundary conditions:

    T t

    2T x2


    T r , t n

    = qnet for x

    T r , t n

    = 0 for x /

    T x , y , z ,t = T in T r , t=t0 =T 0 in

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    Landmine detect ion

    Mines and soil have different thermal properties (thermal contrast)

    Presence of the mine perturbs the thermal behaviour of the soil

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    Descr ip t ion o f the hardware

    RC2000 card from Celoxica

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    Descr ip t ion o f the hardware

    RC2000: FPGA: Xilinx Virtex II xc2v6000-4:

    6 M gates 96 x 88 CLBs 144 Multipliers 2592 Kbits of SelRAM

    6 Memory banks of 2 MB (FPGA and Host) 2 Memory banks of 4 MB (only FPGA) PCI carrier

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    Descr ip t ion o f the hardware

    RC2000 block diagram

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    FPGA FD-TD implementat ion

    System overview:

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    FPGA FD-TD implementat ion

    Hardware overview

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    FPGA FD-TD implementat ion

    Processing element

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    FPGA FD-TD implementat ion

    Host FPGA communication through the GPIO (Global Purpose Input Out) register

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    FPGA FD-TD implementat ion

    VHDL vs Handel-C

    Handel-C VHDLSlices 6607 (20%) 5406 (16%)Select RAM 135 (96 %)Multipliers 12 (9%) 6 (4%)External IOB 573 (54%)Frequency 42 MHz 50MHzSpeed-up 46 100

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    FPGA FD-TD implementat ion

    Handel-C main advantage is the short development time

    VHDL allows to obtain more compact and efficient designs

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    FPGA FD-TD implementat ion

    Drawbacks: Low parallelism Low FPGA utilization

    Advantages: High speed up Scalable design

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    Future Work

    Electromagnetic simulations Pipeline multipliers:

    Trade off speed / latency

    More parallelism ->More memory banks Internal cache

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