3D Hetero-Integration Technology for Future Automotive Smart...

3D Hetero-Integration Technology for

Future Automotive Smart Vehicle System

Kangwook Lee, Tohoku University

Kangwook Lee, Ph.D

Professor, NICHe, Tohoku University

Deputy Director, Global INTegration Initiative (GINTI)

• Background

• Smart Vehicle System for Future Automotive

• 3-D Hetero-Integration Technologies for Smart

Vehicle System

• High Speed, Highly Parallel Processing Image Sensor

Module in Smart Vehicle System

• Summary

AgendaAgendaAgendaAgenda

Potential Applications of 3-D Integration Beyond Mobile & Consumer Products

Killer Application!

� Anticipated applications start for consumer mobile products and extend to high-performance, multi-functional hetero-integrated convergence systems

Yole Report, 2012

BackgroundBackgroundBackgroundBackground

Automotive Is A Emerging Market For SemiconductorBackgroundBackgroundBackgroundBackground

DENSO Corp., IEEE 3D-IC 2011, Osaka,

Evolution Directions of Future Smart Automotive

� Environment – Ecology � Super Clean, Zero Emission, Ultimate Recycling System

� Comfort - Convenience � Smart Highway, Connected Car, Joyful Mobility

� Safety � Zeronize (Accident) Intelligent Safety Systems, Automated Driving


(Autonomous Driving Car)

(Crash-Proof Car)

Automotive Industry Seeking Electronic Solutions For Safety in Future Automotive

� From "Damage Reduction and Collision Avoidance" to Autonomous Driving"


Automotive Industry Seeking Electronic Solutions For Safety in Future Automotive

� Communicate with various sensor networks as a sensor terminal within thecar and to the world around car (car-to-car, car-to-infrastructure) to improvetraffic safety for all road users, increase efficiency of the public transportsystems, and induce better response to hazards, incidents and accidents�� Connected Car, Smart Highway

☞ Safety vehicle system requires high speed signal sensing and high dataprocessing depending on the moving speed of car. It needs more fastlygather and parallely analyze a lot of information from environment


� Limited number of modules/parts can be installed in car due to large size � Limitation of high speed signal sensing and high data transmission

networking due to long distance between modules/parts� Large power consumption

Current Safety Vehicle Electronic Systems

☞ Require integrated vehicle electronic systems for high performance functions and low power consumption

Smart Smart Smart Smart Vehicle System Vehicle System Vehicle System Vehicle System for Future Automotivefor Future Automotivefor Future Automotivefor Future Automotive

Challenges K-W. Lee et al, IEEE IEDM 2009, IEEE T-ED 2011Infineon, 3D Architecture, 2011

� Many numbers and various kinds of LSIs and sensor devices, and ECUs are loaded in car to assist an autonomous driving. It steadily increasing in future; ex) 1000 chips, 47 ECU (electronic control unit), 3.6km wire (Hyundai Equus,2013)

� An estimated 40% of a vehicle`s cost is determined by electronics and S/W(146% increase since the `90s). An estimated 90% of all innovation in automotive are driven by electronics and S/W

� Electronics determine the competiveness of automotive industry in future

Electronics Becomes The Car

http://www.murata.co.jp

☞ Need a smart vehicle system for future automotive

Smart Smart Smart Smart Vehicle System Vehicle System Vehicle System Vehicle System for Future Automotivefor Future Automotivefor Future Automotivefor Future Automotive

Demands for Smart Vehicle SystemHigh Speed Sensing – Highly Parallel Data Processing - Acting

� Small form-factor & miniaturization for low power consumption

� High speed variable real-time signal (distance, velocity, imaging) sensing

and highly parallel data computing/processing, and high speed data

communication between vehicle systems in car and to outside networking

� Hetero-integration of more sensors, more functionality, more information

and more digitalization in system

Smart Smart Smart Smart Vehicle Vehicle Vehicle Vehicle System for Future AutomotiveSystem for Future AutomotiveSystem for Future AutomotiveSystem for Future Automotive

☞ How to compactly integrate heterogeneous LSIs, sensors and photonic devices into a smart vehicle system ?



Analog Devices, SEMI WEST 2010

High density, small form-factor, and hetero-integration of

ECU multi-chip module

http://www.murata.co.jp


� Smaller package of complete solution

Intelligent integrated system of a sensor, micro controller,

passives and power converter in a multilayer block


MEMS accelerator for high sensitive sensing of high speed moving element

Image sensor stacked with ADC LSI for high performance imaging processing

3D processor, 3D memory for high performance computing

Optical interconnection of photonics for high speed data transmission networking

Micro-fluidic channels for the sinking of generated heatK-W. Lee et al, IEEE IEDM 2009, IEEE T-ED 2011

3-D hetero-integrated smart vehicle system of LSIs, sensors,

power ICs, and photonics devices


� Integration technologies ; heterogeneous 3D integration amongst MEMS, sensors, SoC, memory, photonic, and power devices

� Extremely high performance microprocessors ; multi-core technologies with affinity to image recognition and real-time processing

� Energy technologies ; smart grid systems and novel power devices

� Total design methodologies ; ESL design technologies between automotive systems and semiconductors

Evolution Directions of Semiconductor Technologies For Smart Vehicle System in Future Automotive


DENSO Corp., IEEE 3D-IC 2011

All Functions into One Cube !!

3333----D HeteroD HeteroD HeteroD Hetero----Integration Technologies for Integration Technologies for Integration Technologies for Integration Technologies for Smart Vehicle Smart Vehicle Smart Vehicle Smart Vehicle System System System System

3D System Integration Projects in Tohoku Univ.

1978 (IEDM) : 3D DRAM

1989 (Future Electron Device) : 3D Integration Technology

1999 (IEDM) : 3D Image Sensor (Wafer-level Stacking)

2000 (IEDM) : 3D Shared Memory (Wafer-level Stacking)

2001 (ISSCC) : 3D Artificial Retina (Wafer-level Stacking)

2002 (Cool Chips) : 3D Microprocessor (Wafer-level Stacking)

2005 (IEDM) : Super Chip Integration, 10-Layers Memory, Self-Assembly

2007 (IEDM) : Reconfigured Wafer-to-Wafer 3D Integration, Self-Assembly

2008 (IEDM) : Heterogeneous Multi-Chip Module (LSI-MEMS)

2009 (IEDM) : 3D Hetero-integrated Opto-Electronic System (LSI-MEMS-Optics)

2012 (IEDM) : Chip-based 3D Heterogeneous Integration Technology

Hybrid Self-Assembly and Electrostatic Temporary Bonding

3-D Super-Chip

System-on-Board

CMOS-compatible, high flexible 3-D heterogeneous integration of photonics, LSI/power devices, and MEMS sensors for smart vehicle system

T. Fukushima et al., IEDM, 2008

K.W. Lee et al., IEEE 3D SIC, 2009

High-throughput heterogeneous multi-chip integration

by self-assembly and sidewall interconnection

Optical interconnection by

Si interposer with optical waveguide

Noriki et al., SSDM, 2008

K.W. Lee et al., IEEE IEDM 2009

VCSEL PDSi Interposer

Optical Waveguide

Cu TSV

Optical Signal

High accuracy 3D integration

by wafer-level bonding

1st layer

2nd layer

3rd layer TSV

30um

Micro-bump

K.W. Lee et al., IEDM, 2000



- Wafer Bonding

- Thinning

- Bumping

3D stacked LSI wafer

- TSV formation

- Optimal CMOS process

- Wafer burn-in test & repair

M. Koyanagi, Proc. 8th Symposium on Future Electron Devices, 1989

Wafer-level 3D Stacking Technology

☞ 1st proposal of 3D WtW Stacking with TSV

Surface tension of liquid is utilized for chip self-assembly⇒ Damage-free, high accuracy, and high speed bonding

(Top View)

(Cross-sectional View)

HydrophilicBonding Area

LiquidDroplet

Chip HavingHydrophilic Backside

2. Liquid

Supply3. Chip Release 4. Self-Assembly

(Self-aligning & Bonding)

1. HydrophilicArea

HydrophobicArea

LiquidEvaporation



Self-Assembly 3D Stacking Technology

Wafer Testing Sorting of KGDs Multichip-to-Wafer

3D Stacking

By Self-Assembly


Multi-KGDs layers are simultaneously aligned and bonded on LSI wafer by self-assembly method in batch


Multichip-to-Wafer Bonding by Self-Assembly

Wafer Testing Sorting of KGDs Multichip-to-Wafer

3D Stacking

By Self-Assembly

3D LSIs

LSI Wafer C

LSI Wafer A

LSI Wafer B

KGDs Wafer C

KGDs Wafer B

KGDs Wafer A

T. Fukushima et al., IEEE IEDM, 2008

Photograph of various-size self-assembled chips on 8-inch wafer by hybrid self-assembly



(Reconfigured Substrate)

MemoryProcessor

Logic LS

I

IF chip

RF chip

Passives MEMS

Substrate

Various type KGD chips can be integrated simultaneously

on a substrate in wafer-level

� Batch process for high throughput, low cost solution

K.W. Lee et al., IEEE 3D-IC, 2009

A. Self-assembly of heterogeneous multi-chips

with high throughput, high accuracy

B. High step-height sidewall interconnection

C. Fine pitch, high density micro-bumps

D. Passive device on a chip

AB

C

D

Concept of heterogeneous MEMS-LSI multi-chip module


Concept of 3D opto-electronics hetero-integrated system

PDVCSEL

TSV

mirror

Micro-bump

CladdingOptical waveguide

Si substrate

Aperture

Core

Optical

interposer

3D-LSI

Low Loss Optical Waveguide

Low Loss

Optical Coupling

Short Electrical InterconnectAccurate Passive Alignment of

Optical Component

☞ High speed, low energy inter-chip optical interconnection

K.W. Lee et al., IEDM, 2009


Photograph of MEMS-LSI multi-chip module

� LSI, passive and MEMS chips are mounted on substrate by self-assembly � LSI and passive chips are connected by Cu sidewall interconnection� MEMS chip is connected by the cavity chip K.W. Lee et al., IEEE 3D-IC, 2009


Photograph of MEMS-LSI multi-chip module

� MEMS chip vertically stacked on LSI chip by self-assembly

K.W. Lee et al., IEEE 3D-IC, 2009

MEMS Chip

LSI Chip

Substrate

Cu Sidewall Interconnection


Concept of die-level 3D hetero-integration technology

Commercial Chips Chip Process 3D Integration

Commercial chips with different functions and sizes, which were fabricated bydifferent technologies, are processed and integrated in chip-level using backsideTSV and novel detachable technologies

� Low-cost, high flexible, and rapid prototyping solution for 3-D LSIs

K.W. Lee et al., IEEE IEDM, 2012


Process flow of die-level 3-D hetero-integration technology


High Speed Sensing, Highly Parallel Processing Image Sensor Module for Autonomous Driving Assist

� Image sensor module comprising 3-D stacked image sensorsfor high speed signal sensing and 3-D stacked dependableVLSI systems for high performance data processing

- IEEE IEDM 2012

- IEEE T-ED 2013

High Speed, Highly Parallel Processing Image High Speed, Highly Parallel Processing Image High Speed, Highly Parallel Processing Image High Speed, Highly Parallel Processing Image Sensor Module (Tohoku Univ.)Sensor Module (Tohoku Univ.)Sensor Module (Tohoku Univ.)Sensor Module (Tohoku Univ.)

- IEEE ECTC 2014

- IEEE IEDM 2014

3-D Stacked Image Sensor

3-D Stacked VLSI system

3-D Stacked Stereo Vision Image Sensor for High Speed Signal Sensing

CISCDSADC

IFSi interposer A

CISCDSADC

IFSi interposer A

Organic Substrate

Si interposer B

Rear radar

Rear Front

Front surveillancemm-wave radar

Ultrasonicsensor

Short rangemm-wave radarRear

camera

Rearsideradar

Front surveillanceImage sensor

Analog chipADC chip

Interface chip

Image sensor chipColor Filter

Micro Lens

Block Parallel Architecture- High frame rate ; 10,000 frames/s

- High pixel rate ; 2M Pixel

ASET

Dream Chip Project


Configuration and Circuit Block of 3-D Stacked Image Sensor with Block-Parallel Processing

Optical Signal

Metal Adhesive Bump TSV


Photograph of Fabricated 3-D Stacked Image Sensorwith Three-layer Structure

3-D Stacked Image SensorModule with Twin-lens

Cross-sectional Structure of 3-D Stacked Image Sensor

Commercial 2-D Chips

FPGA



X-Ray CT Scan Image of Fabricated 3-D Stacked Image Sensor with Four-layer Structure


CDS Chip

Image SensorChip

ADC Chip

InterposerChip

IF Chip

High Speed Sensing, Highly Parallel Processing Image Sensor Module for Autonomous Driving Assist

� Image sensor module comprising 3-D stacked image sensorsfor high speed signal sensing and 3-D stacked dependableVLSI systems for high performance data processing

- IEEE IEDM 2012

- IEEE T-ED 2013

High Speed, Highly Parallel Processing Image High Speed, Highly Parallel Processing Image High Speed, Highly Parallel Processing Image High Speed, Highly Parallel Processing Image Sensor Module Sensor Module Sensor Module Sensor Module

- IEEE ECTC 2014

- IEEE IEDM 2014


3-D Stacked VLSI system

High Speed, Highly Parallel Processing Image High Speed, Highly Parallel Processing Image High Speed, Highly Parallel Processing Image High Speed, Highly Parallel Processing Image Sensor Module Sensor Module Sensor Module Sensor Module

K.W. Lee et al., IEEE ECTC, 2014

Master

Processor Chip

(Self-Test/Self-Re

pair)

Processor

Chips

(7-layers)

Memory

Chips

(4-layers)

High Dependable 3-D Stacked VLSI System with Self-Test and Self-Repair Functions

JST-CREST Project: “Fundamental technologies for dependable VLSI system”M. Koyanagi: “Three-Dimensional VLSI System with Self-Restoration Function”

H. Hashimoto. et al., IEEE 3D-IC, 2013

Block Diagram of Resilient 3-D Stacked Multicore Processor System

Tier 2

Tier 1

Tier 0

Ext

ern

al

Me

mo

ry

Vertical Bus using TSVs

Test Access Port

(3D TAP)

Test Bus

System Bus Memory Bus

Mem Ctrl:

Memory

controller

VBB:

Vertical

bus bridge

SM:

Stacked shared

memory

Core:

Processor core

PBB: PB bridge

OSTC:

On-line self-test

controller

MemCtrlSMVBBCorePBBOSTC




SystemBus

Tier 3

Tier 7

Photograph of fabricated 2-D core processor chip

(Core Processor Chip, 90nm)





Si Interposer

Configuration (a), top view (b), and SEM cross-section (c) of fabricated 3-D stacked multicore processor chip with two layers

(a) Configuration

2-layered 3-D Stacked

Multicore Processor Chip

1st

Chip

2nd

ChipCu TSV

Cu RDL Cu/Sn

Bump

(b) Top View

(c) SEM Cross-section


X-ray CT-scan image of TSV array in two-layered 3-D stacked multicore processor chip

Cu TSVs

(1st Layer)

Cu TSVs

(2nd Layer)

Interposer

Cu RDL,

Cu/Sn Bump

(2nd Layer)

Cu RDL,

Cu/Sn Bump

(1st Layer)

(Captured image from the movie) (CT-scan movie)


�Vehicle system require high reliability and robustness to vibration and elevated temperature and other environments. But, current 3-D integration technologies not meet severe demand specifications for vehicle system

� It is strongly required to develop 3-D hetero-integration technologies (process, material, structure) for smart vehicle system in future automotive

Challenges for Smart Vehicle System Challenges for Smart Vehicle System Challenges for Smart Vehicle System Challenges for Smart Vehicle System

Toyota, 2009

�Automotive is a emerging market for semiconductor. Automotive industry seek electronic solutions for safety in future automotive

�Large numbers and various kinds of LSIs and sensor devices such as radars, sensors, local area network, power devices and electronic control units are loaded in an automotive to prevent abnormal accidents and to assist an autonomous driving

�The automotive sector could become one of the key markets for 3-D integration. 3-D hetero-integration technologies are introduced for the smart vehicle system in future automotive

�High speed sensing, highly parallel processing image sensor module for autonomous driving assist is proposed. Image sensor module with 3-D stacked image sensor and 3-D stacked multicore processor was successfully demonstrated for the first time as a typical example of smart vehicle system

�It is still challenges to develop 3-D hetero-integration technologies (process, material, structure) to meet severe demand specifications for smart vehicle system in future automotive

SummarySummarySummarySummary

AcknowledgementAcknowledgementAcknowledgementAcknowledgement

This research was supported by the Dependable

VLSI Project of Core Research for Evolutional

Science and Technology (CREST) of Japan Science

and Technology Corporation (JST) and by NEDO

“Development of Functionally Innovative 3D-

Integrated Circuit (Dream Chip) Technology”

Project that is based on the Japanese

government’s METI “IT Innovative Program”.

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