3.Fiscal Access System Using Rfid Document

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FISCAL ACCESS SYSTEM USING RFID

1



INDEX

CONTENTS

1. Abbreviations

2. Fi!res "o#ations

$. Intro%!#tion

&. '"o#( Diara)

*. '"o#( Diara) Des#ri+tion

,. S#-e)ati#. S#-e)ati# Des#ri+tion

/. 0ar%are Co)+onents

• oer s!++"3

• Mi#ro#ontro""er

• RFID Rea%er

• LCD

• 4e3+a%

• EEROM

• '!55er

6. Cir#!it Des#ri+tion

17.So8tare #o)+onents

a. Abo!t 4ie"

b. E)be%%e% 9C:

11. 4EIL +ro#e%!re %es#ri+tion

12.Con#"!sion ;or< S3no+sis

1$. F!t!re As+e#ts

1&. 'ib"iora+-3

2



Abbreviations

S3)bo" Na)eACC A##!)!"ator' ' reister

S= rora) stat!s or%

S Sta#( +ointer

DTR Data +ointer 2 b3tes

DL Lo b3te

D0 0i- b3te

7 ort7

1 ort1

2 ort2

$ ort$I Interr!+t +riorit3 #ontro"

IE Interr!+t enab"e #ontro"

TMOD Ti)er>#o!nter )o%e #ontro"

TCON Ti)er>#o!nter #ontro"

T2CON Ti)er>#o!nter 2 #ontro"

T2MOD Ti)er>#o!nter )o%e2 #ontro"

T07 Ti)er>#o!nter 7-i- b3te

TL7 Ti)er>#o!nter 7 "o b3te

T01 Ti)er>#o!nter 1 -i- b3te

TL1 Ti)er>#o!nter 1 "o b3te

T02 Ti)er>#o!nter 2 -i- b3teTL2 Ti)er>#o!nter 2 "o b3te

SCON Seria" #ontro"

S'UF Seria" %ata b!88er

MAX MAXIM ;IC )an!8a#t!rer <

TTL Transistor to Transistor Loi#

ATM A!to)ati# Te""er Ma#-ine

RS 2$2 Re#o))en%e% Stan%ar%

AC A"ternatin C!rrent

DC Dire#t C!rrent

LCD Li?!i% Cr3sta" Dis+"a3C ersona" Co)+!ter

RS Re!"ate% oer S!++"3

RMS Root Mean S?!are

EEROM E"e#tri#a""3 Erasab"e rora))ab"e ROM

ROM Rea% On"3 Me)or3

RAM Ran%o) A##ess Me)or3

'IOS 'asi# In+!t O!t+!t S3ste)

3



SRAM Stati# RAM

EROM Erasab"e rora))ab"e ROM

DRAM D3na)i# Ran%o) A##ess Me)or3

ISR Interr!+t Servi#e Ro!tine

ICC Interate% Cir#!it C-i+

CAD Car% A##e+tan#e Devi#eIFD Inter8a#e Devi#e

IDE Interate% Deve"o+)ent Environ)ent

Fi!re Lo#ations

S.No. Fi!re ae No.

1

Components of Typical Linear PowerSupply

2

An Electrical Transformer 3 Bridge Rectifier 4 Bridge Rectifier Positie Cycle5 Bridge Rectifier !egatie Cycle6 T"ree terminal oltage Regulator 7 #unctional $iagram of %icrocontroller 8 Pin $iagram of %icrocontroller 9 &scillator connections10 E'ternal cloc( drie connections11 A register 12 B register

13 RA%14 RA% Allocation15 Register Ban(s16 PS)17 $PTR 18 SP19 P&RT *20 TL* and T+*

,



21 $B-22 Connecting %icrocontroller to PC23

24

25

26 LC$27

28

29

30

31

32

33 Linear .eypad34 Pro/ect35 !ew Pro/ect36 Select Target deice37 Select deice for Target38 Copy 0*1 startup code39 Source group 140 !ew file41 &pened new file42 #ile Sae43 Add files to t"e source group44 Adding files to t"e source group45 Compilation46 After Compilation47 Build48 Selecting t"e Ports to e isualied49 Start $eugging



INTRODUCTION

EM'EDDED SYSTEM@

An e)be%%e% s3ste) is a special4purpose system in w"ic" t"e computer is completely

encapsulated y or dedicated to t"e deice or system it controls5 6nli(e a general4purpose

computer7 suc" as a personal computer7 an emedded system performs one or a few predefined

tas(s7 usually wit" ery specific re8uirements5 Since t"e system is dedicated to specific tas(s7

design engineers can optimie it7 reducing t"e sie and cost of t"e product5 Emedded systems

are often mass4produced7 enefiting from economies of scale5

Personal digital assistants 9P$As: or "and"eld computers are generally considered

emedded deices ecause of t"e nature of t"eir "ardware design7 een t"oug" t"ey are more

e'pandale in software terms5 T"is line of definition continues to lur as deices e'pand5 )it"

t"e introduction of t"e &;& %odel 2 wit" t"e )indows <P operating system and ports suc" as a

=



6SB port > ot" features usually elong to ?general purpose computers?7 > t"e line of

nomenclature lurs een more5

P"ysically7 emedded systems ranges from portale deices suc" as digital watc"es and

%P3 players7 to large stationary installations li(e traffic lig"ts7 factory controllers7 or t"e systems

controlling nuclear power plants5

@n terms of comple'ity emedded systems can range from ery simple wit" a single

microcontroller c"ip7 to ery comple' wit" multiple units7 perip"erals and networ(s mounted

inside a large c"assis or enclosure5

Ea)+"es o8 E)be%%e% S3ste)s@

• Aionics7 suc" as inertial guidance systems7 flig"t control "ardwaresoftware and ot"er

integrated systems in aircraft and missiles

• Cellular telep"ones and telep"one switc"es

• Engine controllers and antiloc( ra(e controllers for automoiles

• +ome automation products7 suc" as t"ermostats7 air conditioners7 sprin(lers7 and security

monitoring systems

• +and"eld calculators

• +and"eld computers

• +ouse"old appliances7 including microwae oens7 was"ing mac"ines7 teleision sets7

$$ players and recorders

• %edical e8uipment



• Personal digital assistant

• ideogame consoles

• Computer perip"erals suc" as routers and printers5

•

@ndustrial controllers for remote mac"ine operation5

'LOC4 DIAGRAM@

R# @$REA$ER

%icrocontroller

Powersupply

LC$

EEPR&%

.EDPA$

B6ER

0



Bloc( $iagram description

T"is Pro/ect mainly consists of Power Supply section7 %icrocontroller section7 .eypad

section7 R#@$ Reader section7 LC$ display section7 EEPR&% section and RTC 9Real Time

Cloc(: section5

oer S!++"3 Se#tion@

T"is section is meant for supplying Power to all t"e sections mentioned aoe5 @t asically consists of a Transformer to step down t"e 23* ac to - ac followed y diodes5 +ere

diodes are used to rectify t"e ac to dc5 After rectification t"e otained rippled dc is filtered using

a capacitor #ilter5 A positie oltage regulator is used to regulate t"e otained dc oltage5

Mi#ro#ontro""er Se#tion@

-



T"is section forms t"e control unit of t"e w"ole pro/ect5 T"is section asically consists of

a %icrocontroller wit" its associated circuitry li(e Crystal wit" capacitors7 Reset circuitry7 Pull

up resistors 9if needed: and so on5 T"e %icrocontroller forms t"e "eart of t"e pro/ect ecause it

controls t"e deices eing interfaced and communicates wit" t"e deices according to t"e

program eing written5

LCD Dis+"a3 Se#tion@

T"is section is asically meant to s"ow up t"e status of t"e pro/ect5 T"is pro/ect ma(es

use of Li8uid Crystal $isplay to display prompt for necessary information5

4e3+a% Se#tion@

T"is section consists of a Linear .eypad5 T"is (eypad is used to enter t"e details ofe'piry date and purc"age date of t"e p"arma5 T"e (eypad is interfaced to microcontroller w"ic"

continuously scans t"e (eypad5

RFID Rea%er ;Ra%io Fre?!en#3 I%enti8i#ation<@

Radio #re8uency @dentification 9R#@$: is a generic term for non4contacting tec"nologiest"at use radio waes to automatically identify people or o/ects5 T"e comined antenna and

microc"ip are called an ?R#@$ transponder? or ?R#@$ tag? and wor( in comination wit" an

?R#@$ reader?5

Radio #re8uency @dentification 9R#@$: is t"e latest tec"nology t"at is eing adopted to

trac( and trace materials7 including oo(s5 R#@$ ased Lirary %anagement System "as een

implemented in most of t"e reputed liraries across t"e gloe5 R#@$ interfaced lirary

management system7 along wit" smart card issued to t"e users are eing implemented to

automate t"e lirary functions and ma(e t"e inentory management process efficient and

effectie5 T"e system improes t"e trac(ing of oo(s and documents so t"at t"e oo(s can e

more 8uic(ly located7 t"e document wor(flow more easily trac(ed and transaction records are

seamlessly captured5

1*



EEROM Se#tion@

T"is section asically consists of an EEPR&%5 @n t"is pro/ect t"is section asically used

as a ac(end dataase5 T"e details of t"e e'piry date and purc"ase date of medicines are stored in

t"e memory called EEPR&%5

S#-e)ati#

11



12



0ARD=ARE Co)+onents

T"e +ardware components used in t"is pro/ect are

Regulated Power Supply

%icrocontroller

R#@$ reader

13



LC$

.eypad

EEPR&%

uer

REGULATED O=ER SULY

T"e power supplies are designed to conert "ig" oltage AC mains electricity to a

suitale low oltage supply for electronics circuits and ot"er deices5 A RS 9Re!"ate% oer

S!++"3: is t"e Power Supply wit" Rectification7 #iltering and Regulation eing done on t"e AC

mains to get a Regulated power supply for %icrocontroller and for t"e ot"er deices eing

interfaced to it5

1,



A power supply can y ro(en down into a series of loc(s7 eac" of w"ic" performs a

particular function5 A d5c power supply w"ic" maintains t"e output oltage constant irrespectie

of a5c mains fluctuations or load ariations is (nown as FRegulated $5C Power SupplyG

#or e'ample a regulated power supply system as s"own elowH

#ig 1 Components of linear power supply

Trans8or)er@

A transformer is an electrical deice w"ic" is used to conert electrical power from

one Electrical circuit to anot"er wit"out c"ange in fre8uency5

Transformers conert AC electricity from one oltage to anot"er wit" little loss of

power5 Transformers wor( only wit" AC and t"is is one of t"e reasons w"y mains electricity is

AC5 Step4up transformers increase in output oltage7 step4down transformers decrease in output

oltage5 %ost power supplies use a step4down transformer to reduce t"e dangerously "ig" mains

oltage to a safer low oltage5 T"e input coil is called t"e primary and t"e output coil is called

t"e secondary5 T"ere is no electrical connection etween t"e two coilsI instead t"ey are lin(ed y

an alternating magnetic field created in t"e soft4iron core of t"e transformer5 T"e two lines in t"e

middle of t"e circuit symol represent t"e core5 Transformers waste ery little power so t"e

power out is 9almost: e8ual to t"e power in5 !ote t"at as oltage is stepped down current is

stepped up5 T"e ratio of t"e numer of turns on eac" coil7 called t"e turnJs ratio7 determines t"e

1



ratio of t"e oltages5 A step4down transformer "as a large numer of turns on its primary 9input:

coil w"ic" is connected to t"e "ig" oltage mains supply7 and a small numer of turns on its

secondary 9output: coil to gie a low output oltage5

#ig 2 H An E"e#tri#a" Trans8or)er

Turns ratio K p S K !p!S

Power &utK Power @n

S < @SKP < @P

p K primary 9input: oltage

!p K numer of turns on primary coil

@p K primary 9input: current

RECTIFIER@

A circuit w"ic" is used to conert a5c to dc is (nown as RECT@#@ER5 T"e process of conersion a5c to d5c is called FrectificationGTYES OF RECTIFIERS@

• +alf wae Rectifier • #ull wae rectifier

15 Centre tap full wae rectifier525 Bridge type full ridge rectifier5

Co)+arison o8 re#ti8ier #ir#!its@

ara)eter

T3+e o8 Re#ti8ier

0a"8 ave F!"" ave 'ri%e

!umer of diodes

1

2 ,

P@ of diodes

m

2m m

1=





#ig 3 H Bridge rectifier

O+eration@

$uring positie "alf cycle of secondary7 t"e diodes $2 and $3 are in forward iased w"ile $1

and $, are in reerse iased as s"own in t"e fig9,:5 T"e current flow direction is s"own in t"e fig

9,: wit" dotted arrows5

#ig 9,:H Bridge Rectifier Positie Cycle

$uring negatie "alf cycle of secondary oltage7 t"e diodes $1 and $, are in forward iased

w"ile $2 and $3 are in reerse iased as s"own in t"e fig9:5 T"e current flow direction iss"own in t"e fig 9: wit" dotted arrows5

10



#ig9: H Bridge Rectifier !egatie Cycle

Fi"ter@A #ilter is a deice w"ic" remoes t"e a5c component of rectifier output ut

allows t"e d5c component to reac" t"e load

Ca+a#itor Fi"ter@

)e "ae seen t"at t"e ripple content in t"e rectified output of "alf wae rectifier is 121 or

t"at of full4wae or ridge rectifier or ridge rectifier is &/ suc" "ig" percentages of ripples is

not acceptale for most of t"e applications5 Ripples can e remoed y one of t"e followingmet"ods of filtering5

;a< A capacitor7 in parallel to t"e load7 proides an easier y Mpass for t"e ripples oltage t"oug"

it due to low impedance5 At ripple fre8uency and leae t"e $5C5 to appear at t"e load5

;b< An inductor7 in series wit" t"e load7 preents t"e passage of t"e ripple current 9due to "ig"

impedance at ripple fre8uency: w"ile allowing t"e d5c 9due to low resistance to d5c:

;#< arious cominations of capacitor and inductor7 suc" as L4section filter section filter7

multiple section filter etc5 )"ic" ma(e use of ot" t"e properties mentioned in 9a: and 9: aoe5

Two cases of capacitor filter7 one applied on "alf wae rectifier and anot"er wit" full wae

rectifier5

#iltering is performed y a large alue electrolytic capacitor connected across t"e $C

supply to act as a reseroir7 supplying current to t"e output w"en t"e arying $C oltage from

t"e rectifier is falling5 T"e capacitor c"arges 8uic(ly near t"e pea( of t"e arying $C7 and t"en

1-



disc"arges as it supplies current to t"e output5 #iltering significantly increases t"e aerage $C

oltage to almost t"e pea( alue 915, N R%S alue:5

To calculate t"e alue of capacitor9C:7

C K O3frRl

)"ere7

f K supply fre8uency7

r K ripple factor7

Rl K load resistance

NoteH @n our circuit we are using 1***Q# "ence large alue of capacitor is placed to

reduce ripples and to improe t"e $C component5

Re!"ator@

oltage regulator @cs is aailale wit" fi'ed 9typically 7 12 and 1: or ariale output

oltages5 T"e ma'imum current t"ey can pass also rates t"em5 !egatie oltage regulators are

aailale7 mainly for use in dual supplies5 %ost regulators include some automatic protection

from e'cessie current 9oerload protectionJ: and oer"eating 9t"ermal protectionJ:5 %any of

t"e fi'ed oltage regulators @cs "ae 3 leads and loo( li(e power transistors7 suc" as t"e 0*

1A regulator s"own on t"e rig"t5 T"e L%0* is simple to use5 Dou simply connect t"e positie lead of your unregulated $C power supply 9anyt"ing from -$C to 2,$C: to t"e

@nput pin7 connect t"e negatie lead to t"e Common pin and t"en w"en you turn on t"e power7

you get a olt supply from t"e output pin5

#ig =H A T"ree Terminal oltage Regulator

/XX@

2*





&ne of t"e ma/or differences etween a %icroprocessor and a %icro controller is t"at a controller

often deals wit" its not ytes as in t"e real world application5

@ntel "as introduced a family of %icro controllers called t"e %CS415

T-e Maor Feat!res@

• Compatile wit" %CS41 products

• ,( Bytes of in4system Reprogrammale flas" memory

• #ully static operationH *+ to 2,%+

• T"ree leel programmale cloc(

• 120 0 Mit timercounters

• Si' interrupt sources• Programmale serial c"annel

• Low power idle power4down modes

=-3 AT /6C*1

T"e system re8uirements and control specifications clearly rule out t"e use of 1=7 32 or

=, it micro controllers or microprocessors5 Systems using t"ese may e earlier to implement

due to large numer of internal features5 T"ey are also faster and more reliale ut7 04it microcontroller satisfactorily seres t"e aoe application5 6sing an ine'pensie 04it %icrocontroller

will doom t"e 324it product failure in any competitie mar(et place5

Coming to t"e 8uestion of w"y to use AT0-C1 of all t"e 04it microcontroller aailale

in t"e mar(et t"e main answer would e ecause it "as , . on c"ip flas" memory w"ic" is /ust

sufficient for our application5 T"e on4c"ip #las" R&% allows t"e program memory to e

reprogrammed in system or y conentional non4olatile memory Programmer5 %oreoer

AT%EL is t"e leader in flas" tec"nology in todayJs mar(et place and "ence using AT 0-C1 ist"e optimal solution5

AT/6C*1 MICROCONTROLLER ARC0ITECTURE

T"e 0-C1 arc"itecture consists of t"ese specific featuresH

• Eig"t Mit CP6 wit" registers A 9t"e accumulator: and B

22



• Si'teen4it program counter 9PC: and data pointer 9$PTR:

• Eig"t4 it stac( pointer 9PS):

• Eig"t4it stac( pointer 9Sp:

•

@nternal R&% or EPR&% 901: of *90*31: to ,. 90-C1:• @nternal RA% of 120 ytesH

15 #our register an(s7 eac" containing eig"t registers

25 Si'teen ytes7 w"ic" maye addressed at t"e it leel

35 Eig"ty ytes of general4 purpose data memory

• T"irty Mtwo inputoutput pins arranged as four 04it portsHp*4p3

• Two 1=4it timercountersH T* and T1

• #ull duple' serial data receiertransmitterH SB6#

• Control registersH TC&!7 T%&$7 SC&!7 PC&!7 @P7 and @E

• Two e'ternal and t"ree internal interrupts sources5

• &scillator and cloc( circuits5

23



#ig H #unctional loc( diagram of micro controller

T-e /6C*1 os#i""ator an% #"o#(@

T"e "eart of t"e 0-C1 circuitry t"at generates t"e cloc( pulses y w"ic" all t"e internal

all internal operations are sync"ronied5 Pins <TAL1 And <TAL2 is proided for connecting a

resonant networ( to form an oscillator5 Typically a 8uart crystal and capacitors are employed5

T"e crystal fre8uency is t"e asic internal cloc( fre8uency of t"e microcontroller5 T"e

manufacturers ma(e 0-C1 designs t"at run at specific minimum and ma'imum fre8uencies

typically 1 to 1= %+5

4 &scillator and timing circuit

T3+es o8 )e)or3@

T"e 0-C1 "ae t"ree general types of memory5 T"ey are on4c"ip memory7 e'ternal Code

memory and e'ternal Ram5 &n4C"ip memory refers to p"ysically e'isting memory on t"e micro

2,



controller itself5 E'ternal code memory is t"e code memory t"at resides off c"ip5 T"is is often in

t"e form of an e'ternal EPR&%5 E'ternal RA% is t"e Ram t"at resides off c"ip5 T"is often is in

t"e form of standard static RA% or flas" RA%5

a< Co%e )e)or3

Code memory is t"e memory t"at "olds t"e actual 0-C1 programs t"at is to e run5 T"is

memory is limited to =,.5 Code memory may e found on4c"ip or off4c"ip5 @t is possile to "ae

,. of code memory on4c"ip and =*. off c"ip memory simultaneously5 @f only off4c"ip memory

is aailale t"en t"ere can e =,. of off c"ip R&%5 T"is is controlled y pin proided as EA

b< Interna" RAM

T"e 0-C1 "ae a an( of 120 of internal RA%5 T"e internal RA% is found on4c"ip5 So

it is t"e fastest Ram aailale5 And also it is most fle'ile in terms of reading and writing5

@nternal Ram is olatile7 so w"en 0-C1 is reset7 t"is memory is cleared5 120 ytes of internalmemory are sudiided5 T"e first 32 ytes are diided into , register an(s5 Eac" an( contains

0 registers5 @nternal RA% also contains 120 its7 w"ic" are addressed from 2*" to 2#"5 T"ese

its are it addressed i5e5 eac" indiidual it of a yte can e addressed y t"e user5 T"ey are

numered **" to #"5 T"e user may ma(e use of t"ese ariales wit" commands suc" as SETB

and CLR5

FLAS0 MEMORY@

#las" memory 9sometimes called Fflas" RA%G: is a type of constantly4powered non

olatile t"at can e erased and reprogrammed in units of memory called blocks5 @t is a ariation

of electrically erasale programmale read4only memory 9EEPR&%: w"ic"7 unli(e flas"

memory7 is erased and rewritten at t"e yte leel7 w"ic" is slower t"an flas" memory updating5

#las" memory is often used to "old control code suc" as t"e asic inputoutput system 9B@&S: in

a personal computer5 )"en B@&S needs to e c"anged 9rewritten:7 t"e flas" memory can e

written to in loc( 9rat"er t"an yte: sies7 ma(ing it easy to update5 &n t"e ot"er "and7 flas"

memory is not useful as random access memory 9RA%: ecause RA% needs to e addressale

at t"e yte 9not t"e loc(: leel5

#las" memory gets its name ecause t"e microc"ip is organied so t"at a section of

memory cells are erased in a single action or Fflas"5G T"e erasure is caused y #owler4!ord"eim

tunneling in w"ic" electrons pierce t"roug" a t"in dielectric material to remoe an electronic

c"arge from a floating gate associated wit" eac" memory cell5 @ntel offers a form of flas"

2



memory t"at "olds two its 9rat"er t"an one: in eac" memory cell7 t"us douling t"e capacity of

memory wit"out a corresponding increase in price5

#las" memory is used in digital cellular p"ones7 digital cameras7 LA! switc"es7 PC

Cards for noteoo( computers7 digital set4up o'es7 emedded controllers7 and ot"er deices5

Me)or3 T3+e Feat!res

FLAS0 Low4cost7 "ig"4density7 "ig"4speed

arc"itectureI low powerI "ig" reliailityROM

Read4&nly %emory

%ature7 "ig"4density7 reliale7 low costI

time4consuming mas( re8uired7 suitale

for "ig" production wit" stale codeSRAM

Static Random4Access %emory

+ig"est speed7 "ig"4power7 low4density

memoryI limited density dries up costEROM

Electrically Programmale Read4&nly

%emory

+ig"4density memoryI must e e'posed

to ultraiolet lig"t for erasure

EEROMorE2ROM

Electrically Erasale Programmale

Read4&nly %emory

Electrically yte4erasaleI lower

reliaility7 "ig"er cost7 lowest density

DRAM $ynamic Random Access %emory

+ig"4density7 low4cost7 "ig"4speed7"ig"4power

Te#-ni#a" Overvie o8 F"as- Me)or3

#las" memory is a nonolatile memory using !&R tec"nology7 w"ic" allows t"e user to

electrically program and erase information5 @ntelW #las" memory uses memory cells similar to

an EPR&%7 ut wit" a muc" t"inner7 precisely grown o'ide etween t"e floating gate and t"e

source 5 #las" programming occurs w"en electrons are placed on t"e floating gate5 T"e c"arge is

stored on t"e floating gate7 wit" t"e o'ide layer allowing t"e cell to e electrically erased t"roug"

t"e source5 @ntel #las" memory is an e'tremely reliale nonolatile memory arc"itecture5

2=



#ig 0H Pin diagram of AT0-C1

in Des#ri+tion@

CC@ Supply oltage5

GND@ Xround5

ort 7@

Port * is an 04it open4drain i4directional @& port5 As an output port7 eac" pin can sin(

eig"t TTL inputs5 )"en oneJs are written to port * pins7 t"e pins can e used as "ig" impedance

inputs5 Port * may also e configured to e t"e multiple'ed low order addressdata us during

accesses to e'ternal program and data memory5 @n t"is mode P* "as internal pull4ups5 Port * alsoreceies t"e code ytes during #las" programming7 and outputs t"e code ytes during program

erification5 E'ternal pull4ups are re8uired during program erification5

ort 1@

Port 1 is an 04it i4directional @& port wit" internal pull4ups5 T"e Port 1 output uffers

can sin(source four TTL inputs5 )"en 1s are written to Port 1 pins t"ey are pulled "ig" y t"e

2



internal pull4ups and can e used as inputs5 As inputs7 Port 1 pins t"at are e'ternally eing pulled

low will source current 9@@L: ecause of t"e internal pull4ups5 Port 1 also receies t"e low4order

address ytes during #las" programming and erification5

ort 2@




low will source current 9@@L: ecause of t"e internal pull4ups5 Port 2 emits t"e "ig"4order address

yte during fetc"es from e'ternal program memory and during accesses to e'ternal data

memories t"at use 1=4it addresses 9%&< Y$PTR:5 @n t"is application7 it uses strong internal

pull4ups w"en emitting 1s5 $uring accesses to e'ternal data memories t"at use 04it addresses9%&< Y R@:7 Port 2 emits t"e contents of t"e P2 Special #unction Register5 Port 2 also

receies t"e "ig"4order address its and some control signals during #las" programming and

erification5

ort $@




low will source current 9@@L: ecause of t"e pull4ups5

Port 3 also seres t"e functions of arious special features of t"e AT0-C1 as listed elowH

Port 3 also receies some control signals for #las" programming and erification

20



Ta =5251 Port pins and t"eir alternate functionsRST@

Reset input5 A "ig" on t"is pin for two mac"ine cycles w"ile t"e oscillator is running

resets t"e deice5

ALE>ROG@

Address Latc" Enale output pulse for latc"ing t"e low yte of t"e address during

accesses to e'ternal memory5 T"is pin is also t"e program pulse input 9PR&X: during #las"

programming5 @n normal operation ALE is emitted at a constant rate of 1=t"e oscillator

fre8uency7 and may e used for e'ternal timing or cloc(ing purposes5 !ote7 "oweer7 t"at one

ALE pulse is s(ipped during eac" access to e'ternal $ata %emory5

@f desired7 ALE operation can e disaled y setting it * of S#R location 0E+5 )it" t"e it set7

ALE is actie only during a %&< or %&C instruction5 &t"erwise7 t"e pin is pulled "ig"5

Setting t"e ALE4disale it "as no effect if t"e microcontroller is in e'ternal e'ecution mode5

SEN@

Program Store Enale is t"e read stroe to e'ternal program memory5 )"en t"e AT0-C1

is e'ecuting code from e'ternal program memory7 PSE! is actiated twice eac" mac"ine cycle7

e'cept t"at two PSE! actiations are s(ipped during eac" access to e'ternal data memory5

EA>@

2-



E'ternal Access Enale EA must e strapped to X!$ in order to enale t"e deice to

fetc" code from e'ternal program memory locations starting at ****+ up to ####+5

!ote7 "oweer7 t"at if loc( it 1 is programmed7 EA will e internally latc"ed on reset5

EA s"ould e strapped to CC for internal program e'ecutions5 T"is pin also receies t"e 124

olt programming enale oltage 9PP: during #las" programming7 for parts t"at re8uire 124olt

PP5

XTAL1@

@nput to t"e inerting oscillator amplifier and input to t"e internal cloc( operating circuit5

XTAL2@

@t is t"e &utput from t"e inerting oscillator amplifier5

Os#i""ator C-ara#teristi#s@

<TAL1 and <TAL2 are t"e input and output7 respectiely7 of an inerting amplifier

w"ic" can e configured for use as an on4c"ip oscillator7 as s"own in #igs -5 Eit"er a 8uart

crystal or ceramic resonator may e used5 To drie t"e deice from an e'ternal cloc( source7

<TAL2 s"ould e left unconnected w"ile <TAL1 is drien as s"own in #igure 1*5T"ere are no

re8uirements on t"e duty cycle of t"e e'ternal cloc( signal7 since t"e input to t"e internal

cloc(ing circuitry is t"roug" a diide4y4two flip4flop7 ut minimum and ma'imum oltage "ig"

and low time specifications must e osered5

#ig - &scillator Connections

3*



#ig 1* E'ternal Cloc( $rie Configuration

NotesH2 6nder steady state 9non4transient: conditions7 @&L must e e'ternally

limited as followsH

• %a'imum @&L per port pin H 1* mA

• %a'imum @&L per 04it port H Port * H 2= mA

• Ports 17 27 3H 1 mA

• %a'imum total @&L for all output pinsH 1 mA

• @f @&L e'ceeds t"e test condition7 &L may e'ceed t"e related specification5 Pins are

not guaranteed to sin( current greater t"an t"e listed test conditions5

2. %inimum CC for Power4down is 25

REGISTERS@

@n t"e CP67 registers are used to store information temporarily5 T"at information could

e a yte of data to e processed7 or an address pointing to t"e data to e fetc"ed5 T"e ast

ma/ority of 0*1 registers are 0Mit registers5 @n t"e 0*1 t"ere is only one data typeH 0its5 T"e0its of a register are s"own in t"e diagram from t"e %SB 9most significant it: $ to t"e LSB

9least significant it: $*5 )it" an 04it data type7 any data larger t"an 0its must e ro(en into

04it c"un(s efore it is processed5 Since t"ere are a large numer of registers in t"e 0*17 we

31



will concentrate on some of t"e widely used general4purpose registers and coer special registers

in future c"apters5

$ $= $ $, $3 $2 $1 $*

T"e most widely used registers of t"e 0*1 are A 9accumulator:7 B7 R*7 R17 R27 R37 R,7

R7 R=7 R7 $PTR 9data pointer:7 and PC 9program counter:5 All of t"e aoe registers are 04

its7 e'cept $PTR and t"e program counter5 T"e accumulator7 register A7 is used for all

arit"metic and logic instructions5

SFRs ;S+e#ia" F!n#tion Reisters<

Among t"e registers R*4R is part of t"e 120 ytes of RA% memory5 )"at aout

registers A7 B7 PS)7 and $PTRZ $o t"ey also "ae addressesZ T"e answer is yes5 @n t"e 0*17registers A7 B7 PS) and $PTR are part of t"e group of registers commonly referred to as S#R

9special function registers:5 T"ere are many special function registers and t"ey are widely used5

T"e S#R can e accessed y t"e names 9w"ic" is muc" easier: or y t"eir addresses5 #or

e'ample7 register A "as address E*"7 and register B "as een ignited t"e address #*+7 as s"own

in tale5

T"e following two points s"ould noted aout t"e S#R addresses5

15 T"e Special function registers "ae addresses etween 0*+ and ##+5 T"ese

addresses are aoe 0*+7 since t"e addresses ** to #+ are addresses of RA%

memory inside t"e 0*15

25 !ot all t"e address space of 0*+ to ##+ is used y t"e S#R5 T"e unused locations

0*+ to ##+ are resered and must not e used y t"e 0*1 programmer5

Regarding direct addressing mode7 notice t"e following two pointsH 9a: t"e address alue

is limited to one yte7 **4##+7 w"ic" means t"is addressing mode is limited to accessing RA%

locations and registers located inside t"e 0*15 9: @f you e'amine t"e l st file for an assemly

language program7 you will see t"at t"e S#R registers names are replaced wit" t"eir addresses as

listed in tale5

S3)bo" Na)e A%%ress

32



ACC Accumulator *E*+B B register *#*+PS) Program status word *$*+SP Stac( pointer 01+$PTR $ata pointer 2 ytes

$PL Low yte 02+$P+ +ig" yte 03+P* Port* 0*+P1 Port1 -*+P2 Port2 *A*+P3 Port3 *B*+@P @nterrupt priority control *B0+@E @nterrupt enale control *A0+T%&$ Timercounter mode control 0-+TC&! Timercounter control 00+T2C&! Timercounter 2 control *C0+

T2%&$ Timercounter mode2 control *C-+T+* Timercounter *"ig" yte 0C+TL* Timercounter * low yte 0A+T+1 Timercounter 1 "ig" yte 0$+TL1 Timercounter 1 low yte 0B+T+2 Timercounter 2 "ig" yte *C$+TL2 Timercounter 2 low yte *CC+RCAP2+ TC 2 capture register "ig" yte *CB+RCAP2L TC 2 capture register low yte *CA+SC&! Serial control -0+SB6# Serial data uffer --+PC&! Power control 0+

Tab"e@ /7*1 S+e#ia" 8!n#tion reister A%%ress

A Reister ;A##!)!"ator<

#ig 11H Accumulator register

T"is is a general4purpose register w"ic" seres for storing intermediate results during operating5

A numer 9an operand: s"ould e added to t"e accumulator prior to e'ecute an instruction upon

33



it5 &nce an arit"metical operation is preformed y t"e AL67 t"e result is placed into t"e

accumulator5 @f a data s"ould e transferred from one register to anot"er7 it must go t"roug"

accumulator5 #or suc" uniersal purpose7 t"is is t"e most commonly used register t"at none

microcontroller can e imagined wit"out 9more t"an a "alf 0*1 microcontrollerJs instructions

used use t"e accumulator in some way:5

' Reister

B register is used during multiply and diide operations w"ic" can e performed only upon

numers stored in t"e A and B registers5 All ot"er instructions in t"e program can use t"is register

as a spare accumulator 9A:5

#ig 12H B register

$uring programming7 eac" of registers is called y name so t"at t"eir e'act address is not

so important for t"e user5 $uring compiling into mac"ine code 9series of "e'adecimal numers

recognied as instructions y t"e microcontroller:7 PC will automatically7 instead of registersJ

name7 write necessary addresses into t"e microcontroller5

R Reisters ;R7BR<

3,



#ig 13HRA%

T"is is a common name for t"e total 0 general purpose registers 9R*7 R17 and R2 555R:5

Een t"ey are not true S#Rs7 t"ey desere to e discussed "ere ecause of t"eir purpose5 T"e

an( is actie w"en t"e R registers it includes are in use5 Similar to t"e accumulator7 t"ey are

used for temporary storing ariales and intermediate results5 )"ic" of t"e an(s will e actie

depends on two its included in t"e PS) Register5 T"ese registers are stored in four an(s in t"e

scope of RA%5

T"e following e'ample est illustrates t"e useful purpose of t"ese registers5 Suppose t"at

mat"ematical operations on numers preiously stored in t"e R registers s"ould e performedH

9R1R2: M 9R3R,:5 &iously7 a register for temporary storing results of addition is needed5

Eeryt"ing is 8uite simple and t"e program is as followsH

MO A R$ %eansH moe numer from R3 into accumulator

ADD A R& %eansH add numer from R, to accumulator 9result remains in accumulator:

MO R* A %eansH temporarily moes t"e result from accumulator into R

MO A R1 %eansH moe numer from R1 into accumulator

ADD A R2 %eansH add numer from R2 to accumulator

SU'' A R* %eansH sutract numer from R 9t"ere are R3R,:

3



/7*1 Reister 'an(s an% Sta#(

RAM )e)or3 s+a#e a""o#ation in t-e /7*1

T"ere are 120 ytes of RA% in t"e 0*15 T"e 120 ytes of RA% inside t"e 0*1 areassigned addresses ** to#+5 T"ese 120 ytes are diided into t"ree different groups as followsH

15 A total of 32 ytes from locations ** to 1#+ "e' are set aside for register an(s and

t"e stac(5

25 A total of 1= ytes from locations 2* to 2#+ "e' are set aside for it4addressale

readwrite memory5

35 A total of 0* ytes from locations 3*+ to #+ are used for read and write storage7 or

w"at is normally called Scratc" pad5 T"ese 0* locations of RA% are widely used for

t"e purpose of storing data and parameters nu 0*1 programmers5

Reister ban(s in t-e /7*1

A total of 32ytes of RA% are set aside for t"e register an(s and stac(5 T"ese 32

ytes are diided into , an(s of registers in w"ic" eac" an( "as registers7 R*4R5 RA%

locations * to are set aside for an( * of R*4R w"ere R* is RA% location *7 R1 is RA%

location 17 and R2 is location 27 and so on7 until memory location7 w"ic" elongs to R of

an(*5 T"e second an( of registers R*4R starts at RA% location *0 and goes to location *#+5T"e t"ird an( of R*4R starts at memory location 1*+ and goes to location 1+5 #inally7 RA%

locations 10+ to 1#+ are set aside for t"e fourt" an( of R*4R5 #ig s"ows "ow t"e 32 ytes are

allocated into , an(s5

As we can see from fig 17 t"e an( 1 uses t"e same RA% space as t"e stac(5 T"is is a

ma/or prolem in programming t"e 0*15 )e must eit"er not use register an(17 or allocate

anot"er area of RA% for t"e stac(5

De8a!"t reister ban(

@f RA% locations **41# are set aside for t"e four register an(s7 w"ic" register an( of

R*4R do we "ae access to w"en t"e 0*1 is powered upZ T"e answer is register an( *I t"at

is 7 RA% locations *7 172737,77=7 and are accessed wit" t"e names R*7 R17 R27 R37 R,7 R7 R=7

and R w"en programming t"e 0*15 @t is muc" easier to refer to t"ese RA% locations wit"

3=



names suc" as R*7 R1 and so on7 t"an y t"eir memory locations as s"own in fig 25T"e register

an(s are switc"ed y using t"e $3 $, its of register PS)5

#@X1, H RA% Allocation in t"e 0*1

3



#ig 1H 0*1 Register Ban(s and t"eir RA% Addresses

S= Reister ;rora) Stat!s =or%<

#ig 1=H PS) register

T"is is one of t"e most important S#Rs5 T"e Program Status )ord 9PS): contains

seeral status its t"at reflect t"e current state of t"e CP65 T"is register containsH Carry it7

Au'iliary Carry7 two register an( select its7 &erflow flag7 parity it7 and user4definale status

flag5 T"e AL6 automatically c"anges some of registerJs its7 w"ic" is usually used in regulation

of t"e program performing5

H arit3 bit @f a numer in accumulator is een t"en t"is it will e automatically set 91:7

ot"erwise it will e cleared 9*:5 @t is mainly used during data transmission and receiing ia

serial communication5

B 'it 1. T"is it is intended for t"e future ersions of t"e microcontrollers7 so it is not supposed to

e "ere5

O Over8"o occurs w"en t"e result of arit"metical operation is greater t"an 2 9decimal:7 so

t"at it can not e stored in one register5 @n t"at case7 t"is it will e set 91:5 @f t"ere is no oerflow7

t"is it will e cleared 9*:5

RS7 RS1 H Reister ban( se"e#ts bits. T"ese two its are used to select one of t"e four register

an(s in RA%5 By writing eroes and ones to t"ese its7 a group of registers R*4R is stored in

one of four an(s in RA%5

RS1 RS2 S+a#e in RAM

* * Ban(* **"4*"

30



* 1 Ban(1 *0"4*#"

1 * Ban(2 1*"41"

1 1 Ban(3 10"41#"

F7 H F"a 7. T"is is a general4purpose it aailale to t"e user5

AC H A!i"iar3 Carr3 F"a is used for BC$ operations only5

CY H Carr3 F"a is t"e 9nint": au'iliary it used for all arit"metical operations and s"ift

instructions5

DTR Reister ;Data ointer<

T"ese registers are not true ones ecause t"ey do not p"ysically e'ist5 T"ey consist of

two separate registersH $P+ 9$ata Pointer +ig": and 9$ata Pointer Low:5 T"eir 1= its are used

for e'ternal memory addressing5 T"ey may e "andled as a 1=4it register or as two independent

04it registers5 Besides7 t"e $PTR Register is usually used for storing data and intermediate

results w"ic" "ae not"ing to do wit" memory locations5

#ig 1H $PTR register

S Reister ;Sta#( ointer<

3-



#ig 10H SP register

T"e stac( is a section of RA% used y t"e CP6 to store information temporarily5 T"is

information could e data or an address5 T"e CP6 needs t"is storage area since t"ere are only a

limited numer of registers5

0o sta#(s are a##esse% in t-e /7*1

@f t"e stac( is a section of RA%7 t"ere must e registers inside t"e CP6 to point to it5

T"e register used to access t"e stac( is called t"e SP 9Stac( point: Register5 T"e stac( pointer in

t"e 0*1 is only 0 its wideI w"ic" means t"at it can ta(e alues of ** to ##+5 )"en t"e 0*1 is

powered up7 t"e SP register contains alue *5 T"is means t"at RA% location *0 is t"e first

location used for t"e stac( y t"e 0*15 T"e storing of a CP6 register in t"e stac( is called a

P6S+7 and pulling t"e contents off t"e stac( ac( into a CP6 register is called a P&P5 @n ot"er

words7 a register is pus"ed onto t"e stac( to sae it and popped off t"e stac( to retriee it5 T"e /o of t"e SP is ery critical w"en pus" and pop actions are performed5

!s-in onto t-e sta#(

@n t"e 0*1 t"e stac( pointer 9SP: points to t"e last used location of t"e stac(5 As we

pus" data onto t"e stac(7 t"e stac( pointer is incremented y one5 !otice t"at t"is different from

many microprocessors7 notaly '0= processors in w"ic" t"e SP is decremented w"en data is

pus"ed onto t"e stac(5 As eac" P6S+ is e'ecuted7 t"e contents of t"e register are saed on t"estac( and SP is incremented y 15 !otice t"at for eery yte of data saed on t"e stac( and t"en

SP is incremented only once5 !otice also t"at to pus" t"e registers onto t"e stac( we must use

t"eir RA% addresses5 #or e'ample7 t"e instruction FP6S+G pus"es register R1 onto t"e stac(5

o++in 8ro) t-e sta#(

,*



Popping t"e contents of t"e stac( ac( into a gien register is t"e opposite process of

pus"ing5 )it" eery pop7 t"e top yte of t"e stac( is copied to t"e register specified y t"e

instruction and t"e stac( pointer is decremented once5

T-e !++er "i)it o8 t-e sta#(

As7 mentioned earlier7 locations *0 to 1#+ in t"e 0*1 RA% can e used for t"e stac(5

T"is is ecause locations 2*42#+ of RA% are resered for it4addressale memory and must not

e used y t"e stac(5 @f in a program we need more t"an 2, ytes 9*0 to 1#+K2,ytes: of stac(7

we can c"ange t"e SP to point to RA% locations 3*4#+5 T"is is done wit" t"e instruction

F%& SP7 [<<G5

7 1 2 $ H In+!t>O!t+!t Reisters

#ig 1-H P&RT* @& register

@n case t"at e'ternal memory and serial communication system are not in use t"en7 ,

ports wit" in total of 32 input4output lines are aailale to t"e user for connection to perip"eralenironment5 Eac" it inside t"ese ports corresponds to t"e appropriate pin on t"e

microcontroller5 T"is means t"at logic state written to t"ese ports appears as a oltage on t"e pin

9* or :5 !aturally7 w"ile reading7 t"e opposite occurs M oltage on some input pins is reflected

in t"e appropriate port it5

T"e state of a port it7 esides eing reflected in t"e pin7 determines at t"e same time

w"et"er it will e configured as input or output5 @f a it is cleared 9*:7 t"e pin will e configured

as output5 @n t"e same manner7 if a it is set to 1 t"e pin will e configured as input5 After reset7

as well as w"en turning t"e microcontroller &!7 all its on t"ese ports are set to one ;1<5 T"is

means t"at t"e appropriate pins will e configured as in+!ts5

rora) #o!nterH

,1



T"e important register in t"e 0*1 is t"e PC 9Program counter:5 T"e program counter

points to t"e address of t"e ne't instruction to e e'ecuted5 As t"e CP6 fetc"es t"e &PC&$E

from t"e program R&%7 t"e program counter is incremented to point to t"e ne't instruction5 T"e

program counter in t"e 0*1 is 1=its wide5 T"is means t"at t"e 0*1 can access program

addresses **** to ####+7 a total of =,( ytes of code5 +oweer7 not all memers of t"e 0*1

"ae t"e entire =,. ytes of on4c"ip R&% installed7 as we will see soon5

T3+es o8 instr!#tions

$epending on operation t"ey perform7 all instructions are diided in seeral groupsH

• Arit"metic @nstructions

• Branc" @nstructions• $ata Transfer @nstructions

• Logical @nstructions

• Logical @nstructions wit" its

T"e first part of eac" instruction7 called %!E%&!@C refers to t"e operation an instruction

performs 9copying7 addition7 logical operation etc5:5 %nemonics commonly are s"ortened form

of name of operation eing e'ecuted5 #or e'ampleH

INC R1I @ncrement R1 9increment register R1:

LJMP LAB5 ILong \ump LAB 9long /ump to address specified as LAB:

JNZ LOOP I\ump if !ot ero L&&P 9if t"e numer in t"e accumulator is not *7 /ump to address

specified as L&&P:

Anot"er part of instruction7 called &PERA!$ is separated from mnemonic at least y

one empty space and defines data eing processed y instructions5 Some instructions "ae no

operandI some "ae one7 two or t"ree5 @f t"ere is more t"an one operand in instruction7 t"ey are

separated y comma5 #or e'ampleH

RET M 9return from su4routine:

,2



JZ TEMP M 9if t"e numer in t"e accumulator is not *7 /ump to address specified as TE%P:

ADD A,R3 M 9add R3 and accumulator:

CJNE A,#20,LOOP M 9compare accumulator wit" 2*5 @f t"ey are not e8ual7 /ump to address

specified as L&&P:

Arit-)eti# instr!#tions

T"ese instructions perform seeral asic operations 9addition7 sutraction7 diision7

multiplication etc5: After e'ecution7 t"e result is stored in t"e first operand5 #or e'ampleH

ADD A, R1 M T"e result of addition 9AR1: will e stored in t"e accumulator5

Arit-)eti#a" Instr!#tions

Mne)oni# Des#ri+tion'3te

N!)ber

Os#i""ator

erio%

A$$ A7Rn Add R Register to accumulator 1 1

A$$ A7R'Add directly addressed R' Register to

accumulator 2 2

A$$ A7YRiAdd indirectly addressed Register to

accumulator 1 1

A$$ A7[< Add numer < to accumulator 2 2

A$$C A7Rn Add R Register wit" Carry it to accumulator 1 1

'ran#- Instr!#tions

T"ere are two (inds of t"ese instructionsH

Un#on%itiona" !)+ instr!#tions@

After t"eir e'ecution a /ump to a new location from w"ere t"e program continues

e'ecution is e'ecuted5

,3



Con%itiona" !)+ instr!#tions@

@f some condition is met M a /ump is e'ecuted5 &t"erwise7 t"e program normally

proceeds wit" t"e ne't instruction5

'ran#- Instr!#tion


N!)ber

Os#i""ator

erio%

ACALL

adr11

Call suroutine located at address wit"in 2 . yte

Program %emory space2 3

LCALL adr1=Call suroutine located at any address wit"in =, .

yte Program %emory space3 ,

RET Return from suroutine 1 ,

RET@ Return from interrupt routine 1 ,

A\%P adr11\ump to address located wit"in 2 . yte Program

%emory space2 3

L\%P adr1=\ump to any address located wit"in =, . yte

Program %emory space3 ,

Data Trans8er Instr!#tions

T"ese instructions moe t"e content of one register to anot"er one5 T"e register w"ic"

content is moed remains unc"anged5 @f t"ey "ae t"e suffi' F<G 9%&<:7 t"e data is

e'c"anged wit" e'ternal memory5

Data Trans8er Instr!#tion


N!)ber

C3#"e

N!)ber

%& A7Rn %oe R register to accumulator 1 1

%& A7R'%oe directly addressed R' register to

accumulator 2 2

%& A7YRi %oe indirectly addressed register to 1 1

,,



accumulator

%& A7[< %oe numer < to accumulator 2 2

Loi#a" Instr!#tions

T"ese instructions perform logical operations etween corresponding its of two

registers5 After e'ecution7 t"e result is stored in t"e first operand5

Loi#a" Instr!#tions


N!)ber

C3#"e

N!)ber

A!L A7Rn Logical A!$ etween accumulator and R register 1 1

A!L A7R'Logical A!$ etween accumulator and directly

addressed register R'2 2

A!L A7YRiLogical A!$ etween accumulator and indirectly

addressed register 1 1

A!L A7[< Logical A!$ etween accumulator and numer < 2 2

Loi#a" O+erations on 'its

Similar to logical instructions7 t"ese instructions perform logical operations5 T"e

difference is t"at t"ese operations are performed on single its5

Loi#a" o+erations on bits


N!)ber

C3#"e

N!)ber

CLR C Clear Carry it 1 1

CLR it Clear directly addressed it 2 2SETB C Set Carry it 1 1

SETB it Set directly addressed it 2 2

CPL C Complement Carry it 1 1

CPL it Complement directly addressed it 2 2

,



TIMERS

&n4c"ip timingcounting facility "as proed t"e capailities of t"e microcontroller for

implementing t"e real time application5 T"ese includes pulse counting7 fre8uency measurement7

pulse widt" measurement7 aud rate generation7 etc75 +aing sufficient numer of timercounters

may e a need in a certain design application5 T"e 0*1 "as two timerscounters5 T"ey can e

used eit"er as timers to generate a time delay or as counters to count eents "appening outside

t"e microcontroller5 Let discuss "ow t"ese timers are used to generate time delays and we will

also discuss "ow t"ey are een used as eent counters5

ROGRAMMING /7*1 TIMERS

T"e 0*1 "as timersH Timer * and Timer15t"ey can e used eit"er as timers or as eent

counters5 Let us first discuss aout t"e timersJ registers and "ow to program t"e timers to

generate time delays5

'ASIC RIGISTERS OF T0E TIMER

Bot" Timer * and Timer 1 are 1= its wide5 Since t"e 0*1 "as an 04it arc"itecture7 eac"

1=4it timer is accessed as two separate registers of low yte and "ig" yte5

TIMER 7 REGISTERS

T"e 1=4it register of Timer * is accessed as low yte and "ig" yte5 T"e low yte

register is called TL*9Timer * low yte:and t"e "ig" yte register is referred to as T+*9Timer *

"ig" yte:5T"ese register can e accessed li(e any ot"er register7 suc" as A7B7R*7R17R27etc5for

e'ample7 t"e instruction G%& TL*7 [,#Gmoes t"e alue ,#+ into TL*7t"e low yte of Timer

*5T"ese registers can also e read li(e any ot"er register5

#ig 2*HTimer *9T+* and TL* : registers

,=



TIMER 1 REGISTERS

Timer 1 is also 1=4it register is split into two ytes7 referred to as TL1 9Timer 1 low

yte: and T+1 9Timer 1 "ig" yte:5t"ese registers are accessile n t"e same way as t"e register of

Timer *5

TMOD ;ti)er )o%e< REGISTER

Bot" timers T@%ER * and T@%ER 1 use t"e same register7 called T%&$7 to set t"e

arious timer operation modes5 T%&$ is an 04it register in w"ic" t"e lower , its are set aside

for Timer * and t"e upper , its for Timer 15in eac" caseI t"e lower 2 its are used to set t"e

timer mode and t"e upper 2 its to specify t"e operation5

MODES@

M1 M7@

%* and %1 are used to select t"e timer mode5 T"ere are t"ree modesH *7 17 25%ode * is

a 134it timer7 mode 1 is a 1=4it timer7 and mode 2 is an 04it timer5 )e will concentrate on

modes 1 and 2 since t"ey are t"e ones used most widely5 )e will soon descrie t"ec"aracteristics of t"ese modes7 after descriing t"e reset of t"e T%&$ register5

GATE@ Xate control w"en set5 T"e timercounter is enaled only

)"ile t"e @!T' pin is "ig" and t"e TR' control pin is5

Set5 )"en cleared7 t"e timer is enaled5

C>T Timer or counter selected cleared for timer operation

9@nput from internal system cloc(:5set for counter

&peration 9input T< input pin:5

M 1 %ode it 1

M7 %ode it *

M1 M7 MODE O+eratin Mo%e

,



* 7 7 134it timer mode

04it timercounter T+' wit"

TL' as M Bit pre4scaler5

7 1 1 1=4it timer mode

1=4it timercounters T+'

wit" TL' are CascadedI t"ere

is no prescaler 1 * 2 04it auto reload

04it auto reload

timercounterIT+' +olds a

alue t"at is to e reloaded

into TL' eac" time itoerflows5

1 1 $ Split timer mode5

C>T ;#"o#(>ti)er<

T"is it in t"e T%&$ register is used to decide w"et"er t"e timer is used as a delay

generator or an eent counter5 @f CTK*7 it is used as a timer for time delay generation5 T"e cloc(

source for t"e time delay is t"e crystal fre8uency of t"e 0*15t"is section is concerned wit" t"isc"oice5 T"e timerJs use as an eent counter is discussed in t"e ne't section5

Seria" Co))!ni#ation@

Computers can transfer data in two waysH parallel and serial5 @n parallel data transfers7

often 0 or more lines 9wire conductors: are used to transfer data to a deice t"at is only a few feet

away5 E'amples of parallel data transfer are printers and "ard dis(sI eac" uses cales wit" many

wire strips5 Alt"oug" in suc" cases a lot of data can e transferred in a s"ort amount of time yusing many wires in parallel7 t"e distance cannot e great5 To transfer to a deice located many

meters away7 t"e serial met"od is used5 @n serial communication7 t"e data is sent one it at a

time7 in contrast to parallel communication7 in w"ic" t"e data is sent a yte or more at a time5

Serial communication of t"e 0*1 is t"e topic of t"is c"apter5 T"e 0*1 "as serial

,0





as t"e numer of signal c"anges per second5 @n modems a single c"ange of signal7 sometimes

transfers seeral its of data5 As far as t"e conductor wire is concerned7 t"e aud rate and ps are

t"e same7 and for t"is reason we use t"e ps and aud interc"angealy5

T"e data transfer rate of gien computer system depends on communication ports

incorporated into t"at system5 #or e'ample7 t"e early @B%PC<T could transfer data at t"e rate

of 1** to -=** ps5 @n recent years7 "oweer7 Pentium ased PCS transfer data at rates as "ig" as

=. ps5 @t must e noted t"at in async"ronous serial data communication7 t"e aud rate is

generally limited to 1**7***ps5

RS2$2 Stan%ar%s

To allow compatiility among data communication e8uipment made y arious

manufacturers7 an interfacing standard called RS232 was set y t"e Electronics @ndustries

Association 9E@A: in 1-=*5 @n 1-=3 it was modified and called RS232A5 RS232B A!$ RS232Cwere issued in 1-= and 1-=-7 respectiely5 Today7 RS232 is t"e most widely used serial @&

interfacing standard5 T"is standard is used in PCs and numerous types of e8uipment5 +oweer7

since t"e standard was set long efore t"e adert of t"e TTL logic family7 its input and output

oltage leels are not TTL compatile5 @n RS2327 a 1 is represented y 43 to 427 w"ile a * it

is 3 to 27 ma(ing 43 to 3 undefined5 #or t"is reason7 to connect any RS232 to a

microcontroller system we must use oltage conerters suc" as %A<232 to conert t"e TTL

logic leels to t"e RS232 oltage leels7 and ice ersa5 %A<232 @C c"ips are commonly

referred to as line driers5

RS2$2 +ins

RS232 cale is commonly referred to as t"e $B42 connector5 @n laeling7 $B42P refers

to t"e plug connector 9male: and $B42S is for t"e soc(et connector 9female:5 Since not all t"e

pins are used in PC cales7 @B% introduced t"e $B4- ersion of t"e serial @& standard7 w"ic"

uses - pins only7 as s"own in tale5

1 2 3 ,

= 0 -

9&ut of computer and e'posed end of cale:

*



#ig 21H $B4- pin connector

Pin #unctionsH

Pin $escription1 $ata carrier detect 9$C$:

2 Receied data 9R<$:3 Transmitted data 9T<$:, $ata terminal ready9$TR: Signal ground 9X!$:= $ata set ready 9$SR: Re8uest to send 9RTS:0 Clear to send 9CTS:- Ring indicator 9R@:

!oteH DCD DSR RTS and CTS are actie low pins5

T"e met"od used y RS4232 for communication allows for a simple connection of t"ree linesHT'7 R'7 and Xround5 T"e t"ree essential signals for 24way RS4232

Communications are t"eseH

TXDH carries data from $TE to t"e $CE5

RXDH carries data from $CE to t"e $TE

SGH signal ground

/7*1 #onne#tion to RS2$2

T"e RS232 standard is not TTL compatileI t"erefore7 it re8uires a line drier suc" as

t"e %A<232 c"ip to conert RS232 oltage leels to TTL leels7 and ice ersa5 T"e

interfacing of 0*1 wit" RS232 connectors ia t"e %A<232 c"ip is t"e main topic5

T"e 0*1 "as two pins t"at are used specifically for transferring and receiing data

serially5 T"ese two pins are called T<$ and R<$ and a part of t"e port 3 group 9P35* and P351:5

Pin 11 of t"e 0*1 is assigned to T<$ and pin 1* is designated as R<$5 T"ese pins are TTL

compatileI t"erefore7 t"ey re8uire a line drier to ma(e t"em RS232 compatile5 &ne suc" line

drier is t"e %A<232 c"ip5

%A<232 conerts from RS232 oltage leels to TTL oltage leels7 and ice ersa5

&ne adantage of t"e %A<232 c"ip is t"at it uses a power source w"ic"7 is t"e same as t"e

source oltage for t"e 0*15 @n t"e ot"er words7 wit" a single power supply we can power

1



ot" t"e 0*1 and %A<2327 wit" no need for t"e power supplies t"at are common in many older

systems5 T"e %A<232 "as two sets of line driers for transferring and receiing data5 T"e line

driers used for T<$ are called T1 and T27 w"ile t"e line driers for R<$ are designated as R1

and R25 @n many applications only one of eac" is used5

#@X 22 HC&!!ECT@!X ]C to PC using %A< 232

INTERRUTS

A single microcontroller can sere seeral deices5 T"ere are two ways to do t"atH

@!TERR6PTS or P&LL@!X5

OLLING@

@n polling t"e microcontroller continuously monitors t"e status of a gien deiceI w"en

t"e status condition is met7 it performs t"e serice 5After t"at7 it moes on to monitor t"e ne't

deice until eac" one is sericed5 Alt"oug" polling can monitor t"e status of seeral deices and

sere eac" of t"em as certain condition are met5

INTERRUTS@

@n t"e interrupts met"od7 w"eneer any deice needs its serice7 t"e deice notifies t"e

microcontroller y sending it an interrupts signal5 6pon receiing an interrupt signal7 t"e

microcontroller interrupts w"ateer it is doing and seres t"e deice5 T"e program associated

wit" t"e interrupts is called t"e interrupt serice routine 9@SR:5or interrupt "andler5

2



INTERRUTS s OLLING@

T"e adantage of interrupts is t"at t"e microcontroller can sere many deices

9not all t"e same time7 of course:I eac" deice can get t"e attention of t"e microcontroller ased

n t"e priority assigned to it5 T"e polling met"od cannot assign priority since it c"ec(s all deices

in round4roin fas"ion5 %ore importantly7 in t"e interrupt met"od t"e microcontroller can also

ignore 9mas(: a deice re8uest for serice5 T"is is again not possile wit" t"e polling met"od5

T"e most important reason t"at t"e interrupt met"od is preferale is t"at t"e polling met"od

wastes muc" of t"e microcontrollerJs time y polling deices t"at do not need serice5 So7 in

order to aoid tying down t"e microcontroller7 interrupts are used5

INTERRUT SERICE ROUTINE

#or eery interrupt7 t"ere must e an interrupt serice routine 9@SR:7 or interrupt

"andler5 )"en an interrupt is ino(ed7 t"e microcontroller runs t"e interrupts serice routine5 #or

eery interrupt7 t"ere is a fi'ed location in memory t"at "olds t"e address of its @SR5 T"e group

of memory location set aside to "old t"e addresses of @SR and is called t"e @nterrupt ector

Tale5 S"own elowH

Interr!+t e#tor Tab"e 8or t-e /7*1@

S.No. INTERRUT ROM LOCATION ;0EX< IN FLAG

CLEARING

15 Reset **** - Auto

25 E'ternal "ardware

@nterrupt *

***3 P352 912: Auto

35 Timers * interrupt9T#*:

***B Auto

,5 E'ternal "ardware **13 P353 913: Auto

3



@nterrupt 19@!T1:

5 Timers 1 interrupt9T#1:

**1B Auto

=5 Serial C&% 9R@

and T@:

**23 Programmer

clears it

Si Interr!+ts in t-e /7*1@

@n reality7 only fie interrupts are aailale to t"e user in t"e 0*17 ut many

manufacturersJ data s"eets state t"at t"ere are si' interrupts since t"ey include reset 5t"e si'

interrupts in t"e 0*1 are allocated as aoe5

15 Reset5 )"en t"e reset pin is actiated7 t"e 0*1 /umps to address location ****5t"is is t"e

power4up reset5

25 Two interrupts are set aside for t"e timersH one for Timer * and one for Timer 15%emory

location ***B+ and **1B+ in t"e interrupt ector tale elong to Timer * and Timer 17

respectiely5

35 Two interrupts are set aside for "ardware e'ternal "arder interrupts5 Pin numer 129P352:

and 139P353: in port 3 are for t"e e'ternal "ardware interrupts @!T* and

@!T17respectiely5T"ese e'ternal interrupts are also referred to as E<1 and E<25%emory

location ***3+ and **13+ in t"e interrupt ector tale are assigned to @!T* and @!T17

respectiely5,5 Serial communication "as a single interrupt t"at elongs to ot" receie and transmit5 T"e

interrupt ector tale location **23+ elongs to t"is interrupt5

!otice t"at a limited numer of ytes are set aside for eac" interrupt5 #or e'ample7 a

total of 0 ytes from location ***3 to ***A is set aside for @!T*7 e'ternal "ardware interrupt

*5similarly7a total of 0 ytes from location **B+ to **12+ is resered for T#*7 Timer * interrupt5

@f t"e serice routine for a gien interrupt is s"ort enoug" to fit in t"e memory space allocated toit7 it is placed in t"e ector taleI ot"erwise7 and an L\%P instruction is placed in t"e ector tale

to point to t"e address of t"e @SR5 @n t"at rest of t"e ytes allocated to t"at interrupt are unused5

#rom t"e aoe tale also notice t"at only t"ree ytes of R&% space are assigned to t"e

reset pin5 T"ey are R&% address location *71 and25address location 3 elongs to e'ternal

,



"ardware interrupt *5for t"is reason7 in our program we put t"e L\%P as t"e first instruction and

redirect t"e processor away from t"e interrupt ector tale7 as s"own elow

Ste+s in ee#!tin an interr!+t

6pon actiation of an interrupt7 t"e microcontroller goes t"roug" t"e following steps5

15 @t finis"es t"e instruction it is e'ecuting and saes t"e address of t"e ne't instruction 9PC:

on t"e stac(5

25 @t also saes t"e current status of all t"e interrupts internally 9i5e57 not on t"e stac(:5

35 @t /umps to a fi'ed location in memory called t"e interrupt ector tale t"at "olds t"e

address of t"e interrupts serice routine5

,5 T"e microcontroller gets t"e address of t"e @SR from t"e interrupt ector tale and /umps

to it5 @t starts to e'ecute t"e interrupt serice suroutine until it reac"es t"e last instructionof t"e suroutine7 w"ic" is RET@ 9return from interrupt:5

5 6pon e'ecuting t"e RET@ instruction7 t"e microcontroller returns to t"e place w"ere it

was interrupted5 #irst7 it gets t"e program counter 9PC: address from t"e stac( y popping

t"e top two ytes of t"e stac( into t"e PC5 T"en it starts to e'ecute from t"at address5

!otice from step t"e critical role of t"e stac(5 #or t"is reason7 we must e careful in

manipulating t"e stac( contents in t"e @SR5 Specifically7 in t"e @SR7 /ust as in any CALL

suroutine7 t"e numer of pus"es and pops must e e8ual5

Enab"in an% %isab"in an interr!+t@

6pon reset7 all interrupt are disaled 9mas(ed:7 meaning t"at none will e responded to

y t"e microcontroller if t"ey are actiated5 T"e interrupt must e enaled y software in order

for t"e microcontroller to respond to t"em5 T"ere is a register called @E 9interrupt enale: t"at is

responsile for enaling 9unmas(ing: and disaling 9mas(ing: t"e interrupts5

!otice t"at @E is a it4addressale register5

Ste+s in enab"in an interr!+t@

To enale an interrupt7 we ta(e t"e following stepsH

15 Bit $ of t"e @E register 9EA: must e set to "ig" to allow t"e reset to ta(e effect5

@f EAK17 interrupts are enaled and will e responded to if t"eir corresponding it in @E are "ig"5

@f EAK*7 no interrupt will e responded to7 een if t"e associated it in t"e @E register is "ig"5

Interr!+t Enab"e Reister



$ $= $ $, $3 $2 $1 $*

EA @E5 disales all interrupts5 @f EAK*7 no interrupts is ac(nowledged5 @f EAK17 eac" interrupt source is indiidually enaled disaled

By setting or clearing its enale it5

44 @E5= !ot implemented7 resered for future use5

ET2 @E5 Enales or disales Timer 2 oerflow or capture interrupt 90*2 &nly:

ES @E5, Enales or disales t"e serial port interrupts5

ET1 @E53 Enales or disales Timers 1 oerflow interrupt

E<1 @E52 Enales or disales e'ternal interrupt 15ET* @E51 Enales or disales Timer * oerflow interrupt5

E<* @E5* Enales or disales e'ternal interrupt5

RFID READER

Actie R#@$ and Passie R#@$ tec"nologies7 w"ile often considered and ealuated

toget"er7 are fundamentally distinct tec"nologies wit" sustantially different capailities5 @n most

cases7 neit"er tec"nology proides a complete solution for supply c"ain asset managementapplications5 Rat"er 7t"e most effectie and complete supply c"ain solutions leerage t"e

adantages of eac" tec"nology and comine t"eir use in complementary ways5 T"is need for ot"

tec"nologies must e considered y R#@$ standards initiaties to effectiely meet t"e

re8uirements of t"e user community5

RFID Rea%er Mo%!"e7 are also called as interrogators5 T"ey conert radio waes

Returned from t"e R#@$ tag into a form t"at can e passed on to Controllers7 w"ic" can

%a(e use of it5 R#@$ tags and readers "ae to e tuned to t"e same fre8uency in order to

Communicate5 R#@$ systems use many different fre8uencies7 ut t"e most common and

)idely used supported y our Reader is 12 .+5

=

EA 44 ET2 ES ET1 E<1 ET* E<*



Functions

15 Supports reading of =, Bit %anc"ester Encoded cards

25 Pins for E'ternal Antenna connection

35 Serial @nterface 9TTL:,5 )iegand @nterface also aailale

5 Customer application on re8uest

Te#-ni#a" Data@

#re8uencyH 12 (+

Read RangeH up to 0 cm

Power supplyH $C 9 ^ V:

Current consumption ma'5 H =* mA

&perating temperatureH 42* 555 =_ C

Storing temperatureH 4,* 555 _ C

@nterfaceH RS232 9TTL:7 )iegand and ot"ers 9on $emand:

$imensions 9l ' w ' ": H 3= ' 10 ' 1* mm

Serial @nterface #ormatH -=**Baud7 !o Parity7 0 $ata its7 1 Stop it

NoteH T"e TTL RS4232 @nterface can not e connected directly to a PC C&% port5

T"erefore t"e signal must e conerted to RS 232 leel for PC connection5

T"is #irmware "as t"e following #unctionsH

Read Tag4@$



Send Tag4@$ in ASC@@ #ormat t"roug" t"e Serial )iegand @nterface5

Se8uence starts wit" Tag @$ follows from Carriage4ReturnLine4#eed 9*$" *A":7

E'ampleH `*,12*1-30CCRbL#bJ

A++"i#ations@

&ur readers can e used for Access control7 Time Attendance7 ending mac"ines7

@ndustrial and ot"er applications w"ere Reading t"e data from t"e Card only is re8uired5

RFID 125 Reader Module Pin Diagram & Description

IN NO. SIGNAL DESCRITION

Pin !o H = T'$ Transmit data 9TTL leel: output from module to serial

0



interfacePin !o H , )iegand $ATA +@X+

9 aailale in )iegand :

@t will gie $ATA +@X+ signal5

Pin !o H 0 R'$ Receie data 9TTL leel: input to t"e module from

serial interfacePin !o H 12 Buer 9actie low: Buer will u for 20* ms w"en tag is detectedPin !o H 13 LE$ 9 actie low: LE$ will glow for 20* ms w"en tag is detectedPin !o H 1, )iegand $ATA L&)

9 aailale in )iegand :

@t will gie $ATA L&) signal5

Pin

!oH2720

Antenna @nput Loop Antenna s"ould e connected5

Li?!i% Cr3sta" Dis+"a3

Li8uid crystal displays 9LC$s: "ae materials w"ic" comine t"e properties of ot"

li8uids and crystals5 Rat"er t"an "aing a melting point7 t"ey "ae a temperature range wit"in

w"ic" t"e molecules are almost as moile as t"ey would e in a li8uid7 ut are grouped toget"er

in an ordered form similar to a crystal5An LC$ consists of two glass panels7 wit" t"e li8uidcrystal material sand witc"ed in etween t"em5 T"e inner surface of t"e glass plates are coated

wit" transparent electrodes w"ic" define t"e c"aracter7 symols or patterns to e displayed

polymeric layers are present in etween t"e electrodes and t"e li8uid crystal7 w"ic" ma(es t"e

li8uid crystal molecules to maintain a defined orientation angle5

&ne eac" polarisers are pasted outside t"e two glass panels5 T"ese polarisers would rotate

t"e lig"t rays passing t"roug" t"em to a definite angle7 in a particular direction

)"en t"e LC$ is in t"e off state7 lig"t rays are rotated y t"e two polarisers and t"e

li8uid crystal7 suc" t"at t"e lig"t rays come out of t"e LC$ wit"out any orientation7 and "ence

t"e LC$ appears transparent5

)"en sufficient oltage is applied to t"e electrodes7 t"e li8uid crystal molecules would e

aligned in a specific direction5 T"e lig"t rays passing t"roug" t"e LC$ would e rotated y t"e

polarisers7 w"ic" would result in actiating "ig"lig"ting t"e desired c"aracters5

-



T"e LC$Js are lig"tweig"t wit" only a few millimeters t"ic(ness5 Since t"e LC$Js

consume less power7 t"ey are compatile wit" low power electronic circuits7 and can e powered

for long durations5

T"e LC$ s doesnJt generate lig"t and so lig"t is needed to read t"e display5 By using

ac(lig"ting7 reading is possile in t"e dar(5 T"e LC$Js "ae long life and a wide operating

temperature range5 C"anging t"e display sie or t"e layout sie is relatiely simple w"ic"

ma(es t"e LC$Js more customer friendly5

T"e LC$s used e'clusiely in watc"es7 calculators and measuring instruments are t"e

simple seen4segment displays7 "aing a limited amount of numeric data5 T"e recent adances in

tec"nology "ae resulted in etter legiility7 more information displaying capaility and a wider

temperature range5 T"ese "ae resulted in t"e LC$s eing e'tensiely used in

telecommunications and entertainment electronics5 T"e LC$s "ae een started replacing t"ecat"ode ray tues 9CRTs: used for t"e display of te't and grap"ics7 and also in small T

applications5

T"is section descries t"e operation modes of LC$Js t"en descrie "ow to program and

interface an LC$ to 0*1 using Assemly and C5

LCD o+eration@

@n recent years t"e LC$ is finding widespread use replacing LE$ s 9seen4segment LE$

s or ot"er multi4segment LE$ s:5T"is is due to t"e following reasonsH15 T"e declining prices of LC$s5

25 T"e aility to display numers7 c"aracters and grap"ics5 T"is is in contrast to LE$ w"ic"

is limited to numers and a few c"aracters5

35 @ncorporation of a refres"ing controller into t"e LC$7 t"ere y relieing t"e CP6 of t"e

tas( of refres"ing t"e LC$5 @n t"e case of LE$ s7 t"ey must e refres"ed y t"e CP6 to

(eep on displaying t"e data5

,5 Ease of programming for c"aracters and grap"ics5

LCD +in %es#ri+tion@

T"e LC$ discussed in t"is section "as 1, pins5 T"e function of eac"

pin is gien in tale5

=*



#ig 2- H LC$

TA'LE 1@ in %es#ri+tion 8or LCD

in s3)bo" I>O Des#ri+tion1 ss 44 Xround2 cc 44 power supply

3 EE 44 Power supply tocontrol contrast

, RS @ RSK* to select

command register

RSK1 to select

data register R) @ R)K* for write

R)K1 for read

= E @& Enale $B* @& T"e 04it data us0 $B1 @& T"e 04it data us- $B2 @& T"e 04it data us1* $B3 @& T"e 04it data us11 $B, @& T"e 04it data us12 $B @& T"e 04it data us13 $B= @& T"e 04it data us

=1



1, $B @& T"e 04it data us

T"e LC$ can display a c"aracter successfully y placing t"e

15 $ata in $ata Register

25 Command in Command Register of LC$

15 $ata corresponds to t"e ASC@@ alue of t"e c"aracter to e printed5 T"is can e done y

placing t"e ASC@@ alue on t"e LC$ $ata lines and selecting t"e $ata Register of t"e

LC$ y selecting t"e RS 9Register Select: pin5

25 Eac" and eery display location is accessed and controlled y placing respectie

command on t"e data lines and selecting t"e Command Register of LC$ y selecting t"e

9Register Select: RS pin5

T"e commonly used commands are s"own elow wit" t"eir operations5

TA'LE 2@ LCD Co))an% Co%es

Co%e ;-e< Co))an% to LCD Instr!#tion Reister

1 Clear display screen2 Return "ome, $ecrement cursor = @ncrement cursor S"ift display rig"t S"ift display left0 $isplay off7 cursor off A $isplay off7 cursor onC $isplay on7 cursor off E $isplay on7 cursor on# $isplay on7 cursor lin(ing1* S"ift cursor position to left1, S"ift cursor position to rig"t10 S"ift t"e entire display to t"e left

1C S"ift t"e entire display to t"e rig"t0* #orce cursor to eginning of 1st lineC* #orce cursor to eginning of 2nd line30 2 lines and ' matri'

Uses@

=2



T"e LC$s used e'clusiely in watc"es7 calculators and measuring instruments are t"e

simple seen4segment displays7 "aing a limited amount of numeric data5 T"e recent adances in

tec"nology "ae resulted in etter legiility7 more information displaying capaility and a wider

temperature range5 T"ese "ae resulted in t"e LC$s eing e'tensiely used in

telecommunications and entertainment electronics5

So in t"is pro/ect7 t"e LC$ is used to display t"e instantaneous information5 T"e

information may e prompting or alerting or instructing t"e user5

LINEAR 4EYAD

T"is section asically consists of a Linear .eypad5 Basically a .eypad can e classified into

2 categories5 &ne is Linear .eypad and t"e ot"er is %atri' (eypad5

15 %atri' .eypad5

25 Linear .eypad5

1. Matri 4e3+a%H T"is .eypad got (eys arranged in t"e form of Rows and Columns5 T"at

is w"y t"e name %atri' .eypad5 According to t"is (eypad7 @n order to find t"e (ey eing pressed t"e (eypad need to e scanned y ma(ing rows as ip and columns as output or

ice ersa5

T"is .eypad is used in places w"ere one needs to connect more no5 &f

(eys wit" less no5 &f data lines5

2. Linear 4e3+a%@ T"is .eypad got nJ no5 &f (eys connected to nJ data lines of

microcontroller5

T"is .eypad is used in places w"ere one needs to connect less no5 &f

(eys5

@n t"is pro/ect7 Linear .eypad is used wit" 3 switc"es eing connected ecause t"e no5 &f

switc"es is less 9less t"an 0:5

=3



Xenerally7 in Linear .eypads one end of t"e switc" is connected to %icrocontroller

9Configured as ip: and ot"er end of t"e switc" is connected to t"e common ground5 So

w"eneer a (ey of Linear .eypad is pressed t"e logic on t"e microcontroller pin will go

L&)5

+ere in t"is pro/ect7 a linear (eypad is used wit" switc"es connected in a serial manner5

Linear (eypad is used in t"is pro/ect ecause it ta(es less no5 &f port pins5 T"e Linear .eypad

wit" , .eys is s"own elow5

fig 3* H linear (eypad

=,



EEROM

EEROM 9also written E2ROM and pronounced e4e4prom or simply e4s8uared:7 w"ic"

stands for Electrically Erasale rogrammale R ead4Only Memory7 is a type of non4olatile

memory used in computers and ot"er electronic deices to store small amounts of data t"at must

e saed w"en power is remoed7 e5g57 caliration tales or deice configuration5

)"en larger amounts of more static data are to e stored 9suc" as in 6SB flas" dries:

ot"er memory types li(e flas" memory are more economical5

EEPR&%s are realied as arrays of floating4gate transistors5

History

@n 1-037 Xree( American Xeorge Perlegos at @ntel deeloped t"e @ntel 201=7 w"ic" was

uilt on earlier EPR&% tec"nology7 ut used a t"in gate o'ide layer so t"at t"e c"ip could erase

its own its wit"out re8uiring a 6 source5 Perlegos and ot"ers later left @ntel to form See8

Tec"nology7 w"ic" used on4deice c"arge pumps to supply t"e "ig" oltages necessary for programming EEPR&%s51

Functions of EEPROM

T"ere are different types of electrical interfaces to EEPR&% deices5 %ain categories of

t"ese interface types are H

• Serial us

• Parallel us

+ow t"e deice is operated depends on t"e electrical interface5

=

http://en.wikipedia.org/wiki/Non-volatile_memory


http://en.wikipedia.org/wiki/USB_flash_drive

http://en.wikipedia.org/wiki/Flash_memory

http://en.wikipedia.org/wiki/Floating-gate_transistor

http://en.wikipedia.org/wiki/1983

http://en.wikipedia.org/wiki/Greek_American

http://en.wikipedia.org/w/index.php?title=George_Perlegos&action=editredlink

http://en.wikipedia.org/wiki/Intel

http://en.wikipedia.org/wiki/EPROM

http://en.wikipedia.org/w/index.php?title=Seeq_Technology&action=editredlink


http://en.wikipedia.org/wiki/Charge_pump

http://en.wikipedia.org/wiki/#_note-0

http://en.wikipedia.org/wiki/Serial_bus

http://en.wikipedia.org/wiki/Parallel_bus



http://en.wikipedia.org/wiki/USB_flash_drive



http://en.wikipedia.org/wiki/1983

http://en.wikipedia.org/wiki/Greek_American

http://en.wikipedia.org/w/index.php?title=George_Perlegos&action=editredlink

http://en.wikipedia.org/wiki/Intel




http://en.wikipedia.org/wiki/Charge_pump


http://en.wikipedia.org/wiki/Serial_bus

http://en.wikipedia.org/wiki/Parallel_bus



Serial bus devices

%ost common serial interface types are SP@7 @C and 14)ire5 T"ese t"ree interfaces

re8uire etween 2 and , controls signals for operation7 resulting in a memory deice in an 0 pin

9or less: pac(age5

T"e serial EEPR&% typically operates in t"ree p"asesH &P4Code P"ase7 Address P"ase

and $ata P"ase5 T"e &P4Code is usually t"e first 04its input to t"e serial input pin of t"e

EEPR&% deice 9or wit" most @C deices7 is implicit:I followed y 0 to 2, its of addressing

depending on t"e dept" of t"e deice7 t"en data to e read or written5

Eac" EEPR&% deice typically "as its own set of &P4Code instructions to map to different

functions5 Some of t"e common operations on SP@ EEPR&% deices areH

• )rite Enale 9)RE!:

• )rite $isale 9)R$@:• Read Status Register 9R$SR:

• )rite Status Register 9)RSR:

• Read $ata 9REA$:

• )rite $ata 9)R@TE:

&t"er operations supported y some EEPR&% deices areH

• Program

• Sector Erase

• C"ip Erase commands

Parallel bus devices

Parallel EEPR&% deices typically "ae an 04it data us and an address us wide

enoug" to coer t"e complete memory5 %ost deices "ae c"ip select and write protect pins5

Some microcontrollers also "ae integrated parallel EEPR&%5

&peration of a parallel EEPR&% is simple and fast w"en compared to serial EEPR&%7 ut t"esedeices are larger due to t"e "ig"er pin count 9up to 32 pins or more: and "ae een decreasing

in popularity in faor of serial EEPR&% or #las"5

Failure modes

T"ere are two limitations of stored informationI endurance7 and data retention5

==

http://en.wikipedia.org/wiki/Serial_Peripheral_Interface_Bus

http://en.wikipedia.org/wiki/I%C2%B2C

http://en.wikipedia.org/wiki/1-Wire

http://en.wikipedia.org/wiki/Opcode


http://en.wikipedia.org/wiki/Microcontroller


http://en.wikipedia.org/wiki/I%C2%B2C

http://en.wikipedia.org/wiki/1-Wire

http://en.wikipedia.org/wiki/Opcode


http://en.wikipedia.org/wiki/Microcontroller



$uring rewrites7 t"e gate o'ide in t"e floating4gate transistors gradually accumulates trapped

electrons5 T"e electric field of t"e trapped electrons adds to t"e electrons in t"e floating gate7

lowering t"e window etween t"res"old oltages for eros s ones5 After sufficient numer of

rewrite cycles7 t"e difference ecomes too small to e recogniale7 t"e cell is stuc( in

programmed state7 and endurance failure occurs5 T"e manufacturers usually specify minimal

numer of rewrites eing 1*= or more5

$uring storage7 t"e electrons in/ected into t"e floating gate may drift t"roug" t"e insulator7

especially at increased temperature7 and cause c"arge loss7 reerting t"e cell into erased state5

T"e manufacturers usually guarantee data retention of 1* years or more52

Related types

#las" memory is a later form of EEPR&%5 @n t"e industry7 t"ere is a conention toresere t"e term EEPR&% to yte4wise writeale memories compared to loc(4wise writale

flas" memories5 EEPR&% ta(es more die area t"an flas" memory for t"e same capacity ecause

eac" cell usually needs ot" a read7 write and erase transistor 7 w"ile in flas" memory t"e erase

circuits are s"ared y large loc(s of cells 9often 12N0:5

!ewer non4olatile memory tec"nologies suc" as #eRA% and %RA% are slowly replacing

EEPR&%s in some applications7 ut are e'pected to remain a small fraction of t"e EEPR&%

mar(et for t"e foreseeale future5

Comparison with EPROM and EEPROM/Flash

T"e difference etween EPR&% and EEPR&% lies in t"e way t"at t"e memory

programs and erases5 EEPR&% can e programmed and erased electrically using field emission

9more commonly (nown in t"e industry as ?#owler4!ord"eim tunneling?:5

EPR&%s can`t e erased electrically7 and are programmed ia "ot carrier in/ection onto t"e

floating gate5 Erase is ia an ultraiolet lig"t source7 alt"oug" in practice many EPR&%s are

encapsulated in plastic t"at is opa8ue to 6 lig"t7 and are ?one4time programmale?5

%ost !&R #las" memory is a "yrid style>programming is t"roug" +ot carrier in/ection and

erase is t"roug" #owler4!ord"eim tunneling5

EEPR&% 92,C*2:H

=




http://en.wikipedia.org/wiki/Transistor

http://en.wikipedia.org/wiki/Ferroelectric_RAM

http://en.wikipedia.org/wiki/MRAM


http://en.wikipedia.org/wiki/Field_emission

http://en.wikipedia.org/wiki/Hot_carrier_injection

http://en.wikipedia.org/wiki/Ultraviolet






http://en.wikipedia.org/wiki/Transistor

http://en.wikipedia.org/wiki/Ferroelectric_RAM

http://en.wikipedia.org/wiki/MRAM


http://en.wikipedia.org/wiki/Field_emission


http://en.wikipedia.org/wiki/Ultraviolet





FEATURES

U Low power C%&S

> Actie current less t"an 2 mA

> Standy current less t"an 0 mA

U +ardware writes protection

> )rite control pin

U @nternally organied as 2= ' 0

U Two4wire serial interface

> Bidirectional data transfer protocol

U 04Byte page4write mode

> %inimied total write time per yte

U Automatic word address incrementing > Se8uential register read

U Self4timed write cycle

> %a'imum write cycle time of 1* ms

U ,** .+ Compatiility

EnduranceH 17 ***7*** cycles per yte

U 04pin P$@P7 TSS&P7 %S&P or S&@C pac(ages

U #iltered inputs for noise suppression

OERIE=

T"e @S2,C*2 is a low cost 27*,04it serial EEPR&%5 @t is faricated using ISSI Js adanced

C%&S EEPR&% tec"nology and operates from a single supply5 T"e @S2,C*2 is internally

organied as a 2= ' 0 memory an(5 T"e @S2,C*2 features a serial interface and software

protocol allowing operation on a simple 24wire us5 6p to eig"t @S2,C*2s may e connected to

t"e 24wire us y programming t"e A*7 A17 and A2 inputs5

IN CONFIGURATION

=0



IN DESCRITIONS

A*4A2 Address @nputs

S$A Serial $ata @&

SCL Serial Cloc( @nput

)C )rite Control @nput

CC Power

X!$ Xround

A7 A1 an% A2 4 T"e address inputs are used to set t"e least significant t"ree its of t"e slae

address5 T"ese inputs may e tied +@X+ or L&)7 or t"ey may e actiely drien5 T"ese inputs

allow up to eig"t @S2,C*2 deices to e connected toget"er on t"e us5 )"en left floating7 A*7

A1 and A2 are pulled to ground5 T"e default alues are eros5

Seria" Data ;SDA< 4 T"e S$A pin is a idirectional pin used to transfer data into and out of t"e

deice5 $ata may c"ange only w"en SCL is L&)5 @t is an open4drain output7 and may e wire

&Red wit" any numer of open4drain or open4collector outputs5

Seria" C"o#( ;SCL< 4 T"e SCL input is used to cloc( all data into and out of t"e deice5 @n t"e

)R@TE mode7 data must remain stale w"en SCL is +@X+5 @n t"e REA$ mode7 data is cloc(ed

out on t"e falling edge of SCL5

=rite Contro" ;)C< 4 T"e )rite Control input is used to disale any attempt to write to t"e

memory5 )"en +@X+7 t"e memory is protectedI w"en L&)7 t"e write function is normal5 T"e

part can e read independent of t"e state of )C pin5 )"en not connected7 t"is pin will e pulled

L&)5

=-



ENDURANCE AND DATA RETENTION

T"e @S2,C*2 is designed for applications re8uiring "ig" endurance write cycles and unlimited

read cycles5 @t proides 1* years of secure data retention7 wit" or wit"out power applied7 after t"e

e'ecution of 17***7*** write cycles5

ALICATIONS

T"e @S2,C*2 is ideal for "ig" olume applications re8uiring low power and low density storage5

T"is deice uses a low4cost7 space4saing 04pin plastic pac(age5 Candidate applications include

rootics7 alarm deices7 electronic loc(s7 meters and instrumentation5

GENERAL DESCRITION

T"e @S2,C*2 features a SER@AL communication7 and supports idirectional data transmission

protocol allowing operation on a simple two4wire us etween t"e different deices connected

somew"ere on t"e system us5 T"e two4wire us is defined as a serial data line 9S$A:7 and a

serial cloc( line 9SCL:5

T"e protocol defines any deice t"at sends data onto t"e S$A us as a transmitter7 and t"e

receiing deice as a receier5 T"e deice controlling t"e data transmission is named %ASTER

deice7 and t"e controlled deice is named SLAE deice5 @n all cases7 t"e @S2,C*2 will e a

slae deice7 since it neer initiates any data transfers5 6p to eig"t @S2,C*2 can e connected to

t"e us5 $eice`s p"ysical address inputs A*4A2 must e connected to eit"er CC or X!$5 )"en

left floating7 A*7 A1 and A2 are pulled to ground5 T"e default alues are eros5

#ollowing a START condition7 t"e %ASTER 9transmitter: deice must initiate t"e F$eice

Addressing ByteG including deice type identifier7 deice address7 and a read or write operation

to select a slae deice 9receier: connected to t"e system us5 T"e receier will t"en respond

wit" an Ac(nowledge y pulling t"e S$A line L&)5 T"e Ac(nowledge is used to indicate

*



successful data transfers5 T"e transmitting deice will release t"e data us 9S$A goes +@X+:

after transmitting eig"t its 9one data it is transferred at t"e falling edge of eac" cloc( cycle:5

$uring t"e nint" cloc( cycle7 t"e receier will pull t"e S$A line L&) to ac(nowledge t"e

transmitter t"at it receied t"e eig"t its of data5

DEICE OERATION

START an% STO Con%itions

Bot" S$A and SCL lines remain +@X+ w"en t"e S$A us is not usy5 A +@X+4to4L&)

transition of S$A line7 w"ile SCL is +@X+7 is defined as t"e START condition5 A L&) to4 +ig"transition of S$A line7 w"ile SCL is +@X+7 is defined as t"e ST&P condition5

Data a"i%it3 roto#o"

&ne data it is transferred during eac" cloc( cycle5 T"e data on t"e S$A line must remain stale

during t"e +@X+ period of t"e cloc( cycle7 ecause c"anges on S$A line during t"e SCL +@X+

period will e interpreted as START or ST&P control signals5

1



Devi#e A%%ressin '3te De8initions

T"e most significant four its of $eice Addressing Byte 9Bit to Bit ,: are defined as t"e

deice type identifier5 #or @S2,C*27 t"is is fi'ed as 1*1*5 T"e ne't t"ree significant address its

9Bit 3 to Bit 1: address a particular deice5 6p to eig"t @S2,C*2 deices can e connected on t"e

us5

T"ese eig"t addresses are defined y t"e state of t"e A*7 A17 and A2 inputs5 T"e last it Bit *

defines t"e write or read operation to e performed5 )"en set to F1G7 a REA$ operation is

selectedI w"en set to F*G a )R@TE operation is selected5

=RITE OERATION

'3te =rite

#or a )R@TE operation7 t"e @S2,C*2 re8uires anot"er 04it data word address following t"e

$eice Addressing Byte and Ac(nowledgement5 T"is data word address proides access to any

one of t"e 2= data words of deice`s memory array5

6pon receipt of t"e data word address7 t"e @S2,C*2 responds wit" an Ac(nowledge on S$A7 and

waits for t"e ne't 04it data word7 t"en again responding wit" an Ac(nowledge5 T"e master

deice terminates t"e Byte )rite &peration y generating a ST&P conditionI afterward t"e

@S2,C*2 egins t"e internal )R@TE cycle to t"e nonolatile memory array5 Refer to )rite CycleTiming5 All inputs are disaled during t"is write cycle and t"e deice will not respond to any

re8uests from t"e master5

2



ae =rite

T"e @S2,C*2 is capale of 04yte page4 )R@TE operation5 A page4)R@TE is initiated in t"e

same manner as a yte write7 ut instead of terminating t"e internal write cycle after t"e first data

word is transferred7 t"e master deice can transmit up to more words5 After t"e receipt of eac"

data word7 t"e @S2,C*2 responds immediately wit" an Ac(nowledge on S$A line7 and t"e four

lower order data word address its are internally incremented y one w"ile t"e four "ig"er order

its of t"e data word address remain constant5 @f t"e master deice s"ould transmit more t"an 0

words7 prior to issuing t"e ST&P condition7 t"e address counter will Froll oer7G and t"e

preiously written data will e oerwritten5 All inputs are disaled until completion of t"e

internal )R@TE cycle5

A#(no"e%e o""in

&nce t"e internal write cycle "as started and t"e @S2,C*2 inputs are disaled7 ac(nowledge

polling can e initiated5 T"is inoles sending a start condition followed y t"e $eice

Addressing Byte5 T"e readwrite it is representation of t"e operation desired5 &nly if t"e

internal write cycle "as een completed will t"e @S2,C*2 respond wit" ac(nowledge on t"e S$A

us allowing t"e read or write se8uence to continue5

READ OERATION

REA$ operations are initiated in t"e same manner as )R@TE operations7 e'cept t"at t"e

readwrite it of t"e deice addressing yte is set to F1G5 T"ere are t"ree REA$ operationoptionsH current address read7 random address read and se8uential read5

C!rrent A%%ress Rea%

T"e @S2,C*2 contains an internal address counter w"ic" maintains t"e address of t"e last data

word accessed7 incremented y one5 #or e'ample7 if t"e preious operation eit"er a read or write

operation addressed to t"e address location n7 t"e internal address counter would increment to

3



address location n15 )"en t"e @S2,C*2 receies t"e $eice Addressing Byte wit" a REA$

operation 9readwrite it set to F1G:7 it will respond an Ac(nowledge and transmit t"e 04it data

word stored at address location n15 @f t"e Current Address REA$ operation only accesses a

single yte of data7 t"e master deice terminates t"e Current Address REA$ operation y pulling

Ac(nowledge +@X+ 9lac( of Ac(nowledge: indicating t"e last data word to e read7 followed y

a ST&P condition5

Ran%o) A##ess Rea%

Random Address REA$ operation allows t"e master deice to access any memory location in a

random fas"ion5 T"is operation inoles a two4step process5 #irst7 t"e master deice generates a

START condition and initiates $eice Addressing Byte wit" a dummy )R@TE operation

9readwrite it sets to F*G:7 followed y t"e address of t"e data word t"e master deice is to

REA$5 T"is procedure stores t"e desired address of data word to t"e internal address counter of

t"e @S2,C*25

After t"e data word address Ac(nowledge is receied y t"e master deice7 t"e master deice

now initiates a C6RRE!T A$$RESS REA$ y sending $eice Addressing Byte wit" a REA$

operation 9readwrite it sets to F1G:5 T"e @S2,C*2 responds wit" an Ac(nowledge and transmits

t"e eig"t data its stored at t"e address location w"ere t"e master deice is to REA$5 At t"is

point7 t"e master deice terminates t"e operation y pulling Ac(nowledge +@X+ 9lac( of

Ac(nowledge: indicating t"e last data word to e read7 followed y a ST&P condition5

,



Se?!entia" Rea%

Se8uential Reads can e initiated as eit"er a Current Address Read or Random Address Read5

T"e first data word is transmitted as wit" t"e ot"er yte read modes7 t"e master deice now

responds wit" an AC.nowledge indicating t"at it re8uires additional data from t"e @S2,C*25 T"e

@S2,C*2 continues to output data for eac" AC.nowledge receied5 T"e master deice terminates

t"e se8uential REA$ operation y pulling AC.nowledge +@X+ 9lac( of AC.nowledge:

indicating t"e last data word to e read7 followed y a ST&P condition5

T"e data output is se8uentialI wit" t"e data from address n followed y t"e date from address

n1 555 etc5 T"e address4counter increments y one automatically7 allowing t"e entire memory

contents to e serially read during se8uential read operation5 )"en t"e memory address

oundary 9address 2: is reac"ed7 t"e address counter Frolls oerG to address *7 and t"e

@S2,C*2 continues to output data for eac" Ac(nowledge receied5



'UER

T"e ?Pieoelectric sound components? introduced "erein operate on an innoatie principle

utiliing natural oscillation of pieoelectric ceramics5 T"ese uers are offered in lig"tweig"t

compact sies from t"e smallest diameter of 12mm to large Pieo electric sounders5 Today7

pieoelectric sound components are used in many ways suc" as "ome appliances7 &A e8uipment7

audio e8uipment telep"ones7 etc5 And t"ey are applied widely7 for e'ample7 in alarms7 spea(ers7

telep"one ringers7 receiers7 transmitters7 eep sounds7 etc5

FIG@ T3+es o8 '!55ers

=



Os#i""atin S3ste)@

Basically7 t"e sound source of a pieoelectric sound component is a pieoelectric

diap"ragm5 A pieoelectric diap"ragm consists of a pieoelectric ceramic plate w"ic" "as

electrodes on ot" sides and a metal plate 9rass or stainless steel7 etc5:5 A pieoelectric ceramic

plate is attac"ed to a metal plate wit" ad"esies5

#ig5 2 s"ows t"e oscillating system of a pieoelectric diap"ragm5 Applying $5C5 oltage

etween electrodes of a pieoelectric diap"ragm causes mec"anical distortion due to t"e

pieoelectric effect5 #or a miss"aped pieoelectric element7 t"e distortion of t"e pieoelectric

element e'pands in a radial direction5 And t"e pieoelectric diap"ragm ends toward t"e

direction s"own in #ig52 9a:5

T"e metal plate onded to t"e pieoelectric element does not e'pand5 Conersely7 w"en

t"e pieoelectric element s"rin(s7 t"e pieoelectric diap"ragm ends in t"e direction s"own in

#ig52 9:5 T"us7 w"en AC oltage is applied across electrodes7 t"e ending s"own in #ig52 9a:

and #ig52 9: is repeated as s"own in #ig52 9c:7 producing sound waes in t"e air5

DESIGN ROCEDURES@

@n general7 man`s audile fre8uency range is aout 2* + to 2*(+5 #re8uency ranges of

2(+ to ,(+ are most easily "eard5 #or t"is reason7 most pieoelectric sound components are

used in t"is fre8uency range7 and t"e resonant fre8uency 9f*: is generally selected in t"e same



range too5 As s"own in #ig5 37 t"e resonant fre8uency depends on met"ods used to support t"e

pieoelectric diap"ragm5 @f pieoelectric diap"ragms are of t"e same s"ape7 t"eir alues will

ecome smaller in t"e order of 9a:7 9: and 9c:5

@n general7 t"e pieoelectric diap"ragm is installed in a caity to produce "ig" sound

pressure5 T"e resonant fre8uency 9fca: of t"e caity in is otained from #ormula 91:

9+elm"olt`s #ormula:5 Since t"e pieoelectric diap"ragm and caity "ae proper resonant

fre8uencies7 9f*: and 9fca: respectiely7 sound pressure in specific fre8uencies can e increased

and a specific andwidt" can e proided y controlling ot" positions5

0



Cir#!it Des#ri+tion

T"is section gies an oeriew of t"e w"ole circuitry and "ardware inoled in t"e

pro/ect5 T"e main aim of t"is pro/ect is to implement t"e stoc( updating detecting t"e e'piry

date for p"armacy5 T"e purpose of t"e pro/ect is to (now t"e details of t"e stoc( and also t"e

e'piry date for t"e medicines in t"e p"armacy5

@n t"is pro/ect we are giing power supply to all units7 it asically consists of a

Transformer to step down t"e 23* ac to 12 ac followed y diodes5 +ere diodes are used to

rectify t"e ac to dc5 After rectification t"e otained rippled dc is filtered using a capacitor #ilter5

A positie oltage regulator is used to regulate t"e otained dc oltage5

T"e o/ectie of t"is pro/ect is to proide additional security to t"e AT% using R#@$5 T"e

Readers w"ic" reads t"e information from t"e cards are called Card Readers5 )e can use R#@$

Reader to read t"e data from t"e R#@$ card5

T"e pro/ect asically employs a microcontroller as a "eart of our pro/ect

w"ic" is interfaced wit" R#@$ Card Reader to get t"e data regarding t"e card eing read y t"e

Card Reader5 @f aut"entication results in Success it prompts for P@! numer to e c"ec(ed wit"

pre4assigned P@! and transaction results if and only if P@! numer matc" occurs5

T"e R#@$ card stores t"e secret information of t"e concerned

person5 )"eneer t"e card is eing inserted into t"e AT% mac"ine t"en t"e respectie Card

Reader reads t"e card and t"en communicates wit" t"e controller5 T"e system as(s for t"e P@!

9Personal @dentification !umer: code w"ic" "as already gien to t"e concerned person5 )"en

t"e P@! code is entered t"roug" t"e (eypad t"en t"e transaction will e occurred if and only if

t"e P@! code matc"es wit" pre4stored P@! numer5

-



S&#T)ARE ComponentsA'OUT SOFT=ARE

Software used isH

.eil software for C programmingE'press PCB for lay out design

E'press SC+ for sc"ematic design

4EIL Jision$

)"at`s !ew in Qision3Z

Qision3 adds many new features to t"e Editor li(e Te't Templates7 ;uic( #unction !aigation7

and Synta' Coloring wit" race "ig" lig"ting Configuration )iard for dialog ased startup and

deugger setup5 Qision3 is fully compatile to Qision2 and can e used in parallel wit"

Qision25

=-at is Jision$K

Qision3 is an @$E 9@ntegrated $eelopment Enironment: t"at "elps you write7 compile7 and

deug emedded programs5 @t encapsulates t"e following componentsH

• A pro/ect manager5

• A ma(e facility5

• Tool configuration5

• Editor5

• A powerful deugger5

0*



E+ress C'

E'press PCB is a Circuit $esign Software and PCB manufacturing serice5 &ne

can learn almost eeryt"ing you need to (now aout E'press PCB from t"e "elp topics included

wit" t"e programs gien5

$etailsH

E'press PCB7 ersion 5=5*

E+ress SC0

T"e E'press SC+ sc"ematic design program is ery easy to use5 T"is software

enales t"e user to draw t"e Sc"ematics wit" drag and drop options5

A ;uic( Start Xuide is proided y w"ic" t"e user can learn "ow to use it5

$etailsH

E'press SC+7 ersion 5=5*EM'EDDED C@

T"e programming Language used "ere in t"is pro/ect is an E)be%%e% C

Language5 T"is Emedded C Language is different from t"e generic C language in few t"ings

li(e

a: $ata types

: Access oer t"e arc"itecture addresses5

T"e Emedded C Programming Language forms t"e user friendly language wit" access oer Port

addresses7 S#R Register addresses etc5

Emedded C $ata typesH

Data T3+es Si5e in 'its Data Rane>Usae

unsigned c"ar 04it *42

signed c"ar 04it 4120 to 12

unsigned int 1=4it * to =3

signed int 1=4it 4327=0 to 327=

sit 14it S#R it addressale only

it 14it RA% it addressale

only

01



sfr 04it RA% addresses 0*4##+

only

Signed c"arH

o 6sed to represent t"e M or alues5

o As a result7 we "ae only its for t"e magnitude of t"e signed numer7 giing us alues

from 4120 to 125

SOFT=ARE

Jision$

Qision3 is an @$E 9@ntegrated $eelopment Enironment: t"at "elps you write7 compile7 and

deug emedded programs5 @t encapsulates t"e following componentsH

• A pro/ect manager5

• A ma(e facility5

• Tool configuration5

• Editor5

• A powerful deugger5

02



To "elp you get started7 seeral e'ample programs 9located in t"e C*1Ea)+"es7

C2*1Ea)+"es7 C1,,Ea)+"es7 and ARM...Ea)+"es: are proided5

0ELLO is a simple program t"at prints t"e string ?+ello )orld? using t"e Serial

@nterface5

'!i"%in an A++"i#ation in Jision2

To uild 9compile7 assemle7 and lin(: an application in Qision27 you mustH

15 Select Pro/ect 4 9for e'ample7 1,,EXAMLES0ELLO0ELLO.U2:5

25 Select Pro/ect 4 Reuild all target files or Build target5

Qision2 compiles7 assemles7 and lin(s t"e files in your pro/ect5

Creatin Yo!r On A++"i#ation in Jision2

To #reate a ne +roe#t in Jision2 3o! )!stH

15 Select Pro/ect 4 !ew Pro/ect5

25 Select a directory and enter t"e name of t"e pro/ect file5

35 Select Pro/ect 4 Select $eice and select an 0*17 217 or C1='ST1* deice from t"e

$eice $ataase5

,5 Create source files to add to t"e pro/ect5

5 Select Pro/ect 4 Targets7 Xroups7 #iles7 Add#iles7 select Source Xroup17 and add t"esource files to t"e pro/ect5

=5 Select Pro/ect 4 &ptions and set t"e tool options5 !ote w"en you select t"e target deice

from t"e $eice $ataase all special options are set automatically5 Dou typically only

need to configure t"e memory map of your target "ardware5 $efault memory model

settings are optimal for most applications5

5 Select Pro/ect 4 Reuild all target files or Build target5

Deb!in an A++"i#ation in Jision2

To deug an application created using Qision27 you mustH

15 Select $eug 4 StartStop $eug Session5

25 6se t"e Step toolar uttons to single4step t"roug" your program5 Dou may enter G

)ain in t"e &utput )indow to e'ecute to t"e main C function5

35 &pen t"e Serial )indow using t"e Seria" 1 utton on t"e toolar5

03



$eug your program using standard options li(e Step7 Xo7 Brea(7 and so on5

Startin Jision2 an% #reatin a roe#t

Qision2 is a standard )indows application and started y clic(ing on t"e program icon5 To

create a new pro/ect file select from t"e Qision2 menu

roe#t M !ew Pro/ect5 T"is opens a standard )indows dialog t"at as(s you for t"e new

pro/ect file name5

)e suggest t"at you use a separate folder for eac" pro/ect5 Dou can simply use t"e icon Create

!ew #older in t"is dialog to get a new empty folder5 T"en select t"is folder and enter t"e file

name for t"e new pro/ect7 i5e5 Pro/ect15

Qision2 creates a new pro/ect file wit" t"e name PR&\ECT1562 w"ic" contains a default

target and file group name5 Dou can see t"ese names in t"e Pro/ect

=in%o H Fi"es.

!ow use from t"e menu Pro/ect M Select $eice for Target and select a CP6 for your pro/ect5

T"e Select $eice dialog o' s"ows t"e Qision2 deice dataase5 \ust select t"e

microcontroller you use5 )e are using for our e'amples t"e P"ilips 0*C1R$ CP65 T"is

selection sets necessary tool options for t"e 0*C1R$ deice and simplifies in t"is way t"e tool

Configuration5

'!i"%in roe#ts an% Creatin a 0EX Fi"es

Typical7 t"e tool settings under &ptions M Target are all you need to start a new

application5 Dou may translate all source files and line t"e application wit" a clic( on t"e Build

Target toolar icon5 )"en you uild an application wit" synta' errors7 Qision2 will display

errors and warning messages in t"e &utput

)indow M Build page5 A doule clic( on a message line opens t"e source file on t"e correct

location in a Qision2 editor window5

&nce you "ae successfully generated your application you can start deugging5

After you "ae tested your application7 it is re8uired to create an @ntel +E< file to

download t"e software into an EPR&% programmer or simulator5 Qision2 creates +E< files

wit" eac" uild process w"en Create +E< files under &ptions for Target M &utput is enaled5

Dou may start your PR&% programming utility after t"e ma(e process w"en you specify t"e

program under t"e option Run 6ser Program [15

0,



CU Si)!"ation

Qision2 simulates up to 1= %ytes of memory from w"ic" areas can e mapped for read7 write7

or code e'ecution access5 T"e Qision2 simulator traps and reports illegal memory accesses

eing done5

@n addition to memory mapping7 t"e simulator also proides support for t"e integrated

perip"erals of t"e arious 0*1 deriaties5 T"e on4c"ip perip"erals of t"e CP6 you "ae

selected are configured from t"e $eice

Database se"e#tion

Dou "ae made w"en you create your pro/ect target5 Refer to page 0 for more @nformation aout

selecting a deice5 Dou may select and display t"e on4c"ip perip"eral components using t"e

$eug menu5 Dou can also c"ange t"e aspects of eac" perip"eral using t"e controls in t"e dialog o'es5

Start Deb!in

Dou start t"e deug mode of Qision2 wit" t"e $eug M StartStop $eug Session command5

$epending on t"e &ptions for Target M $eug Configuration7 Qision2 will load t"e application

program and run t"e startup code Qision2 saes t"e editor screen layout and restores t"e screen

layout of t"e last deug session5 @f t"e program e'ecution stops7 Qision2 opens an editor

window wit" t"e source te't or s"ows CP6 instructions in t"e disassemly window5 T"e ne't

e'ecutale statement is mar(ed wit" a yellow arrow5 $uring deugging7 most editor features are

still aailale5

#or e'ample7 you can use t"e find command or correct program errors5 Program source

te't of your application is s"own in t"e same windows5 T"e Qision2 deug mode differs from

t"e edit mode in t"e following aspectsH

h T"e F$eug %enu and $eug CommandsG descried on page 20 are Aailale5 T"e additional

deug windows are discussed in t"e following5

h T"e pro/ect structure or tool parameters cannot e modified5 All uild Commands are disaled5

Disasse)b"3 =in%o

T"e $isassemly window s"ows your target program as mi'ed source and assemly

program or /ust assemly code5 A trace "istory of preiously e'ecuted instructions may e

0



displayed wit" $eug M iew Trace Records5 To enale t"e trace "istory7 set $eug M

Enale$isale Trace Recording5

@f you select t"e $isassemly )indow as t"e actie window all program step commands

wor( on CP6 instruction leel rat"er t"an program source lines5 Dou can select a te't line and set

or modify code rea(points using toolar uttons or t"e conte't menu commands5

Dou may use t"e dialog $eug M @nline Assemly to modify t"e CP6 instructions5

T"at allows you to correct mista(es or to ma(e temporary c"anges to t"e target program you are

deugging5

SOURCE CODE

1. Clic( on t"e .eil uision @con on $es(top

2. T"e following fig will appear

#ig 32H pro/ect

$. Clic( on t"e Pro/ect menu from t"e title ar

&. T"en Clic( on !ew Pro/ect

0=



#ig 33H new pro/ect

*. Sae t"e Pro/ect y typing suitale pro/ect name wit" no e'tension in u r own foldersited in eit"er CH or $H

,. T"en Clic( on save utton aoe5

. Select t"e component for u r pro/ect5 i5e5 Atmel

/. Clic( on t"e Symol eside of Atmel

0



#ig 3, H select target deice6. Select AT0-C1 as s"own elow

#ig 3H select deice foer target17. T"en Clic( on F&.G

11. T"e #ollowing fig will appear

00



#ig 3=H Copy 0*1 startup code

12. T"en Clic( eit"er DES or !&mostly F!&G

1$. !ow your pro/ect is ready to 6SE

1&. !ow doule clic( on t"e Target17 you would get anot"er option FSource group 1G as

s"own in ne't page5

#ig 3H Source group 1

1*. Clic( on t"e file option from menu ar and select FnewG

0-



#ig 30 new file

1,. T"e ne't screen will e as s"own in ne't page7 and /ust ma'imie it y douleclic(ing on its lue oarder5

#ig 3-H &pened new file

1. !ow start writing program in eit"er in FCG or FAS%G

1/. #or a program written in Assemly7 t"en sae it wit" e'tension F5 asmG and for FCG ased program sae it wit" e'tension F 5CG

-*



#ig ,*H #ile Sae16. !ow rig"t clic( on Source group 1 and clic( on FA%% 8i"es to Gro!+ So!r#eG

#ig ,1H Add files to t"e source group

27. !ow you will get anot"er window7 on w"ic" y default FCG files will appear5

-1



#ig ,2H Adding files to t"e source group21. !ow select as per your file e'tension gien w"ile saing t"e file

22. Clic( only one time on option FADDG

2$. !ow Press function (ey # to compile5 Any error will appear if so "appen5

#ig ,3 Compilation2&. @f t"e file contains no error7 t"en press Control# simultaneously5

2*. T"e new window is as follows

-2



#ig ,,H uilding

2,. T"en Clic( F&.G

2. !ow Clic( on t"e Perip"erals from menu ar7 and c"ec( your re8uired port as s"own

in fig elow

#ig , H Selecting t"e Ports to e isualied

2/. $rag t"e port a side and clic( in t"e program file5

-3



#ig ,=Hstart deugging

26. !ow (eep Pressing function (ey F#11G slowly and osere5

$7. Dou are running your program successfully5

E)be%%e% C@

=-at is an e)be%%e% s3ste)K

An emedded system is an application t"at contains at least one programmale computer

and w"ic" is used y indiiduals w"o are7 in t"e main7 unaware t"at t"e system is computer4

ased5

=-i#- +rora))in "an!ae s-o!"% 3o! !seK

+aing decided to use an 0*1 processor as t"e asis of your emedded system7 t"e ne't (ey

decision t"at needs to e made is t"e c"oice of programming language5 @n order to identify a

suitale language for emedded systems7 we mig"t egin y ma(ing t"e following oserationsH

-,



• Computers 9suc" as microcontroller7 microprocessor or $SP c"ips: only accept

instructions in mac"ine codeJ 9o/ect codesJ:5 %ac"ine code is7 y definition7 in t"e

language of t"e computer7 rat"er t"an t"at of t"e programmer5 @nterpretation of t"e code

y t"e programmer is difficult and error prone5

• All software7 w"et"er in assemly7 C7 C7 \aa or Ada must ultimately e translated into

mac"ine code in order to e e'ecuted y t"e computer5

• Emedded processors M li(e t"e 0*1 M "ae limited processor power and ery limited

memory aailaleH t"e language used must e efficient5

• T"e language c"osen s"ould e in common use 5

S!))ar3 o8 C "an!ae Feat!res@

@t is mid4leelJ7 wit" "ig"4leelJ features 9suc" as support for functions and modules:7 and

low4leelJ features 9suc" as good access to "ardware ia pointers:5

• @t is ery efficient5

• @t is popular and well understood5

• Een des(top deelopers w"o "ae used only \aa or C can soon understand C synta'5

• Xood7 well4proen compilers are aailale for eery emedded processor 904it to 324it

or more:5

'asi# C +rora) str!#t!re@

4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4

Basic lan( C program t"at does not"ing

@ncludes

4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4

[include <reg15"> S#R declarations

oid main 9oid:

)"ile 91:I

-



Body of t"e loop @nfinite loop

!

! matc" t"e races

CONCLUSION

T"e pro/ect FFISCAL ACCESS SYSTEM USING RFID "as een successfully designed and

tested5 @ntegrating features of all t"e "ardware components used "ae deeloped it5 Presence of

eery module "as een reasoned out and placed carefully t"us contriuting to t"e est wor(ing of t"e unit5

Secondly7 using "ig"ly adanced @CJs and wit" t"e "elp of growing tec"nology t"e

pro/ect "as een successfully implemented

-=



REFERENCES

0*14%@CR&C&!TR&LLER A!$ E%BE$$E$ SDSTE%S5

%o"d5 %aidi5

T"e 0*1 %icro controller Arc"itecture7 Programming Applications

B4ennet- .A3a"a

#undamentals &f %icro processors and %icro computers

B'.Ra)

%icro processor Arc"itecture7 Programming Applications

BRa)es- S. Gaon(ar

Electronic Components

4D.. rasa%

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