3G The Evolution of the SDI

447722 SMPTE MMoottiioonn IImmaaggiinngg Journal, November/December 2006 • wwwwww..ssmmppttee..oorrgg

When television broadcast networks were first

established 70 years ago, video signals,

which were then analog baseband, were dis-

tributed on 75� coaxial cables and terminated with

BNC connectors.

Twenty years ago, when the video signal transitioned

to the serial digital interfaces (SDI) (SMPTE 259M),1 the

same 75� coax infrastructure was retained. Coaxial

cable has many advantages over other cable types,

including support for high frequencies, its physical

robustness, and simple connectivity.

As new facilities were built, higher grades of compati-

ble coaxial cable were introduced, resulting in facilities

with greater amounts of performance margin in their

cabling infrastructure. Ten years ago, when HD-SDI

(SMPTE 292M)2 was introduced, the existing cable was

once again retained.

Today, there is a need for even higher speed inter-

faces. Can this transition to a higher speed interface be

achieved while retaining the existing cable infrastruc-

ture?

Why a Higher Capacity Interface IsRequired

In North America, the dominant broadcast HDTV

standards are 720p/60 and 1080i/60. The European

Broadcast Union (EBU) has recently decided to support

both 720p/50 and 1080i/50 HDTV formats. It is probable

that many production facilities will want to distribute their

program material in both formats—perhaps broadcast-

ing in 720p but producing a DVD in 1080i.

This places many production facilities in a quandary

when trying to decide on a common production format.

One possible solution is to produce content in a 1080-

line progressive format, which can be easily converted

to either emission format with minimal quality degrada-

tion. In addition, there is a growing desire and need to

3G: The Evolution of the SerialDigital Interface (SDI)By John Hudson and Nigel Seth-Smith

SMPTE and the InternationalTelecommunications Union (ITU) haveboth recently adopted new standards fora 3-Gbit/sec (nominal) SDI interface using75�� coaxial cable and BNC connectors.The interest in these interfaces is drivenby a desire to be able to transport 1080-line progressive format video over a sin-gle-link interface, rather than the dual-linkinterfaces currently used. The implemen-tation of this interface with existing infra-structure components such as patch pan-els, connectors, coax cable types, andsuch, has been studied, and key compo-nents have been realized in silicon. Theresults of this work and key design guide-lines are discussed in this paper.

John Hudson Nigel Seth-Smith

Hudson.qxp 11/21/2006 2:13 PM Page 472

SMPTE MMoottiioonn IImmaaggiinngg Journal, November/December 2006 • wwwwww..ssmmppttee..oorrgg 447733

produce high-definition content at higher

bit depths (12 bits per component), and

to provide support for R'G'B' and 4:4:4:4

processing.

Another application that is driving the

need for a higher capacity interface is

digital cinema. For example, the pro-

posed SMPTE 428-x, “Digital Cinema

Distribution Master (DCDM) Image

Characteristics Level 3—Serial Digital

Interface Signal Formatting,” defines a

2048 x 1080p/24, 4:4:4 (X'Y'Z')/12-bit

format.3

Note: At time of writing, SMPTE 428-x

is in development within the DC28 tech-

nology committee.

Unfortunately, the bandwidth require-

ments to transmit these video formats

in serial digital form exceed the capabil-

ities of a single SMPTE 292M interface

(Fig. 1).

All of the above applications could be

addressed by using two or more SMPTE

292M 1.5-Gbit/sec links. Indeed,

SMPTE 372M4 provides a standardized method for the

carriage of such higher capacity signals over a dual-link

interface, providing an aggregate bandwidth of 2.97

Gbits/sec. However, such dual-link interfaces are very

expensive and awkward to implement.

The use of mezzanine compression would allow high-

er bandwidth signals to be squeezed into a single 1.5

Gbit/sec link. This mandates the addition of codecs at

every input and output. Except for cost considerations,

the compression scheme needs to be carefully

designed to minimize image degradation and latency.

The use of high-speed optical interconnect would

also provide sufficient bandwidth to address the above

applications and more. Although such interfaces are

technically feasible, they are still very expensive to

implement and require different capabilities, in terms of

system design, installation, and maintenance, com-

pared to the traditional coax and BNC infrastructure

common today.

The Ideal Transport Interface

SD and HD SDI have become the ubiquitous interface

standards within the professional broadcast industry,

and the success of SDI is due in no small part to a num-

ber of specific characteristics:

• Ability to transport uncompressed signals

• Low latency

• Cost-effective implementation

• Robustness and reliability

• Seamless interoperability

• Reuse of existing infrastructure

The last point has been one of the critical success

factors for SDI and is characterized by the ability of the

interface to evolve over time, while retaining the use of

the installed base of cabling, patch panels, and BNC

connectors. This characteristic is very important, as

much of the cabling in a facility is routed through walls

and conduits, making it prohibitively expensive to

change. An ideal higher capacity transport interface

should embody all of the characteristics identified

above, building on the evolutionary success of SD and

HD SDI.

To this end, new standards for a 2.97-Gbit/sec SDI

interface using 75� coax cable and BNC connectors

has now been adopted by both SMPTE (SMPTE 424M

and 425M) and the ITU (ITU-R-BT.1120-3-2005).5

3G: THE EVOLUTION OF THE SERIAL DIGITAL INTERFACE (SDI)

Figure 1. Required bit rate to transmit various video formats.

Figure 2. Insertion loss for 100 m of two different coax cable types.



3-Gbit/sec SDI Standards

ITU-R-BT.1120-3, “Digital Interfaces for HDTV Studio

Signals,” was revised in 2005 to include support for the

transmission of 1920 x 1080 50p and 60p Y'C'BC'R 4:2:2

10-bit data over a 2.970 or 2.970/1.001 Gbit/sec SDI

interface.

The 3-Gbit/sec interface standard from SMPTE is

defined in two documents: SMPTE 424M6 for the physi-

cal interface and SMPTE 425M7 for data mapping. The

SMPTE standards cover a wider scope of applications

than ITU-R-BT.1120-3, as shown in Table 1.

In addition to support for the above image formats,

SMPTE 425M also provides a standardized means to

transport two SMPTE 292M-compliant signals over a

single 3-Gbit/sec SDI interface.

In support of these standards, semiconductor devices

are now commercially available that enable a 2.97-

Gbit/sec SDI interface capable of operating over existing

HD-SDI cabling and plant.

3-Gbit/sec Cable Equalization

One of the major limiting factors for sending high-

speed data over copper cables is the skin effect, which

results in increased attenuation as the frequency of the

signal increases. Other factors such as dielectric loss

and impedance mismatches at connectors also limit

cable-length performance at high bit rates, but beyond

about 20 m or so at the frequencies being discussed in

this paper, losses are dominated by the skin effect. This

effect is due to the flow of AC currents mostly on the

surface (skin) of a conductor at high frequencies.

As a result of the skin effect, the insertion loss of a

piece of cable increases as the square root of the fre-

quency of the signal

it carries. Figure 2

shows the insertion

loss of a 100-m sec-

tion of two different

types of coaxial

cable used in broad-

cast applications.

To properly

receive a signal that

has traveled a length

of cable, a cable

equalizer must be

used. This device is

a filter with a frequency response that is the comple-

ment of the response of the cable. In most video appli-

cations, the equalizers used are “adaptive” in that they

automatically adjust the amount of equalization applied

to match the total loss in the cable to which they are

connected.

To design a cable equalizer that will recover a 3-

Gbit/sec signal after it has been attenuated by a length

of cable, a high-pass filter must be designed. Typically,

the high-pass filter realized has a frequency response

with a gradient of approximately 6 dB/octave. Careful

design with regard to the placement of the poles and

zeros of the filter is required to ensure that an approxi-

mation of the desired 1/root f response is achieved.

Figure 3 shows the equalizer frequency response,

along with the cable insertion loss for 100 m of coaxial

cable. As shown, the equalizer is able to compensate

for cable loss at frequencies greater than 1.5 GHz, thus

making it suitable to be used with 3-Gbit/sec data.

Despite the fact that the input signal is not completely

restored by the equalization filter, restoration is sufficient

to allow the DC restorer, digital slicer, and output buffer

of the device to recover the entire signal. This is illustrat-

ed in Fig. 4, which shows a screen shot of the input and

output of the GS2974 multi-rate (DC to 3 Gbits/sec),

adaptive cable equalizer. The diagram illustrates equal-

ization of 100 m of Belden 1694A cable with a data rate

of 3 Gbits/sec (PRN-23 signal).

3-Gbit/sec Data Re-clocking

As can be seen in Fig. 4, an equalized signal is not

necessarily a clean signal, since an equalizer does

nothing to remove jitter resulting from noise added on


Table 1—Source Image Formats Supported in the 3-Gbit/sec SDI Standards



the link. It would not be possible to use an

equalized signal to go any additional dis-

tance without first reducing the jitter.

Jitter reduction is typically accom-

plished using a data re-clocking circuit. A

SDI re-clocker needs to be specifically

designed to meet the unique requirements

of the interface. SDI signals are very dif-

ferent from other signals commonly found

in the datacom and telecom industries,

due to the data rates employed and other

unique signal characteristics (pathological

signals), resulting from the scrambling

polynomial defined in SMPTE 259M,

SMPTE 292M, and SMPTE 424M.

At the simplest level, a SDI data re-clocker provides

the means to extract a clock signal from the serial data

stream; to lock an extremely low-phase-noise voltage-

controlled oscillator to the extracted clock, using a

phase-locked loop (PLL); and to re-sample the serial

digital input signal with the low-noise clock source.

When designing a PLL for a SDI re-clocker, a tradeoff

must be made between the amount of jitter that can be

present on the input (input jitter tolerance or IJT) and the

amount of residual jitter that is output from the device.

Critical to system performance is the setting of the

lower band edge of the PLL loop filter or loop bandwidth

(LBW) of the re-clocking device. Generally, more jitter

attenuation is achieved by lowering the LBW, whereas

board and system noise immunity is achieved with a

higher LBW.

Another important factor to recognize is that the lower

the loop bandwidth, the longer it will take for the re-

clocker to lock to the incoming source. This is especially

important where source

switching, for example, in a

router, is employed. Taking all

of these factors into account, a

good compromise is to set the

re-clocker LBW between 500

kHz and 2 MHz, with 1.4 MHz

being optimal for the majority

of serial routing and distribu-

tion applications.

In multi-pass systems in

which the SDI signal is cas-

caded within a facility, jitter

can accumulate from unit to unit. The LBW of the receiv-

er at each subsequent unit must therefore be wide

enough to accommodate the accumulated jitter. Ideally,

the re-clocking device should automatically adapt its

LBW in accordance with the input jitter; otherwise it may

be necessary to optimize each receiver in the system at

the time of installation. This kind of functionality is diffi-

cult to achieve with a traditional linear PLL-based re-

clocking device; however, other techniques such as the

slew PLL can be employed to achieve this requirement.

Figure 5 compares the jitter attenuation performance

of a linear and a slew PLL. For a fair comparison, the

phase slew of the slew PLL and LBW of the linear PLL

are chosen such that at 0.2 UI (Unit Interval), input jitter

modulation, both achieve 3 dB attenuation at 1.4 MHz

modulation frequency.

The jitter transfer function is plotted at 2.8 MHz to

show how the PLL attenuates input jitter at higher fre-

quency. It can be seen that the output jitter of the slew


Figure 3. Cable insertion loss and equalizer gain.

Figure 4. Input and output of equalizer after 100 m of Belden 1694A cable with a datarate of 3 Gbits/sec.



PLL attains a maximum and then it is limited. This is an

attribute of the nonlinearity present in the slew PLL.

In summary, a slew PLL achieves higher jitter attenu-

ation in the presence of large input jitter, while providing

small signal VCO/board noise immunity. The capabilities

discussed above are especially important in systems

operating at the higher data rates of the 3-Gbit/sec SDI

interface as system jitter margins are significantly

reduced.

Figure 6 shows a screen shot of the output of the

GS2975—a multi-rate to 3-Gbit/sec slew PLL re-clocker.

The diagram illustrates a re-clocked 3-Gbit/sec PRN-23

signal after 100 m of equalized Belden 1694A cable.

Figures 7 and 8 show an 11-stage multi-pass configu-

ration. In this demonstration, off-the-shelf cabling, con-

nectors, and a patch panel were combined with 10 pro-

totype re-clocking distribution amplifiers and a prototype

3-Gbit/sec router to represent a system installation. The

3-Gbit/sec FPGA-based SDI signal generator in this

system is locked to an NTSC black burst reference

using a GS4911B genlock and a GS4915 clock-cleaning

device.

Just visible in the background of Fig. 8 is a clean and

open eye from the serial digital output of the last pass in

the system, illustrating 0.25 UI alignment jitter after 11

passes.

3-Gbit/sec SDI Transmitter

SMPTE 424M defines the signal characteristics for a

compliant 3-Gbit/sec SDI transmitter, and in many

respects, the 3-Gbit/sec SDI standard is very similar to

the 1.5 Gbit/sec HD SDI standard.

Because of the higher data rate of the 3-

Gbit/sec SDI interface, certain parameters such

as rise/fall time, output return loss, and align-

ment jitter could prove to be challenging from a

system design perspective.

As long as some basic guidelines are fol-

lowed; however, (described later) designing a

SMPTE 424M-compliant transmitter should not

be any more onerous than designing a SMPTE

292M-compliant transmitter. No new or special

design techniques are required, and commer-

cial silicon is now available that greatly simpli-

fies the task.

Careful design of the transmitter, however, is

paramount to good system performance, and

perhaps one of the more challenging aspects of

SMPTE 424M is the output jitter specification.

Although it is not the intent of this paper to present a

detailed system jitter analysis, it is worth discussing

some general rules of thumb and good engineering

practice.

Transmit Jitter Template

The jitter template shown in Fig. 9 is derived from the

parameters defined in SMPTE 424M.

According to the diagram in Fig. 9, the source should

produce no more than 2 UI (673 ps) timing jitter in the

frequency band from 10 Hz to 15 kHz.

Between 15 kHz and 100k-Hz, the timing jitter tem-

plate rolls off at a slope of 20 dB per decade. The align-

ment jitter should be no more than 0.3 UI (101 ps) in the


Figure 5. Transfer functions of linear and slew PLLs.

Figure 6. 3-Gbit/sec signal after 100 m of cable, equaliza-tion, and re-clocking.



frequency band beyond 100 kHz. SMPTE

424M defines the alignment jitter from 100

kHz to something greater than 1/10th the seri-

al clock frequency. It is very important to

make sure that this parameter is met up to

1.485 GHz, as jitter, due to duty cycle distor-

tion in the transmitter, may appear at half the

serial-clock frequency.

Low-frequency or timing jitter is generally

“outside the loop bandwidth” of SDI data

recovery devices. The PLLs in a well-

designed SDI re-clocker can typically accom-

modate (track or pass) up to about 10 UI of

timing jitter before the onset of signal errors.

In de-serializers—depending on the design—

the timing jitter margin can be even larger, due

to the serial-to-parallel conversion and the use

of parallel data FIFOs and buffers.

In general, timing jitter is of little concern in

SDI systems. However, designers should be

aware that timing jitter will accumulate at each

“pass” in a serial digital system; thus it is high-

ly recommended that positive action is taken

to attenuate accumulated timing jitter in

receiver designs and to minimize the genera-

tion of timing jitter in transmitter designs. This

is discussed further in the following sections.

Alignment jitter has a much more powerful

impact on system performance and must be

tightly controlled to achieve the expected SDI

bit error rate of at least 10-12. Having only

101 ps of alignment jitter places strict

demands on the transmitter design.

Sources of Alignment Jitter

Bandwidth-limited devices in the signal

chain, such as cable drivers, cable equal-

izers and cross-point switches, serial digi-

tal muxes, and buffers, all add jitter.

Impedance discontinuities through con-

nectors and transmission line stubs (lead-

ing to signal reflections), cross talk, and

noise coupling also contribute to jitter.

In all of the above cases, the jitter effect

is due to some form of signal distortion

and cannot be completely eliminated.

Thus, the jitter introduced from these

effects can be considered systematic and


Figure 7. Block diagram of multi-pass configuration shown in Fig. 8.

Figure 8. 11-stage multi-pass 3-Gbit/sec SDI configuration.

Figure 9. Jitter template for SMPTE 424M.



cumulative (arithmetically additive).

Note that in some cases, the jitter so produced could

be considered subtractive; however, to build a robust

system, designers should consider systematic jitter to

be purely additive when deriving a jitter budget.

Pathological signal patterns, which are unique to

SMPTE signals, can cause poorly designed standard

PLL circuits to introduce jitter and bit errors. This is

especially true for data recovery circuits, which extract

clock from data and are inevitably pattern dependent.

The noise in a PLL circuit designed for a serializer

device is generally not pattern dependent, because the

PLL locks on to a reference clock. However, these

devices can be very sensitive to board and power sup-

ply noise, which in turn can be data pattern dependent;

thus the serializer will also be a source of both system-

atic and pattern dependent (random) jitter.

The jitter generated in even a very careful design can

very quickly become significant at 3 Gbits/sec. This

means that special attention is required in the design of

the system reference clock and serial-to-parallel/paral-

lel-to-serial conversion circuitry.

Example Jitter Budget Calculation—Receiver

Consider the notional equipment block diagram in Fig.

10. Assuming a 3-Gbit/sec SDI source operating at the

maximum allowable limits of SMPTE 424M and worst-

case operating conditions, it can be seen that to achieve

robust system performance, an IJT of approximately 0.6

UI is required.

The LBW of the de-serializer should be chosen

between 3 MHz and 6 MHz to accommodate multi-pass

system jitter accumulation and to provide margin for pat-

tern-dependent jitter caused by pathological signals.

Example: If the receiver’s LBW is 4.2 MHz and the

input source is provided by the output of a router with a

LBW of 1.4 MHz, the receiver will follow the jitter of the

router during pathological video lines. The phase at the

re-clocker in the router with an LBW of 1.4 MHz slews

slowly so that a 4.2-MHz receiver will closely track the

signal without introducing bit errors, even allowing for

worst-case manufacturing tolerances and operating con-

ditions.

A number of different FPGA vendors now offer

devices with built-in high-speed transceivers. These

devices provide a flexible and popular choice when

implementing 3-Gbit/sec SDI de-serializers. It should be

noted, however, that these devices may not provide suf-

ficient IJT margin or a low enough LBW to accommo-

date the jitter budget shown in Fig. 10. Therefore, it is

recommended that receivers include a 3-Gbit/sec SDI

re-clocker in front of an FPGA-based de-serializer, to

ensure that the IJT can be achieved. Ideally, a re-clock-

er should be provided at each input, immediately follow-

ing the input equalizer.

It should also be noted that there is very little timing or

alignment jitter attenuation of the processor clock output

of the de-serializer, resulting in at least 1 UI (~336 ps) of

alignment jitter on the parallel interface. This clock jitter

can be further compounded within the parallel process-

ing domain of the equipment, with up to 3 UI of jitter (~1

nsec), typical unless care is taken with clock distribution

in the design.

Although this is a concern when calculating set-up

and hold-time margin between parallel processing

devices, it is generally not a major problem in terms of

system operation. However, this clock should never be


Figure 10. Notional equipment block diagram.



used to directly drive an SDI serializer unless that serial-

izer is able to filter the jitter using a VCXO/PLL.

Example Jitter Budget Calculation—Transmitter

The diagram in Fig. 10 shows a clean transmit clock

source-genlocked to a house reference.

The specification for a typical synchronization signal

is defined in SMPTE 318M8 and a genlock circuit utiliz-

ing a VCXO should be used with very low LBW (<10

Hz), to ensure that the recovered parallel clock meets

both the timing and alignment jitter requirements of

SMPTE 424M. However, this low-loop bandwidth does

make the PLL susceptible to board-generated noise, so

special care needs to be taken with power supply de-

coupling of the genlock circuitry, etc.

Of course, the jitter on the genlock-generated parallel

clock should be much better than the SMPTE specifica-

tions to accommodate jitter accumulation at the output

of the serializer (typically 0.15 UI or 50 ps). By choosing

proper LBW or phase slew for the genlock circuit and

employing careful design techniques, the phase drift of

the generated clock over one video line can be as low

as 15-20 ps.

Due to the clean reference clock available, the jitter

attenuation requirements of the PLL within the serializer

can be greatly relaxed. This makes a transceiver-based

FPGA device eminently suitable as a 3-Gbit/sec SDI

serializer.

One of the disadvantages of a VCXO-based genlock

design is that the clock frequency it generates is gener-

ally fixed to a single rate. If a piece of

equipment is required to address multi-

ple rates, then multiple VCXO/PLL-

based genlock circuitry is required,

which can be costly to implement.

Generic digital clock generators using

techniques such as direct digital synthe-

sis (DDS), can be used to provide a

greater level of flexibility. However, the

clock signals produced by such devices

generally have very poor high-frequency

jitter performance. While these clock

generators are adequate for parallel

domain processing, they are not suit-

able for 3-Gbit/sec SDI transmitters.

Semiconductor devices such as the

GS4911B and the GS4915 are

designed specifically to address the timing and clock

generation requirements for professional broadcast

equipment. These devices provide the flexibility of digital

clock generators with the very low alignment and timing

jitter available from VCXO/PLL-based designs. Such

devices greatly simplify the task of creating a suitably

clean clock signal for 3 Gbit/sec SDI transmitters.

Figure 11 shows the jitter spectrum of the GS4911B

timing generator and the GS4915 clock-cleaner. In this

diagram, the clock signal generated is gen-locked to a

NTSC black burst reference with a LBW of <10 Hz.

With careful design and the selection of suitable com-

ponents, it is possible to develop a 3-Gbit/sec SDI trans-

mitter with <0.2 UI jitter, which meets the SMPTE 424M

jitter requirement with margin.

3-Gbit/sec SDI Basic Design Guidelines

When designing a transmitter or receiver system to

meet the SMPTE 424M requirements, many different

factors must be considered, such as jitter margin, print-

ed circuit board (PCB) layout, matching network design,

and component choice. To meet basic AC and DC elec-

trical characteristics, special attention must be paid to

component layout when designing 3-Gbit/sec serial digi-

tal interfaces.

FR-4 dielectric material can be used for PCB design.

However, controlled impedance transmission lines are

required for any high-speed signal trace longer than

approximately 1 cm. Furthermore:

• The PCB trace width for 3-Gbit/sec rate signals


Figure 11. Jitter spectrum of the GS4911B genlock and GS4915 clock cleaner.



should be closely matched to any surface-mount com-

ponent widths to minimize reflections due to changes in

trace impedance.

• The PCB ground plane should be removed under

the input or output matching network components to

minimize parasitic capacitance.

• Wherever possible, the input or output BNC connec-

tors should be mounted in-line and as close as possible

to the cable driver or cable equalizer.

• Special attention should be paid to power supply,

noise filtering, and power and ground plane isolation for

all high-speed and VCO/VCXO/PLL circuitry.

• Surface-mount components and connectors should

be used wherever possible to eliminate the possibility of

transmission line stubs caused by through-hole compo-

nents or PCB vias.

Note that these same guidelines are equally applica-

ble to SD SDI and HD SDI designs.

Most semiconductor manufacturers provide applica-

tion circuits and PCB layout guidelines in the data

sheets of their products. In addition, specific application

notes and tutorials are also available. This information

greatly simplifies the task of creating a fully compliant

design with optimal performance.

3 Gbit/sec Transmitter Return Loss

SMPTE 424M specifies a transmitter return loss of

better than 10 dB between 1.485 GHz and 3 GHz and

better than 15 dB from 5 Mhz to 1.485 GHz.

There are many factors that must be considered

when designing to meet these return loss requirements

and the designer must constantly

trade off return loss performance

with the quality (niceness of eye) of

the transmitted signal.

While it is never easy to make a

necessary design tradeoff such as

PCB layout; matching network

design; component and connector

choice, the limiting factor in any

design usually ends up being the

performance of the semiconductor

device used to drive the cable.

A SDI cable driver needs to be

specifically designed to meet the

unique requirements of the interface

and this is especially true at 3

Gbits/sec. Drivers specified for use

in the datacom/telecom industry are not optimized for

operation in 75� environments, nor are they designed

to meet the rise and fall time characteristics of the SDI

interface.

To simplify the task of meeting the return loss require-

ments of SMPTE 424M, it is recommended that a dedi-

cated 3 Gbit/sec SDI cable driver should be selected.

Figure 12 shows a plot of the return loss from DC to 3

GHz for the GS2978 cable driver. The measurement

includes the effects of the matching network, recom-

mended PCB layout, and BNC connector. It can be

seen that the SMPTE 424M return loss specification is

achieved with considerable margin.

3-Gbit/sec Connectors, Cabling, and PatchPanels

SMPTE 424M specifies the use of a 75� BNC con-

nector with the mechanical characteristics defined by

IEC 60169-8 Amendment 2, 1997, Annex A.9

Mechanically, this is the same connector specified for

all other SDI interfaces. Furthermore, SMPTE 424M

specifies a return loss of better than 10 dB between

1.485 GHz and 3 GHz and better than 15 dB from 5

Mhz to 1.485 GHz.

Manufacturers specialize in the design of mechanical-

ly and electrically compliant 75� BNC connectors and

patch-panels specifically for HD SDI interfaces. At the

time of writing, however, few of these manufacturers—

with a couple of notable exceptions—publish specifica-

tions such as return loss beyond 2 GHz.


Figure 12. Return loss of the GS2978 cable driver.



A quick phone call is all that is generally required to

elicit the fact that their products are typically character-

ized and tested beyond 3 GHz and easily meet the

SMPTE 424M requirement of greater than 10 dB at 3

GHz with significant margin. Typically, connectors are

available with 5 to 15 dB return loss margin, with

respect to SMPTE 424M requirements.

Connector and patch panel manufacturers are

encouraged to make their extended performance para-

meters more readily available.

Coaxial cable manufacturers have been making prod-

ucts that exceed the SMPTE 424M return loss require-

ments for many years. Typically, any facility specifically

designed for HD SDI will already provide sufficient per-

formance to meet the requirements defined in SMPTE

424M.

If in doubt, system designers and installers are rec-

ommended to contact their cable suppliers to check for

compliance to SMPTE 424M, as few, with one notable

exception, currently publish data up to and beyond 3

GHz, even though their product is fully compliant.

Again, cable manufacturers are encouraged to make

their extended performance parameters more readily

available.

Conclusion

The need exists for a higher speed serial digital inter-

face to transport uncompressed 1080-line progressive

signals and other high-definition formats, including digi-

tal cinema formats, within a studio environment. New

standards have been adopted by the ITU-R and SMPTE

that specify a serial digital interface that operates up to

2.970 Gbits/sec, satisfying these requirements.

Semiconductor providers have developed silicon

specifically designed to enable the reuse of the existing

installed infrastructure of cabling, connectors, and patch

panels, making the 3-Gbit/sec interface both technically

and economically feasible to implement.

References1. SMPTE 259M-2006—Television, “SDTV Digital Signal/

Data–Serial Digital Interface,” www.smpte.org.

2. SMPTE 292M-1998—Television, “Bit-Serial Digital

Interface for High-Definition Television Systems,”

www.smpte.org.

3. SMPTE 428-x, “Digital Cinema Distribution Master (DCDM)

Image Characteristics Level 3—Serial Digital Interface

Signal Formatting.”

4. SMPTE 372M-2002—Television, “Dual Link 292M

Interface for 1920 x 1080 Picture Raster,” www.smpte.org.

5. ITU-R BT.1120-3 (2005) Digital Interfaces for HDTV Studio

Signals.

6. SMPTE 424M-2006—Television, “3 Gb/s Signal/Data

Serial Interface,” www.smpte.org.

7. SMPTE 425M-2006—Television, “3 Gb/s Signal/Data

Serial Interface—Source Image Format Mapping,”

www.smpte.org.

8. SMPTE 318M-1999—Television and Audio, “Synchroniza-

tion of 59.94- or 50-Hz Related Video and Audio Systems

in Analog and Digital Areas—Reference Signals,”

www.smpte.org.

9. IEC 60169-8 Amendment 2, 1997, Annex A.

Acknowledgments

The authors would like to thank the Electronics

Division of Belden CDT for furnishing coaxial cable

information. They would also like to thank their col-

leagues for their contributions to this work and to

Gennum Corporation for permission to publish this

paper.


Presented at the SMPTE and VidTrans Joint Conference, Hollywood, CA,Jan. 29-Feb. 1, 2006. Copyright © 2006 by SMPTE.

THE AUTHORS

John Hudson is senior manager of new product definition

in the Video Products Division of Gennum Corp., where he

is responsible for the definition of semiconductor devices

for serial data transport, image processing, system timing,

and analog and digital A/V interfaces. He is also Gennum’s

representative for international standardization and actively

contributes to the SMPTE standardization process. Prior to

joining Gennum in 1999, Hudson worked for 14 years at

Sony Broadcast and Professional Europe, as a design

engineer/principal design engineer in the Systems Product

Development Group.

Hudson received a Higher National Diploma in electron-

ics and communications systems engineering from

Farnborough College of Technology in 1986 and began his

career as an electronics technician apprentice at the

Military Vehicle Engineering Establishment in Chobham,

England.

Nigel Seth-Smith graduated from Southampton University

in 1974, and first digitized a video signal at the IBA in 1977.

Since then, he has led design departments at Scientific-

Atlanta, DPS, and Snell & Wilcox, before moving to product

definition at Gennum in 2002. He recently moved to

Lymington and so has, almost inevitably, taken up sailing.


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