3gpp W-cdma Systems

7/31/2019 3gpp W-cdma Systems

1/9

ideband code division multiple access (W-CDMA) canpresent many engineering design and verificationchallenges, due to its physical layer complexity as wellas complexities that can arise when integrating RF and baseband designsto achieve a working system.Systemdesignengineers typicallyhave the task of interpretingstandards specifications, first for partitioning subsys-tem requirements, then verifying that the end-to-endsystem design (typically including both baseband andRF designs) will meet specifications when they are fi -nally integrated. This article considersa case study thatillustrates the importance of simulating baseband andRF designs together to accomplish this task. Spe -cifically, a conceptual system design that includes sys-temmodels,a fixed-point finite impulse response (FIR)filter, and transistor-level circuit design is simulated

G. Jue is with Agilent EEsof EDA in Spokane, Washington, USA.

56 June 2002IEEEmagazine

ISSN 1527-3342/02/$17.002002 IEEE

E Y E W

I R E


2/9

and verified together against measurements defined inthe third-generation partnership project (3GPP)W-CDMA standards specifications. Tradeoffs betweenimproving either the RF or baseband design to meetoverall system specifications will be discussed. Finally,design verification usingconnected solutions, orconnectivity between,

electronic design auto-mation (EDA) softwareand test equipment will be described, illustratinghow verification testingcan be started earlier tohelp reduce risk by identify-ing performance issues earlyin thedesigncycle,when theyare potentially easier and lesscostly to implement.

3GPP W-CDMA Designand Verification ChallengesNewly emerging wireless signal formats, such as3GPP W-CDMA, can present significant design chal-lenges to the system design engineer. Typically, speci-fications are still evolving when the design cyclestarts, so the system design engineer must track

changes as the 3G specification evolves. Furthermore,3G technologies, suchas 3GPP W-CDMA, are complextechnologies, and much time can be spent just study-ing and understanding the specifications. Whilestudying and tracking evolving 3G specifications, the

system design engineer must,at thesame time,be ableto perform system tradeoffs, define RF and basebandsubsystem requirements, and ensure that the designwill work when it is finally put together. This can be adifficult design and verification challenge, particu-larly when RF and baseband engineers can be twodifferent design groups, perhaps using different de-sign tools. In addition, it is often important for RF

June 2002 57

IEEE magazine

Open ACLR/REMSchematic; CreateBehavioral Design;Evaluate System

Performance

Modify BehavioralDesign to Meet Specs.;Define Design Reqmts.

Design RF Transistor-Level Circuits and

Baseband Section;Insert RF and Baseband

Designs into SystemDesign to Evaluate

System Performance

Use EDA-Test Equip.Connected Solution to

Create Real-WorldTest Signal

Use EDA-Test Equip.Connected Solution to

Bring DUT SignalBack into Simulationfor Further Analysis

I

I

I

I

I

Select 3GPPW-CDMA Spec.; Open Corresponding SchematicReplace Placeholder in Schematic with Desired System DesignDesign Sys. with RF Behavioral Elements-Specify Gain, P1dB, 1P3, etc...for RF PerformanceUse 3GPPW-CDMA Source to Provide Baseband FunctionalitySimulate and Evaluate System Performance Against Specs.

I

I

Modify Gain, P1dB, IP3, etc...of RF Behavioral Elements Until System Design Meets Specs.Use Resulting Gain, P1dB, IP3, etc...Parameters as RF Circuit Design Requirments

I

I

I

I

I

I

I

Design RF Circuits and Baseband SectionsInsert Transistor-Level Circuits(s) into System DesignVerify if System Design Still Meets Specs. with Transistor-Level Circuit Design(s)Insert Baseband Design into System DesignVerify if System Design Still Meets Specs. with Baseband and RF DesignsTune System/Circuit/Baseband Design(s) until System Design Meets Specs.Use Final Tuned Parameter to Refine Baseband and RF Design Requirements

I Use Connected Solution to Create Real-World Test Signal on Test Bench for EarlyVertification Testing of DUT on Test Bench

I Model Baseband and RF Impairments at Input of DUT in Simulation

I Evaluate DUT Performance with Test Signal Containing Baseband and RF DesignImpairments of Test Bench

I

I

Use Connected Solution to Bring Measured DUT Test Signal into Simulation from Test BenchPerform Fur ther Analysis in Simulation by Modeling System Design at Output of DUT

Figure 1. An example of the design flow used in the case study.

Newly emerging wireless signalformats can present significant designchallenges to the systemdesign engineer.


3/9

and baseband designs to progress in parallel for fastertime-to-market, making system performance interac-tions and potential problems between RF and base-

band sections more difficult to verify and fix untilprototype designs are completed and tested together.

This highlights the need to provide RF and baseband design and verification capability in one EDAen-vironment to allow RF/baseband tradeoffs to be

examined at a system level and support rapid paralleldesign cycles by verifying overall system performanceas both the RF and baseband teams complete their de-signs. Design verification can be further enhanced byconnecting EDA software to test equipment (con-nected-solutions) to create real-world test signals thatreflect the effects introduced by RF and baseband de-signs, facilitatingearly verificationtesting of hardware.

Case Study: Verifying Baseband and RFDesigns Together in a Conceptual3GPP W-CDMA System DesignThis case study will illustrate the importance of verify-ing RF and baseband designs together in the EDA sim-ulation environment early to help minimize time-consuming and potentially costly design iterationslater in the design/fabrication cycle. The designs pre-sented in this case study are conceptual designs andarenot intended to represent an actual implementation,rather, their purpose is to facilitate this case study.

The example design flow used in this case study isillustrated in Figure 1. It begins by putting together asystem design using behavioral elements, where pa-rameters such as RF gain, 1-dB compression point,third-order intercept point, and other parameters can

be specified to approximate the RF system performanceof the design. The behavioral element parameters canthen be adjusted as necessary until the system designmeets the system design specifications, at which timethey can also serve as design requirements for design-ing individual transistor-level circuits. The RF transis-tor-level circuit designs, once completed, can then beinserted back into the system-level design to verify if the system still meets design specifications with thecompleted circuitdesign(s).Similarly, the baseband de-

signs, once completed, can also be inserted back intothe system-level design to verify system performancewith both baseband and RF designs present. If overallsystem performance does not meet design specifica-tions with both the baseband and RF designs consid-ered, tuning can be used to modify system, baseband,and RF designs as needed until the system meets speci-fications. The final tuned baseband/RF design parame-

ters could then be used as refined design requirementsfor the baseband and RF sections. Early verificationtesting of the device-under-test (DUT) is facilitated us-ing an EDA-test-equipment-connected solution tomodel the baseband and RF impairments at the DUTinput to create a real-world test signal on the test

bench to begin early hardware verification testing of the DUT. Simulated results can then be compared tomeasured results at this stage in the design flow, andthesystem designcan be modified, if needed, to resolveany potential issues found in early verification testing.An EDA-test-equipment-connected solution is thenused to bring the measured signal at the output of theDUT from the test bench back into simulation for fur-ther analysis. The DUTs output signal can be passedthrough the remainder of the system design, modeledin simulation to verify the simulated system perfor-mance with the DUTs measured signal.

To begin the case study, a preliminary user-equip-ment uplink design is created consisting of an uplink3GPP W-CDMA signal source, RF mixer and filter,driver amplifier, power amplifier and RF duplexer, withadjacent channel leakage ratio (ACLR) and error vectormagnitude (EVM) measurements (Figure 2). Behavioral

blocks are used at this stage of the design to determinedesign parameters such as gain, 1-dB compressionpoints, third-order intercept points, etc., for the mixerand amplifiers to meet the 3GPP design specifications.The behavioral design parameters for the system designare tuned to meet the 3GPP W-CDMA requirements

G output power: +24 dBm maximum, +1/ 3 dB tol-erance

G spreading rate: 3.84 MCpsG ACLR: 33 dB or better at 5 MHz frequency offsetG ACLR:43dB orbetter at10 MHz frequency offset

58 June 2002

IEEE magazine

Preliminary 3GPP W-CDMA System Design with Behavioral Elements

3GPP

W-CDMASignal Source RF UpconverterDriver

AmplifierPower

Amplifier Tx/Rx DuplexerACLR and EVMMeasurements

Simulation Variables Design Variables

Figure 2. Preliminary system design using behavioral elements and simulation results.


4/9

G error vector magnitude (EVM): 17.5% max.Thepreliminary systemdesign meeting the above de-

sign requirements and the simulation results are showninFigure 2.The RFoutput poweris24.2dBm,withanup-per channel ACLR of 34.9 dB at a 5 MHz offset, and 69.4dBat a 10MHz offset. Simu-lated EVM is 3%.

At this point in the

design cycle, the sys-tem engineer couldperform what-if trade-off scenarios to deter-mine the design require-ments for each of the in-dividual blocks compris-ing the design. Design pa-rameters, such as RF gain,1-dB compression point,third-order intercept point,and others, can be determined and allocated as designrequirements at the individual block level. As the de-signs for the individual blocks are completed, they can be inserted back into the system-level simulation toverify that the overall system performance is main-tained as the design cycle progresses.

To illustrate this, an existing transistor-leveldesignof a driver amplifier is inserted back into the system-leveldesign to verify that the design performance still meetsthe original design specifications when reusing this de-sign.Figure 3 shows thesystem-levelsimulation after re-placing the original behavioral driver amplifier with thetransistor-level circuit design. The simulation showsthat the system still meets the original design require-

ments. The RF output power is 24.4 dBm, with an upperchannel ACLR of 34.8 dB at a 5-MHz offset and 69.6 dBat a 10-MHz offset. Simulated EVM is 3.1%.

This verification process may be repeated as each of theindividual block designs are completed to verifysys-tem-levelperformanceof circuitdesigns continuously asthe design cycle progresses or to verify the performance

of existing designs against new signal formats. This canidentify potential systemperformanceproblems earlyinthe design cycle, where the time-to-market and cost im-pact may be less significant, compared to reworking de-signs later in the testing phase.

While design verification, so far, has focused on theRF design, it is useful to consider that the baseband de-sign canalsohave an impact on RF systemperformancemetrics such as bit error rate/block error rate(BER/BLER), ACLR, and EVM.

Pushing into the 3GPP W-CDMAuplink simulationsignal source (Figure 3) shows the baseband physicalchannel structure for the uplink source. In this exam-ple, the data-traffic channel (DTCH) and data-controlchannel (DCCH) are channel coded, convolutionally(or turbo) coded, and interleaved. The DTCH uses20-ms frames. At the frame segmentation point, theDTCH is split into two parts for the physical layers10-ms frame structure. The DCCH that operates with

40-ms frames is split into four parts so that each signal-ing frame is spreadover four 10-msradioframes.Thesechannels are then rate matched and multiplexed to-gether prior to spreading. The multiplexed data at thispoint is called the coded composite transport channel(CCTrCH). After a second interleaving, the CCTrCH ismapped onto a dedicated physical data channel

June 2002 59

IEEE magazine

3GPP W-CDMA System Verification with Transistor-Level Circuit Design3GPP

W-CDMASignal Source RF Upconverter

DriverAmplifier

PowerAmplifier Tx/Rx Duplexer

ACLR and EVMMeasurements

Simulation Variables Design Variables

Figure 3. System verification with transistor-level circuit design and simulation results.

Design issues can be caught early in thedesign cycle, where they are potentially less time-consuming and less costly tofix than later in the testing phase.


5/9

(DPDCH) running at 60 kb/s. The DPDCH is spreadwith an orthogonal variable spread factor (OVSF) codewith spread factor (SF) equal to 64 to reach the desired3.84 Mcps. After gain scaling (to adjust the transmis-sion power for the varying spread factor), the spreadDPDCH is applied to the I channel. The dedicatedphysical control channel (DPCCH) data is spread withan OVSF code with SF = 256 to reach the 3.84 Mcps rate

and is gain scaled relative to the DPDCH. The DPCCHis then applied to the Q channel. The scramble codegenerator is used to provide the unique channelizationrequired for each mobile station.

The signal source functionality described in Figure 4provides baseband functionality as a placeholder forthe actual baseband implementation to help support a

parallel RF design cycle. Much like the RF behavioralelements used to put together the preliminary RF de-sign, these baseband blocks can provide basebandfunctionality so that BER/BLER can be simulated at asystem level. These baseband blocks could be replacedwith custom designs using hardware description lan-guage (HDL) code as they are completed for sys-tem-level verification. Replacing the baseband blocks

with HDL code could be analogous to replacing the be-havioral driver amplifier with the RF circuit design forsystem level verification.

The baseband and RF designs could be designed bydifferent groups of engineers, possibly even with dif-ferent EDA design software. It can be useful to verifythe system-level performance with both the baseband

60 June 2002

IEEE magazine

The simulation signal source providesbaseband functionality for convolutional/turbo coding,

timeslot, and framing structure.Signal_SourceSignalPower=SignalPowerFCarrier=F_Freq

Figure 4. Inside the uplink simulation signal source.

3GPP W-CDMA System Verification with Transistor-LevelCircuit Design and Fixed Point FIR Design

3GPPW-CDMA

Signal Source RF UpconverterDriver AmplifierCircuit Design



n Variables DesignVariables

Figure 5. System-level verification with the fixed-point FIR and transistor-level circuit design and simulation results.


6/9

designs and RF designs present in the top-level systemdesign as they are competed.

To illustrate this, a 49-tap fixed-point FIR root-raised cosine filter is designed for an alpha of 0.22,and the bit-width is set to 8 b. The FIR fixed-point de-sign is inserted into the system design, along with thetransistor-level RF circuitdesign previously dis-

cussed. The schematicand simulation resultsare shown in Figure 5.As can be seen, the sys-tem nolongermeets theoriginal design specifi-cations. The RF outputpower is 24.4 dBm, withan upper channel ACLRof 31.9 dB at a 5-MHz offsetand 37.6 dB at a 10-MHz off-set. ACLR has degraded sig-nificantly due to the limited 8-b bit-width of thefixed-point FIR design. EVMhas not degradedsignifi-cantly at 4.4%.

The system design, containing both the basebandFIR design and transistor-level circuit design, can now be modified as necessary to meet the 3GPP W-CDMAdesign specification. The bit-width of the FIR, third-or-der intercept points of the mixer and 1-dB compressionpoint of the power amplifier are tuned/adjusted untilthe system meets design specifications. The resultingdesign and simulation results are shown below in Fig-

ure 6. It is interestingto note that systemengineers canoptimize or modify the design with an overall mixed

baseband/RF system perspective in mind and effec-tively trade off increasing either the dynamic range of the RF section (1-dB compression or third-order in-tercept point) or the dynamic range of the baseband

section (FIR bit-width) to meet design specifications.This mixed RF/baseband design and verification can

be useful in performing design trade-offs, not only forperformance, but also for design costs and implemen-tation risks by determining where the improvement(basebandversus RF) shouldbe made. The final designafter tuning the bit-width, mixer third-order interceptpoint, and power amplifier 1-dB compression point re-sulted in an RF output power of 24.5 dBm, with an up-per channel ACLR of 34.6 dB at a 5-MHz offset and 49.2dB at a 10-MHz offset. Simulated EVM is 3.9%.

IEEE magazineJune 2002 61

Final 3GPP W-CDMA System Design with Transistor-LevelCircuit Design and Fixed Point FIR Design

3GPPW-CDMA




tion Variables Design Variables

Figure 6. Resulting system design with fixed-point FIR and transistor-level circuit design after tuning to meet ACLR andEVM requirements.

EDA connectivity to test equipment canbe used to enhance design verificationthroughout the design cycle by modeling real-world signals insimulation and turning them into RFtest signals on the testbench.


7/9

Early Verification Testing with ConnectedSolutions between EDA and Test EquipmentTheFIR bit-widthrequired to meet theACLR andEVMspecification is 11 b with 49 taps. At this point, the sys-tem design has been completed in simulation with be-havioral system elements, a transistor-level circuitdesign, and a fixed point FIR filter baseband design.The baseband designer can use this information fromthe systemengineer to refine/redesign the filter forop-timal performance and insert the filters HDL imple-mentation into the system simulation for additionalverification. Likewise, the resulting gain, 1-dB com-pression point, and third-order intercept point for the

behavioral system elements can be used as design re-quirements for individual RF components.

As designs are completed, it can be useful to begin

verification testing as hardware returns from fabrica-tion. Connected solutions between EDA and testequipment can help in early verifica-tion testing by using the simulationtool to modeldesignsnot yetavailablefor testing. For example, in the casestudy presented, it would be useful to

begin verification testing of the driveramplifier or power amplifier on thetest bench with a real-world signalcontaining the impairments resultingfrom the baseband fixed-point FIR,potential RF impairments in the mod-ulator, mixer, phase noise in the localoscillator (LO), filter distortion, etc.This early verification capabilityusingconnected solutions between EDAand test equipment allows tradeoffsandwhat-ifscenarios to be performed,using the simulation tool to simulatemodels for prototype hardware that isnot yet available for testing.

The case study will illustrate thisEDA-test equipment connectivity us-

ing an existing evaluation board for the driver ampli-fier. The system simulation design is modified by re-moving thepoweramplifier andduplexer at theoutputof the driver amplifier. The simulation input signal tothe driver amplifier is connected to an electrical servicegenerator (ESG) signal generator interface so that areal-world test signal can be downloaded from simula-tion and created on the test bench. The ESG interface inthe schematic will download the I and Q signals fromthe simulation, which contain the modeled signal dis-tortions from the fixed-point FIR, mixer, and filter. Theresulting schematic and simulation results for the out-put of the driver amplifier are shown in Figure 7.

The connected solutions verification test benchsetup is shown in Figure 8, with the Agilent ESG signalgenerator, Agilent E4440 Performance Spectrum Ana-

lyzer (PSA) with digital demodulation, and a laptopwith the system design modeled in the Advanced

62 June 2002

IEEE magazine

3GPP W-CDMA System Virtual Verification using ADS-ESG Link

3GPPW-CDMA



Simulation Variables Design Tuning Variables ESG Virtual Vertification Link

Figure 7. Verification schematic using connected solutions between EDA software and test equipment.

Figure 8. Test setup using laptop with Agilent ADS 2002 EDA software, Agilent ESG Signal Generator (bottom), Agilent E4440 PSA Spectrum An-alyzer, DUT, and power supply. Measured results using the PSA are shownon right.


8/9

Design System (ADS) 2002 EDA software. The test re-sults are shown on the right-hand side of Figure 8 andcompare well to the simulation results at the output of the driver amplifier in Figure 7.

It can beseen that the measuredresults (Table 1)com-pare well to the simulated results. An approximate 2-dBdiscrepancy in lower measured DUToutput power rela-tive to simulated output power was not resolved at thetime of this writing. Based on observations made duringsimulation, ACLR performance at the output of thedriver amplifier is being dominated by other compo-nents modeled in simulationspecifically the 11-b49-tapfixed-point FIR(whichwassimulated since it wasnotavailable for test on the testbench). This wasverified by replacingthe fixed-pointFIRwitha floating-point be-havioral root-raised-cosine filter in the simulator and

creating a new real-world signal on the testbench.The resulting upper ACLR with the behavioralroot-raised-cosine filter was measured to be 50.9dB at a 5-MHz offset and 58.2 dB at a 10-MHz off-set, indicating that theimpairments resulting fromthe fixed-point FIR are dominating the ACLR per-formance at this stage in the system design. Thisimplies that the system-level ACLR performance

could possibly be enhanced by improving the FIRfilter design (either in number of taps or

bit-width),whichmightpossibly ease the requiredRF design performance of the driver amplifier orpower amplifier (PA). Additional simulations

wouldbe usefulto help evaluate these types of tradeoffs.At this point, a system designer could perform

what-if scenarios by modifying the simulation designand verifying the performance impact on the testbenchwith the available prototype hardware. The system de-signercouldalso modify or replace theprototype hard-ware on the testbench to determine how a modifieddesign or reusing an existing hardware design or pur-chased vendor part might perform with the real-worldsignal created in simulation.

It is worthpointing out that thesignalbeingdemod-ulated by thePSAsignal analyzeris being generatedbythe EDA software. Compatibility between the designsoftware and test equipment can provide flexibility ineither generating a real-world signal from simulationand using it on the test bench or generating the signal

June 2002 63

IEEE magazine

Table 1. Comparison of measured versus simulatedresults at the output of the driver amplifier.

Simulated Measured

ACLR @ 5 MHz upper offset 35.9 dB 35.9 dB

ACLR @ 5 MHz lower offset 35.9 dB 35.7 dB

ACLR @ 10 MHz upper offset 44.4 dB 45.3 dB

ACLR @ 10 MHz lower offset 44.1 dB 45.1 dB

EVM 2.98 % 3.2%

E4437B

SignalGenerator

Driver

AmplifierDUT

E4406A

Vector SignalAnalyzerReal-WorldTestSignal

with SimulatedImpairments

Power Supply Not Shown DUTSignal

ADS-ESGLink

IQ with SimulatedRF and DSP Impairments

Simulation SourceSignal from DUT

89600 VSA Measurementin Simulation

89600ADS-VSA

Link

Advanced Design System EDA Tool

3GPPW-CDMA SystemVirtual Vertification using ADS-ESG Link3GPP W-CDMA System Virtual Vertification with D.U.T.Sig nal Read Back

into ADS for Post-Processing using S9600 VSA in Simulation3GPP W-CDMASignal Source

Signal Read FromD.U.T./E4406A VSARF Upconverter ESG VirtualVertification Link

Simulation VariablesSimulationVariables

Design/TuningVariables DesignVariables


S9600 VSA inSimulation

Figure 9. Connected solutions test setup, using EDA software to model design impairments and EDA connectivity to testequipment to create real world signal and to read test signal back into EDA environment for additional simulations.


9/9

on the testbench and bringing it back into simulation.For example, it may also be desirable to model designimpairments in the simulation tool, create thereal-world test signal on the testbench, pass it throughthe DUT, and read the signal back into the simulationtool for further simulation analysis.

These steps were performed using the test setupshown in Figure 9. This test setup uses the ADS-ESG

connected solution previously discussed to create thereal-world test signalon the testbench. This test signal isthen passed through the DUT and into an AgilentE4406A vector signal analyzer (VSA). The DUT outputtest signal is then read from the E4406A VSA back intothe ADS simulation environment using the Agilent89600 VSA software, which is dynamically linked fromwithin ADS. The 89600 VSA software offers simulationsignal-source capability to read measured signals fromthetestbench/VSAback into ADS, as well as signal anal-ysis capability to demodulate and post- process simu-lated signals within ADS. Once the measured DUToutput signal is read back into ADS, it is passed throughthe modeled power amplifier and duplexer to evaluatethe final system performance with any resulting distor-tions that the power amplifier and duplexer might beadding. Note that code-domain power and code-do-main error are being analyzed using the 89600 VSAsoft-ware in simulation, which are additional measurementsuseful for 3GPP W-CDMAdesign and verification. Alsonote that the measurement display for the 89600 VSA insimulation has a similar user-interface and measure-ment algorithms as the vector signal analyzer on thetestbench. This continuity between the simulation do-main and test domain can help in transitioning back andforth between design and test efforts for verification.

The test setup shown in Figure 9 could be useful forsuch tasks ascascading anexistingfilterbehind thedriveramplifier to determine its EVM or ACLR impact at the fi-nal system output or possibly assessing the impact of ameasured impairment(phase noise, filterdistortion,LNAperformance, etc.) on receiver performance (if a receiverdesignwasbeing modeled instead).These are just a cou-ple of potential examples that are interesting possibili-ties for further investigation but, unfortunately, are

beyond the scope of this article. The E4440A PSA couldhave also been used in place of the E4406A VSA.

Summary This case study illustrates how some of the design andverification challenges presented by emerging wire-less signal formats can be addressed by simulating

both the RF and baseband portions of a system design

in the sameEDAsimulation tool for requirements par-titioning and system-level design verificationthroughout the design cycle. Design issues in integrat-ing the baseband and RF designs together can becaught early in the design cycle, where they are poten-tially less time-consuming and less costly to fix thanlater in the testing phase.

This case study also illustrates how EDAconnectiv-

ity to test equipment can be used to enhance designverification throughout the design cycle by modelingreal-world signals in simulation and turning them intoRF test signals on the testbench to test early prototypehardware. Design impairments from hardware not yetavailable fortest canbe modeled in simulation to createreal-world test signals on the testbench to begin testingof preliminary hardware or components as they be-come available. Verification is further enhanced withcompatibility between design and test in being able togenerate a signal in simulation, turn it into an RF testsignal at the input of the DUT, and bring the DUT out-put signal back into simulation for further analysis.This can provide flexibility in performing what-if sce-narios with a connected-solution test setup to evaluatehardware design modifications in simulation or to as-sess the impact of reusing existing hardware or vendorparts on a simulated system. Finally, a more seamlesslevel of connectivity between EDA software and testequipment is desirable for better predictability andease of verification when transitioning back and forth

between design and test, as illustrated by the 89600VSA software, which is dynamically linked fromwithin ADS 2002.

Additional ReadingUE Radio Transmission and Reception (FDD) (Release 1999), in

3GPP Technical Specification 25.101, v3.2.2 (2000-4). Available:http://www.3gpp.org

Terminal Conformance Specification; Radio Transmission and Re-ception (FDD) (Release 1999), in 3GPP Technical Specification34.121, v3.0.0 (2000-3). Available: http://www.3gpp.org

Agilent Solutions for Designing and Manufacturing Base Transceiver Sta-tions and Their Components. [Online]. Available:http://www.agilent.com/find/basestationtest

ADS 2002 Connected Solutions, Wireless Design Libraries, ApplicationNotes. [Online]. Available: http://www.agilent.com/eesof-eda

Agilent Solutions for Designing and Manufacturing Wireless Appliances.[Online]. Available:http://www.agilent.com/find/wirelessdesign

Agilent 3G Application Notes. [Online]. Available:

http://www.agilent.com/find/3G Agilent ADS Training Class: Designing W-CDMA/3GPP CommunicationSystems Using ADS. [Online]. Available: http://con-tact.tm.agilent.com/tmo/eesof/education/

L. Eichinger, UMTS RF System Simulation. Munich, Germany: AgilentTechnologies, 2001.

64 June 2002

IEEE magazine

Date post:	05-Apr-2018
Category:	Documents
Upload:	pavika-sharma
View:	215 times
Download:	0 times

3gpp W-cdma Systems

Documents