4 BIT Arithmetic And Logic Unit (ALU)

Philips 74HC/HCT181Brijesh ChavdaMeet Aghera

Mrugesh ChandaranaSandip Patel

AdviserDavid Parent

Date: 12/03/05

Abstract

• Goal is to design 4-bit ALU driving up to 25fF.

• Perform arithmetic operations like A+B, A+B’, A-1, A+(AB’), AB-1.

• Perform Logical operations like Ex-OR, Compare, AND, NAND, NOR, OR plus 10 other logic operations.

• The data must be transferred at clock rate of 200MHz.

• Maximum area is 323 X 760 µm².

Introduction

• ALU is a building block of several complex circuits.

• The designed ALU is able to handle two 4 bit inputs to produce required output based on the output selector lines.

• Challenging to design 16 logic level circuit working with 5ns delay.

• Using this knowledge and experience, we can move on to designing more complex integrated circuits.

Design Flows

• Calculate the longest path delay from the circuit.

• Create schematic and layout for INV, NAND2 and NAND3.

• Combine these three building blocks to create the different blocks of the circuit.

• Test the schematic logic of all the modules.

• Assembled all the modules and flip-flops.

• Run DRC, extracted and LVS check to verify the design.

• Analyze the circuit power and timing using Analog Affirma.

Block diagram of Philips 74HC/HCT181

Longest Path Calculation

CELL BIT WN Load WP Load CintCg or Cin of load Cg+Cint phl plh WN WP

    (cm) (cm) F F   s s cm cm

                     

INV_A 16 0.00E+00 0.00E+00 5.00E-15 2.50E-14 3.00E-14 9.00E-11 9.00E-11 3.93E-04 7.11E-04

NAND2_A 15 3.93E-04 7.11E-04 5.00E-15 1.85E-14 2.35E-14 2.00E-10 2.00E-10 3.94E-04 3.51E-04

INV_B 14 3.94E-04 3.51E-04 5.00E-15 1.25E-14 1.75E-14 1.00E-10 1.00E-10 2.06E-04 3.71E-04

NAND2_B 13 2.06E-04 3.71E-04 5.00E-15 9.68E-15 1.47E-14 2.00E-10 2.00E-10 2.75E-04 2.45E-04

NAND2_C 12 2.75E-04 2.45E-04 5.00E-15 8.72E-15 1.37E-14 2.00E-10 2.00E-10 2.62E-04 2.33E-04

NAND2_D 11 2.62E-04 2.33E-04 5.00E-15 8.31E-15 1.33E-14 2.00E-10 2.00E-10 2.56E-04 2.28E-04

NAND2_E 10 2.56E-04 2.28E-04 5.00E-15 8.13E-15 1.31E-14 2.00E-10 2.00E-10 2.54E-04 2.26E-04

INV_C 9 2.54E-04 2.26E-04 5.00E-15 8.06E-15 1.31E-14 1.00E-10 1.00E-10 1.60E-04 2.88E-04

NAND3_A 8 1.60E-04 2.88E-04 5.00E-15 7.51E-15 1.25E-14 2.50E-10 2.50E-10 8.52E-04 5.02E-04

NAND2_F 7 8.52E-04 5.02E-04 5.00E-15 2.27E-14 2.77E-14 2.00E-10 2.00E-10 4.51E-04 4.01E-04

INV_D 6 4.51E-04 4.01E-04 5.00E-15 1.43E-14 1.93E-14 1.00E-10 1.00E-10 2.24E-04 4.05E-04

NAND2_G 5 2.24E-04 4.05E-04 5.00E-15 1.06E-14 1.56E-14 2.00E-10 2.00E-10 2.87E-04 2.55E-04

INV_E 4 2.87E-04 2.55E-04 5.00E-15 9.10E-15 1.41E-14 1.00E-10 1.00E-10 1.70E-04 3.08E-04

NAND2_H 3 1.70E-04 3.08E-04 5.00E-15 8.02E-15 1.30E-14 2.00E-10 2.00E-10 2.53E-04 2.25E-04

NAND3_B 2 2.53E-04 2.25E-04 5.00E-15 8.01E-15 1.30E-14 2.35E-10 2.35E-10 1.85E-04 1.63E-04

INV_F 1 1.85E-04 1.63E-04 5.00E-15 5.84E-15 1.08E-14 9.00E-11 9.00E-11 1.60E-04 2.89E-04

              2.67E-09      

Schematic of 4-Bit ALU

Layout of the circuit

Verification – LVS Check

Final TB

Logic Simulation

Lesson learned

• Follow the steps and guideline given by

Dr. Parent

• How to design a compact circuit.

• How to fix the LVS errors.

• Optimize transistor size to meet out specifications.

• How to use cadence tools.

Acknowledgements

• Thanks to Professor David Parent for his guidelines and help throughout the project.

• Thanks to Cadence Design Systems for VLSI Lab.