Chapter 1

Introduction

Universal shift register is capable of converting input data to parallel or serial which also does shifting of data bidirectional, unidirectional (SISO , SIPO , PISO , PIPO) and also parallel load this is called as Universal shift register .

Shift register are used as: Data storage device , Delay element , communication lines , digital electronic devices (Temporary data storage , data transfer , data manipulation , counters) , etc .

1.1 Block diagram of universal shift register(USR) :

Figure 1.1 block diagram of USR.

The diagram of a shift register that has all the capabilities listed above is shown in fig. 1.1. It consists of four D flip-flops and four multiplexers (MUX) .

The s, and So inputs control the mode of operation of the register as specified in the function entries of Table 1.1

Table 1-1Function table for register of fig. 1.1

Mode ControlRegister operationS1 S0

0 0 No change0 1 Shift left1 0 Shift right1 1 Parallel load

A bidirectional shift register with parallel load is a general-purpose register capable of performing three operations: shift left, shift right, and parallel load. Not all shift registers available in MSI circuits have all these capabilities. The particular application dictates the choice of one MSI shift register over another.

CHAPTER 2

Implementation of USR in Verilog

2.1 Verilog Code :

`timescale 1ns / 1ps

//modual declaraion of input and output and register

module USR(O,I,clk,reset,s,SINR,SINL);

wire [3:0] w;

input [3:0]I;

input [1:0]s ;

input clk ;

input reset,SINR,SINL;

output [3:0]O;

reg [27:0] count = 0;

//MUX modual calling

mux_4_1 m1(w[0],s[1],s[0],I[0],SINL,O[1],O[0]);

mux_4_1 m2(w[1],s[1],s[0],I[1],O[0],O[2],O[1]);

mux_4_1 m3(w[2],s[1],s[0],I[2],O[1],O[3],O[2]);

mux_4_1 m4(w[3],s[1],s[0],I[3],O[2],SINR,O[3]);

//D flip flop modual calling

D_FF d1(O[0],w[0],clk,reset);

D_FF d2(O[1],w[1],clk,reset);

D_FF d3(O[2],w[2],clk,reset);

D_FF d4(O[3],w[3],clk,reset);

//increment count on every clock

endmodule

//sub module for D flip flop

module D_FF(q,d,clk,reset);

output reg q;

input d,clk,reset;

always@(posedge clk)

if (reset == 1'b1)

q<=1'b0;

else

q<=d;

endmodule

//sub module for 4x1 MUX

module mux_4_1(y,s1,s0,i3,i2,i1,i0);

output reg y;

input i3,i2,i1,i0;

input s1,s0;

always@(s1,s0,i3,i2,i1,i0)

begin

if (s0==0 & s1==0)

y=i0;

else if (s0==0 & s1==1)

y=i1;

else if (s0==1 & s1==0)

y=i2;

else if (s0==1 & s1==1)

y=i3;

end

endmodule

2.2 RTL and technology schematic :

2.2.1 RTL :

Figure 2.1 RTL schematic of USR

2.2.2 4x1 MUX :

Figure 2.2 RTL schematic of 4x1 MUX

2.2.3 Technological schematic of USR :

Figure 2.3 technology schematic of USR

2.3 Simulation and test bench:2.3.1 Test bench:

`timescale 1ns / 1ps

module uni_testbench;

// Inputs reg [3:0] I; reg clk; reg reset; reg [1:0] s; reg SINR; reg SINL;

// Outputs wire [3:0] O;

// Instantiate the Unit Under Test (UUT) USR uut ( .O(O), .I(I), .clk(clk), .reset(reset), .s(s), .SINR(SINR), .SINL(SINL) );

initial begin // Initialize Inputs //I = 4'b0000; clk = 1'b1; reset = 1'b1; SINR = 1'b1; SINL = 1'b0; s = 2'b00;

#100; reset = 1'b1;// s = 2'b00; #100; I = 4'b0101; reset = 1'b10; #100; s = 2'b11; #100; s = 2'b01; #100; s = 2'b10; #100; s = 2'b00;

// Wait 100 ns for global reset to finish #100; // Add stimulus here

#100; I = 4'b1010; reset = 1'b10; #100; s = 2'b11; #100; s = 2'b01; #100; s = 2'b10;

#100; s = 2'b00; end always #50 clk=~clk;endmodule

2.3.2 Simulation result :

Figure 2.4 Simulation result of USR

Chapter 3

Implementation of CLA on FPGABoard

3.1 UCF file:

NET "I[0]" LOC = "L13" ;NET "I[1]" LOC = "L14" ;NET "I[2]" LOC = "H18" ;NET "I[3]" LOC = "N17" ;

NET "s[0]" LOC = "H13" | IOSTANDARD = LVTTL | PULLDOWN | CLOCK_DEDICATED_ROUTE = FALSE;NET "s[1]" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN | CLOCK_DEDICATED_ROUTE = FALSE; NET "reset" LOC = "V16"| IOSTANDARD = LVTTL | PULLDOWN ; NET "SINL" LOC = "D18"| IOSTANDARD = LVTTL | PULLDOWN ;NET "SINR" LOC = "V4"| IOSTANDARD = LVTTL | PULLDOWN ;

NET "clk" LOC = "C9";

NET "O[0]" LOC = "F12" ;NET "O[1]" LOC = "E12" ;NET "O[2]" LOC = "E11" ;NET "O[3]" LOC = "F11" ;

Chapter 4

4.1 Schematic of USR :

Figure 4.1 symbol representation of USR

4.1.1 D flip flop:

Figure 4.2 schematic of D flip flop

Simulation result :

Figure 4.3 simulation result of D FF

4x1 MUX:

Figure 4.4 schematic of 4x1 MUX

Simulation of 4x1 MUX :

Figure 4.5 simulation result of 4x1 MUX

Chapter 5

Layout of USR

D flip flop (semi-custom design) :

Figure 5.1 layout of D flip flop

D flip flop (Auto generated ) :

Figure 5.2 layout of D flip flop auto generated

Simulation result :

Figure 5.3 simulation result of D flip flop layout

4x1 MUX (semi-custom design) :

Figure 5.2 Layout of 4x1 MUX

4x1 MUX (auto generated ) :

Figure 5.3 auto generated layout of 4x1 MUX

4x1 Simulation result :

Figure 5.4 simulation of 4x1 MUX