4. Program Counter Design

Olle SegerAndreas Ehliar

Jian Wang

A pipelinedCPU

* similar (but not identical) to Senior

0: add1: jmp.eq ds0 52: xxx3: yyy4: zzz5: and6: www

IR3

JT

JT = jump takenjmpdec = jump decoded

PC FSM

•The PC FSM must be a Mealy machine• in : decoded IR => Is it a jump instruction? What kind?• in : jump taken = JT• out : next PC• out: should the IR be nopped?

• The following instructions should be implemented• jump ds0/ds1 addr• jump.eq ds0/ds1 addr

λ

δ D

inout

state

next state

0: add1: jmp.eq ds0 52: xxx3: yyy4: zzz5: and6: www

PC IR IR1 IR2 IR3 ...01 add2 jmp add2 nop jmp add2 nop nop jmp add5 nop nop nop jmp6 and nop nop nop

PC IR IR1 IR2 IR3 ...01 add2 jmp add2 nop jmp add2 nop nop jmp add3 xxx nop nop jmp4 yyy xxx nop nop

A pipelinedCPU

* similar (but not identical) to Senior

0: add1: jmp.eq ds1 52: xxx3: yyy4: zzz5: and6: www

IR3

JT

JT = jump taken

0: add1: jmp.eq ds1 52: xxx3: yyy4: zzz5: and6: www

PC IR IR1 IR2 IR3 ...01 add2 jmp add3 xxx jmp add3 nop xxx jmp add5 nop nop xxx jmp6 and nop nop xxx

PC IR IR1 IR2 IR3 ...01 add2 jmp add3 xxx jmp add3 nop xxx jmp add4 yyy nop xxx jmp5 zzz yyy nop xxx

State graph

0

1 2

ds0(nop,stall PC)

-(nop,stall PC)JT(nop,PC=Target)JT(PC++)

3

-(PC++)

4

jmp(PC

++)

ds1(PC++)

-(nop,stall PC)

jmp inIR1 jmp in

IR2jmp inIR3

State graph (simplified)

0

1 2ds0(nop,stall PC) -(nop,stall PC)

JT(nop,PC=Target)JT(PC++)

jmp(PC++)

ds1(PC++)

1.

1.

0: jmp 51: xxx2: yyy3:4:5: zzz

jmp 5

1

5

1a

xxx will be executed1 delay slot

add r3,r0,r1

nop

add r3,r2,r3

add r3,r0,r1nopadd r3,r2,r3

1b

If RF is SRAM1 nop

nop

jmp.lt

nop

5

1c

0:set r2,101:nop2:jump.lt r0,r2,203:nop ; Delay slot 14:nop ; Delay slot 25:nop ; Delay slot 3…20:

1c

1c

0

1 2

jmp(PC++)

3

jmpdec = PFC_OP[4]JT = PFC_OP2[4]*(PC_FSM_EQUAL*(PFC_OP2[1:0]==0) + …)

jmp(PC++)

-(PC++)

JT(PC=PFC_DATA_2)

JT(PC++)

-(PC++)

0JT(PC++)

JT(PC=PFC_DATA_2)

+1

1 0

PC

21

0

&PFC_OP[4]

PFC_OP[1:0]

jump decision

1d

ProgramCounterModule

2

2