1
Cross-bar architectures
Daniele Ielmini
DEI - Politecnico di Milano, Milano, [email protected]
Flash scaling overview
Mar. 2, 2010 D. Ielmini, "Non volatile memories" – 4 2
1. Flash scaling: 2. Evolutionary scenario:
3. Paradigm shift
H. Tanaka et al., VLSI Symp. 2007
M. Lee, et al., IEDM Tech. Dig. 2007
T. Kamaigaichi, et al., IEDM Tech. Dig. 2008
www.micron.com
2
Crossbar architectures
Mar. 2, 2010 D. Ielmini, "Non volatile memories" – 4 3
• Introduction
• SiO2-based 3D-OTP (Matrix, 2004)
• NiO RRAM crossbar (Samsung, 2005)
• NiO RRAM BEOL crossbar (Samsung,
2007)
• Perovskite-based RRAM crossbar
(Unity, 2008)
• PCM crossbar (Hitachi, 2009)
• PCMS crossbar (Intel-Numonyx, 2009)
Crossbar
Mar. 2, 2010 D. Ielmini, "Non volatile memories" – 4 4
• Mutually crossing perpendicular wordlines and bitlines
• Memory element at each WL/BL crossing
• Highest cell density 4F2 + 3D stacking = 4F2/n density
3
Why rectifier?
Mar. 2, 2010 D. Ielmini, "Non volatile memories" – 4 5
• Diode rectifier needed to avoid read current sneakthrough
• Diode must: 1. Isolate unselected cells � low leakage current2. Sustain reset current � high forward current
SiO2-based 3D-OTP
• First reported in 2004 by Matrix (later acquired by
Sandisk)
• This product is on the market!
• Advantage: CMOS process/materials, 4F2/n area/bit
• Disadvantage: only one time programmableMar. 2, 2010 D. Ielmini, "Non volatile memories" – 4 6
4
Programming = breakdown
• Breakdown shunts the resistive SiO2 layer, the polySi pn diode remains (rectification needed forselect/unselect)
Mar. 2, 2010 D. Ielmini, "Non volatile memories" – 4 7
sensing
Diode rectification
• In 2008, Sandisk claimed development of a rewritable 3D
memory based on the same concept, that never surfaced …
• Sandisk and Toshiba announced a cross-licensing agreement
on 3D concepts in 2008
Mar. 2, 2010 D. Ielmini, "Non volatile memories" – 4 8
5
RRAM crossbar (Samsung, 2005)
• 4x5 crossbar array
• No selection device � sneakthroughMar. 2, 2010 D. Ielmini, "Non volatile memories" – 4 9
P/E characteristics
• Back-end compatible (room temperature) p-
NiO/n-TiO2 diode added to:
– Suppress sneakthrough
– Sustain mA-range reset current at 30x30 µm2
Mar. 2, 2010 D. Ielmini, "Non volatile memories" – 4 10
6
RRAM crossbar (Samsung, 2007)
• Progress at IEDM 2007: 2 layers + smaller area (F = 500 nm) thanks to higher forward currentdensity
Mar. 2, 2010 D. Ielmini, "Non volatile memories" – 4 11
1D-1R characteristics
• Reset voltage higher than 2 V due to seriesresistance, diode onset voltage, etc.
• As the cell scales below 500 nm, no reset will bepossible unless the forward current density isimproved by diode technology
Mar. 2, 2010 D. Ielmini, "Non volatile memories" – 4 12
7
Forward current density
• Improvement mainly by band-gap/offset lowering
• Other constraint � room temperature diode
Mar. 2, 2010 D. Ielmini, "Non volatile memories" – 4 13
Crossbar RRAM (Samsung, 2008)
Mar. 2, 2010 D. Ielmini, "Non volatile memories" – 4 14
• Si-based decoder cannot bestacked � area benefit degrades with no. of layers
� oxide based stackabledecoder
8
All-oxide RRAM integration
Mar. 2, 2010 D. Ielmini, "Non volatile memories" – 4 15
GaInZnO (GIZO) TFT transistors
Mar. 2, 2010 D. Ielmini, "Non volatile memories" – 4 16
W/L = 160um/2um
9
CMOX memory (Unity, 2008)
• Individual cell in the crossbar array consists ofstacked CMO (switching layer) + TO (select layer)
Mar. 2, 2010 D. Ielmini, "Non volatile memories" – 4 17
Tunnel diode (non-rectifier)
• Current exponentially increases with TO thickness(SiO2?)
• Relatively large current suggests TAT mechanism
Mar. 2, 2010 D. Ielmini, "Non volatile memories" – 4 18
10
Mar. 2, 2010 D. Ielmini, "Non volatile memories" – 4 19
• Analog bipolar switching
• Area-dependent switching
• Correlated changes of R and C
suggest a parallel switching
model with doping-dependent ε
Program/erase characteristics3mA/25 mm2 =
1.2x104 Acm-2
Switching model
Mar. 2, 2010 D. Ielmini, "Non volatile memories" – 4 20
11
Ion migration and diffusion
Mar. 2, 2010 D. Ielmini, "Non volatile memories" – 4 21
CMOx device
• Ideal combination of crossbar + stacking + MLC
Mar. 2, 2010 D. Ielmini, "Non volatile memories" – 4 22
12
OTP RRAM (Samsung, 2009)
• 1D1R main advantage = room temperature (stackable)
• Issue = reset current � stackable OTP (no reset needed!)
• Al2O3 as active material (no reversible switching needed)
Mar. 2, 2010 D. Ielmini, "Non volatile memories" – 4 23
tAl2O3 = 2 nm
tPt = 15 nm
0.5 um
tdiode = 70 nm
Program and I-V characteristics
Mar. 2, 2010 D. Ielmini, "Non volatile memories" – 4 24
J = 3x104 Acm-2 =
record for oxide diode
13
PCM crossbar
• GST element + poly-Si p-i-n diode
• Only one layer demonstrated
• Forward current 8MAcm-2 is enough for PCM reset
Mar. 2, 2010 D. Ielmini, "Non volatile memories" – 4 25
Diode characteristics• PolySi diode compares well with epi-Si p-n diode
• 50-nm intrinsic region to minimize reverse leakage
• Electrode optimization to optimize series resistanceand diode contamination affecting reverse leakage
Mar. 2, 2010 D. Ielmini, "Non volatile memories" – 4 26
2 mA/(90 nm)2 ≈ 20 MAcm-2
Samsung PCM, IEDM 2006Hitachi PCM, VLSI 2009
14
P/E characteristics
• Note: does Ireset really scale as F2?
– Theory says Ireset ∝ F (isotropic scaling)
– Experimental data show Ireset ∝ F1.4 (non isotropic scaling)
– Numonyx and Hitachi data reveals non-isotropic scaling
Mar. 2, 2010 D. Ielmini, "Non volatile memories" – 4 27
F2 (µm2)
numonyx
epiSi
Ireset ∝ F2
PCMS crossbar
• Concept: PCM addressed by an Ovonic
threshold switch (OTS) � PCMS
Mar. 2, 2010 D. Ielmini, "Non volatile memories" – 4 28
15
OTS• Original invention by Ovshinsky in 1968 was not
PCM but OTS = a diode with voltage snapback
Mar. 2, 2010 D. Ielmini, "Non volatile memories" – 4 29
Original Ovshinsky invention
Mar. 2, 2010 D. Ielmini, "Non volatile memories" – 4 30
16
Threshold and memory switching
• Threshold switching (an electronic process dictated by negative differential resistance) isubiquitous for chalcogenide glasses
• For some chalcogenide glass(phase change materials), the dissipated power in the ON state is so large that crystallizationtakes place
Mar. 2, 2010 D. Ielmini, "Non volatile memories" – 4 31
Switching materials
• Threshold switching: AlAsTe*, AlGeAsTe,
SiAsTe, GaSiGeAsTe, GeAsTe, GeSbTeS,
GeSiAsPTe,
• Memory switching: InTe, GeSbTe, GeSb,
SbTe, CuGeTe, AgGeTe, AlAsTe*, InSe,
AgInSbTe
* TS or MS depending on composition
Mar. 2, 2010 D. Ielmini, "Non volatile memories" – 4 32
17
Characteristics and read disturb
• The leakage from unselected bits (N-1)Ileak
must not exceed the sensing level Iread(set)/10
Mar. 2, 2010 D. Ielmini, "Non volatile memories" – 4 33
0 1 2 3 4 5 610
-10
10-9
10-8
10-7
10-6
10-5
10-4
Ileak
Vread
/3 Vread
/2
Iread
(set)=300uA
Iread
(reset)=1uA
Curr
en
t [A
]
Voltage [V]
Reset state
Set state
Rectifier only
Vread
=3.6V
Program disturb
• Program voltage must exceed VT,reset, whileinhibit voltage must be lower than VT,set
Mar. 2, 2010 D. Ielmini, "Non volatile memories" – 4 34
0 1 2 3 4 5 610
-10
10-9
10-8
10-7
10-6
10-5
10-4
Ileak
Vread
/3 Vread
/2
Iread
(set)=300uA
Iread
(reset)=1uA
Curr
en
t [A
]
Voltage [V]
Reset state
Set state
Rectifier only
Vread
=3.6V
18
P/E and reliability
• VT window seems sufficient for read
Mar. 2, 2010 D. Ielmini, "Non volatile memories" – 4 35
No-select crossbar (Macronyx, 2003)
• PCM without OTS
• Rectifier provided by the amorphous phase in PCM
• Read is destructive, post-read refresh needed
Mar. 2, 2010 D. Ielmini, "Non volatile memories" – 4 36
Y.-C. Chen, et al., IEDM 905, 2003
19
Application: cross-point array
Self-select PCM cross-point array (Y.-C. Chen et al.,
IEDM Tech. Dig., 905-908, 2003)
BL,sel
WL,sel
0.0 0.5 1.0 1.5 2.010
-9
10-8
10-7
10-6
1x10-5
1x10-4
10-3
State 0
Cu
rre
nt
[A]
Voltage [V]
State 1
I(1)
I(0)
Mar. 2, 2010 37D. Ielmini, "Non volatile memories" – 4
Leakage comparison @ 25C
1 10 100 100010
-6
1x10-5
1x10-4
10-3
25C
Curr
en
t [A
]
Number of WLs [1]
60
V/2
V/3
__
__
I(1)/10
Mar. 2, 2010 38D. Ielmini, "Non volatile memories" – 4
20
Leakage comparison @ 85C
1 10 100 100010
-6
1x10-5
1x10-4
10-3
85C
Curr
en
t [A
]
Number of WLs [1]
10
V/2
V/3
__
__
I(1)/10
Mar. 2, 2010 39D. Ielmini, "Non volatile memories" – 4
Conclusions
• Crossbar is a nice idea, but many practical
issues need to be solved
• Stackable diode: room temperature process
+ sufficient forward current
• Reset current limits NiO-RRAM to 30 um size
• CMOx and similar analog/uniform RRAMs
seem most scalable (low Ireset)
• PCM crossbar seems not scalable
Mar. 2, 2010 D. Ielmini, "Non volatile memories" – 4 40
