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MR2A16A Rev. 10.1, 7/20131 Copyright © Everspin Technologies 2013
MR2A16A256K x 16 MRAM MemoryFEATURES
• Fast35nsRead/WriteCycle• SRAMCompatibleTiming,UsesExistingSRAMControllersWithoutRedesign
• UnlimitedRead&WriteEndurance• DataNon-volatilefor>20yearsatTemperature• OneMemoryReplacesFlash,SRAM,EEPROMandBBSRAMinSystemforSimpler,MoreEfficientDesign
• Replacebattery-backedSRAMsolutionswithMRAMtoimprovereliability
• 3.3VoltPowerSupply• AutomaticDataProtectiononPowerLoss• Commercial,Industrial,ExtendedTemperatures• RoHS-CompliantSRAMTSOP2andBGAPackages-MSLLevel3• AEC-Q100Grade1option
INTRODUCTIONTheMR2A16Aisa4,194,304-bitmagnetoresistiverandomaccessmemory(MRAM)deviceorganizedas262,144wordsof16bits.TheMR2A16AoffersSRAMcompatible35nsread/writetimingwithunlimitedendurance.Dataisalwaysnon-volatileforgreaterthan20years.Dataisautomaticallyprotectedonpowerlossbylow-voltageinhibitcircuitrytopreventwriteswithvoltageoutofspecification.TheMR2A16Aistheidealmemorysolutionforapplicationsthatmustpermanentlystoreandretrievecriticaldataandprogramsquickly.
TheM24A16Bisavailableinasmallfootprint48-pinballgridarray(BGA)packageanda44-pinthinsmalloutlinepackage(TSOPType2).Thesepackagesarecompatiblewithsimilarlow-powerSRAMproductsandothernonvolatileRAMproducts.
TheMR2A16Aprovideshighlyreliabledatastorageoverawiderangeoftemperatures.Theproductisofferedwithcommercial(0to+70°C),industrial(-40to+85°C),extended(-40to+105°C)andAEC-Q100Grade1(-40to+125°C)operatingtemperaturerangeoptions.
RoHS
CONTENTS1.DEVICEPINASSIGNMENT.........................................................................22.ELECTRICALSPECIFICATIONS.................................................................43.TIMINGSPECIFICATIONS.......................................................................... 74.ORDERINGINFORMATION.......................................................................125.MECHANICALDRAWING..........................................................................136.REVISIONHISTORY......................................................................................15HowtoReachUs..........................................................................................15
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MR2A16A Rev. 10.1, 7/20132 Copyright © Everspin Technologies 2013
1. DEVICE PIN ASSIGNMENT
Figure 1.1 Block Diagram
Table 1.1 Pin Functions
MR2A16A
Signal Name Function A AddressInput
E ChipEnable
W WriteEnable
G OutputEnable
UB UpperByteEnable
LB LowerByteEnable
DQ DataI/O
VDD PowerSupply
VSS Ground
DC DoNotConnect
NC NoConnection
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MR2A16A Rev. 10.1, 7/20133 Copyright © Everspin Technologies 2013
A0A1A2A3
DQL0DQL1
VDD
E
VSS
DQL2DQL3
W
A7A8A9
A4
22212019181716151413121110987654321
A6A5
23242526272829303132333435363738394041424344
A15G
DQL7DQL6
VSS
VDD
DQL5DQL4
A14 A13A12A11A10
DC
A17A16
UB LBDQU15DQU14DQU13DQU12
DQU11DQU10DQU9DQU8
1 2 3 4 5 6
LB G A0 A1 A2 NC A
DQU8 UB A3 A4 E DQL0 B
DQU9 DQU10 A5 A6 DQL1 DQL2 C
VSS DQU11
A15
DQL3 VDD D
VDD DQU12 NC A16 DQL4 VSS E
DQU14 DQU13 A14
A13
DQL5 DQL6 F
DQU15 NC
A10
A17
A11
W DQL7 G
NC
A7
A9A8
A12
DC H
Figure 1.2 Pin Diagrams for Available Packages (Top View)
44-Pin TSOP Type2 48-Pin BGA
Table 1.2 Operating Modes
DEVICE PIN ASSIGNMENT MR2A16A
E 1 G 1 W 1 LB 1 UB 1 Mode VDD Current DQL[7:0]2 DQU[15:8]2
H X X X X Notselected ISB1,ISB2 Hi-Z Hi-Z
L H H X X Outputdisabled IDDR Hi-Z Hi-Z
L X X H H Outputdisabled IDDR Hi-Z Hi-Z
L L H L H LowerByteRead IDDR DOut Hi-Z
L L H H L UpperByteRead IDDR Hi-Z DOut
L L H L L WordRead IDDR DOut DOut
L X L L H LowerByteWrite IDDW Din Hi-Z
L X L H L UpperByteWrite IDDW Hi-Z Din
L X L L L WordWrite IDDW Din Din
1H=high,L=low,X=don’tcare2Hi-Z=highimpedance
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MR2A16A Rev. 10.1, 7/20134 Copyright © Everspin Technologies 2013
2. ELECTRICAL SPECIFICATIONSAbsolute Maximum RatingsThisdevicecontainscircuitrytoprotecttheinputsagainstdamagecausedbyhighstaticvoltagesorelectricfields;however,itisadvisedthatnormalprecautionsbetakentoavoidapplicationofanyvoltagegreaterthanmaximumratedvoltagestothesehigh-impedance(Hi-Z)circuits.
Thedevicealsocontainsprotectionagainstexternalmagneticfields.Precautionsshouldbetakentoavoidapplicationofanymagneticfieldmoreintensethanthemaximumfieldintensityspecifiedinthemaximumratings.
Table 2.1 Absolute Maximum Ratings1
MR2A16A
Symbol Parameter Temp Range Package Value Unit
VDD Supplyvoltage2 - - -0.5to4.0 V
VIN Voltageonanypin2 - - -0.5toVDD+0.5 V
IOUT Outputcurrentperpin - - ±20 mA
PD Packagepowerdissipation3 - Note3 0.600 W
TBIAS Temperatureunderbias
Commercial - -10to85
°CIndustrial - -45to95
Extended - -45to110
AEC-Q100Grade1 - -45to130
Tstg StorageTemperature - - -55to150 °C
TLeadLeadtemperatureduringsolder(3minutemax) - - 260 °C
Hmax_writeMaximummagneticfieldduringwrite
Commercial TSOP2,BGA 2,000
A/mIndustrial,ExtendedBGA 2,000
TSOP2 10,000
AEC-Q100Grade1 TSOP2 2,000
Hmax_readMaximummagneticfieldduringreadorstandby
Commercial TSOP2,BGA 8,000
A/mIndustrial,ExtendedBGA 8,000
TSOP2 10,000
AEC-Q100Grade1 TSOP2 8,000
Notes:1. Permanentdevicedamagemayoccurifabsolutemaximumratingsareexceeded.Functionaloperationshouldberestricted
torecommendedoperatingconditions.Exposuretoexcessivevoltagesormagneticfieldscouldaffectdevicereliability.2. AllvoltagesarereferencedtoVSS.3. Powerdissipationcapabilitydependsonpackagecharacteristicsanduseenvironment.
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MR2A16A Rev. 10.1, 7/20135 Copyright © Everspin Technologies 2013
Parameter Symbol Min Typical Max UnitPowersupplyvoltage1 VDD 3.0 3.3 3.6 V
Writeinhibitvoltage VWI 2.5 2.7 3.01 V
Inputhighvoltage VIH 2.2 - VDD+0.32 V
Inputlowvoltage VIL -0.53 - 0.8 V
TemperatureunderbiasMR2A16A(Commercial)MR2A16AC(Industrial)MR2A16AV(Extended)MR2A16AM(AEC-Q100Grade1)4
TA
0-40-40-40
7085105125
°C
1 Thereisa2msstartuptimeonceVDDexceedsVDD,(max).SeePower Up and Power Down Sequencing below.2 VIH(max)=VDD+0.3VDC;VIH(max)=VDD+2.0VAC(pulsewidth≤10ns)forI≤20.0mA.3 VIL(min)=-0.5VDC;VIL(min)=-2.0VAC(pulsewidth≤10ns)forI≤20.0mA.4AEC-Q100Grade1temperatureprofileassumes10%dutycycleatmaximumtemperature(2yearsoutof20yearslife.)
Table 2.2 Operating Conditions
Power Up and Power Down Sequencing
TheMRAMisprotectedfromwriteoperationswheneverVDDislessthanVWI.AssoonasVDDexceedsVDD(min),thereisastartuptimeof2msbeforereadorwriteoperationscanstart.Thistimeallowsmemorypowersuppliestostabilize.
TheEand W controlsignalsshouldtrackVDDonpoweruptoVDD-0.2VorVIH(whicheverislower)andremainhighforthestartuptime.Inmostsystems,thismeansthatthesesignalsshouldbepulledupwitharesistorsothatsignalremainshighifthedrivingsignalisHi-Zduringpowerup.AnylogicthatdrivesEandWshouldholdthesignalshighwithapower-onresetsignalforlongerthanthestartuptime.
DuringpowerlossorbrownoutwhereVDDgoesbelowVWI,writesareprotectedandastartuptimemustbeobservedwhenpowerreturnsaboveVDD(min).
Figure 2.1 Power Up and Power Down Diagram
MR2A16AElectrical Specifications
BROWNOUT or POWER LOSS
NORMAL OPERATION
VDD
READ/WRITE INHIBITED
VWI
2 ms
READ/WRITE INHIBITED
VIH
STARTUP
NORMAL OPERATION
2 ms
E
W
RECOVER
VIH
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MR2A16A Rev. 10.1, 7/20136 Copyright © Everspin Technologies 2013
Parameter Symbol Min Typical Max Unit
Inputleakagecurrent Ilkg(I) - - ±1 μA
Outputleakagecurrent Ilkg(O) - - ±1 μA
Outputlowvoltage(IOL=+4mA)(IOL=+100μA)
VOL - - 0.4VSS+0.2
V
Outputhighvoltage(IOH=-4mA)(IOH=-100μA)
VOH 2.4VDD-0.2
- - V
Table 2.3 DC Characteristics
Table 2.4 Power Supply Characteristics
Parameter Symbol Typical Max Unit
ACactivesupplycurrent-readmodes1
(IOUT=0mA,VDD=max) IDDR 55 80 mA
ACactivesupplycurrent-writemodes1
(VDD=max)CommercialGradeIndustrialGradeExtendedGradeAEC-Q100Grade
IDDW
105105105105
155165165165
mA
ACstandbycurrent(VDD=max,E=VIH)no other restrictions on other inputs
ISB1 18 28 mA
CMOSstandbycurrent(E≥VDD-0.2VandVIn≤VSS+0.2Vor≥VDD-0.2V)(VDD=max,f=0MHz)
ISB2 9 12 mA
1 Allactivecurrentmeasurementsaremeasuredwithoneaddresstransitionpercycleandatminimumcycletime.
MR2A16AElectrical Specifications
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MR2A16A Rev. 10.1, 7/20137 Copyright © Everspin Technologies 2013
MR2A16A3. TIMING SPECIFICATIONS
Table 3.1 Capacitance1
Parameter Symbol Typical Max UnitAddressinputcapacitance CIn - 6 pF
Controlinputcapacitance CIn - 6 pF
Input/Outputcapacitance CI/O - 8 pF
1 f=1.0MHz,dV=3.0V,TA=25°C,periodicallysampledratherthan100%tested.
Table 3.2 AC Measurement Conditions
Figure 3.1 Output Load Test Low and High
Figure 3.2 Output Load Test All Others
Parameter Value UnitLogicinputtimingmeasurementreferencelevel 1.5 V
Logicoutputtimingmeasurementreferencelevel 1.5 V
Logicinputpulselevels 0or3.0 V
Inputrise/falltime 2 ns
Outputloadforlowandhighimpedanceparameters SeeFigure3.1
Outputloadforallothertimingparameters SeeFigure3.2
V
Output
L = 1.5 V
RL = 50 Ω
ZD= 50 Ω
Output
435 Ω
590 Ω
5 pF
3.3 V
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MR2A16A Rev. 10.1, 7/20138 Copyright © Everspin Technologies 2013
MR2A16ATiming Specifications
Parameter Symbol Min Max Unit
Readcycletime tAVAV 35 - ns
Addressaccesstime tAVQV - 35 ns
Enableaccesstime2 tELQV - 35 ns
Outputenableaccesstime tGLQV - 15 ns
Byteenableaccesstime tBLQV - 15 ns
Outputholdfromaddresschange tAXQX 3 - ns
Enablelowtooutputactive3 tELQX 3 - ns
Outputenablelowtooutputactive3 tGLQX 0 - ns
Byteenablelowtooutputactive3 tBLQX 0 - ns
EnablehightooutputHi-Z3 tEHQZ 0 15 ns
OutputenablehightooutputHi-Z3 tGHQZ 0 10 ns
BytehightooutputHi-Z3 tBHQZ 0 10 ns1 Wishighforreadcycle.Powersuppliesmustbeproperlygroundedanddecoupled,andbuscontentionconditionsmustbeminimizedoreliminatedduringreadorwritecycles.
2 Addressesvalidbeforeoratthesametime Egoeslow.3 Thisparameterissampledandnot100%tested.Transitionismeasured±200mVfromthesteady-statevoltage.
Table 3.3 Read Cycle Timing1
Read Mode
Figure 3.3A Read Cycle 1
Figure 3.3B Read Cycle 2
A (ADDRESS)
Q (DATA OUT)
tAVAV
tAXQX
tAVQV
Previous Data Valid
Note: Device is continuously selected (E ≤ VIL, G ≤ VIL).
Data Valid
A (ADDRESS)
E (CHIP ENABLE)
G (OUTPUT ENABLE)
Q (DATA OUT) Data Valid
tAVAV
tAVQVtELQV
tELQX
tBHQZ
tGHQZ
tEHQZ
tBLQVtBLQX
tGLQVtGLQX
LB, UB (BYTE ENABLE)
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MR2A16A Rev. 10.1, 7/20139 Copyright © Everspin Technologies 2013
MR2A16ATiming Specifications
Table 3.4 Write Cycle Timing 1 (W Controlled)1
Parameter Symbol Min Max Unit
Writecycletime2 tAVAV 35 - ns
Addressset-uptime tAVWL 0 - ns
Addressvalidtoendofwrite(Ghigh) tAVWH 18 - ns
Addressvalidtoendofwrite(Glow) tAVWH 20 - ns
Writepulsewidth(Ghigh) tWLWHtWLEH
15 - ns
Writepulsewidth(Glow) tWLWHtWLEH
15 - ns
Datavalidtoendofwrite tDVWH 10 - ns
Dataholdtime tWHDX 0 - ns
WritelowtodataHi-Z3 tWLQZ 0 12 ns
Writehightooutputactive3 tWHQX 3 - ns
Writerecoverytime tWHAX 12 - ns
1 AllwriteoccursduringtheoverlapofElowandWlow.Powersuppliesmustbeproperlygroundedanddecoupledandbuscontentionconditionsmustbeminimizedoreliminatedduringreadandwritecycles.IfGgoeslowatthesametimeorafterWgoeslow,theoutputwillremaininahighimpedancestate.AfterW,EorUB/LBhasbeenbroughthigh,thesignalmustremaininsteady-statehighforaminimumof2ns.TheminimumtimebetweenEbeingassertedlowinonecycletoEbeingassertedlowinasubsequentcycleisthesameastheminimumcycletimeallowedforthedevice.
2 Allwritecycletimingsarereferencedfromthelastvalidaddresstothefirsttransitionaddress.3 Thisparameterissampledandnot100%tested.Transitionismeasured±200mVfromthesteady-statevoltage.Atanygivenvoltageortemperate,tWLQZ(max)<tWHQX(min)
W (WRITE ENABLE)
A (ADDRESS)
E (CHIP ENABLE)
t AVAV
t AVWH t WHAX
t AVWL
t WLEHt WLWH
DATA VALID
t DVWH t WHDX
Q (DATA OUT)
D (DATA IN)
t WLQZ
t WHQX
Hi -Z Hi -Z
Figure 3.4 Write Cycle Timing 1 (W Controlled)
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MR2A16A Rev. 10.1, 7/201310 Copyright © Everspin Technologies 2013
MR2A16ATiming Specifications
Table 3.5 Write Cycle Timing 2 (E Controlled)1
Figure 3.5 Write Cycle Timing 2 (E Controlled)1
Parameter Symbol Min Max Unit
Writecycletime2 tAVAV 35 - ns
Addressset-uptime tAVEL 0 - ns
Addressvalidtoendofwrite(Ghigh) tAVEH 18 - ns
Addressvalidtoendofwrite(Glow) tAVEH 20 - ns
Enabletoendofwrite(Ghigh) tELEHtELWH
15 - ns
Enabletoendofwrite(Glow)3 tELEHtELWH
15 - ns
Datavalidtoendofwrite tDVEH 10 - ns
Dataholdtime tEHDX 0 - ns
Writerecoverytime tEHAX 12 - ns1 AllwriteoccursduringtheoverlapofElowandWlow.Powersuppliesmustbeproperlygroundedanddecoupledandbuscontentionconditionsmustbeminimizedoreliminatedduringreadandwritecycles.IfGgoeslowatthesametimeorafterWgoeslow,theoutputwillremaininahighimpedancestate.AfterW,EorUB/LBhasbeenbroughthigh,thesignalmustremaininsteady-statehighforaminimumof2ns.TheminimumtimebetweenEbeingassertedlowinonecycletoEbeingassertedlowinasubsequentcycleisthesameastheminimumcycletimeallowedforthedevice.
2 Allwritecycletimingsarereferencedfromthelastvalidaddresstothefirsttransitionaddress.3 IfEgoeslowatthesametimeorafterWgoeslow,theoutputwillremaininahigh-impedancestate.IfEgoeshighatthesametimeorbeforeWgoeshigh,theoutputwillremaininahigh-impedancestate.
A (ADDRESS)
E (CHIP ENABLE)
W (WRITE ENABLE)
Q (DATA OUT)
D (DATA IN)
tAVAV
tAVEH tEHAX
tELEH
tEHDXtDVEH
tAVEL
Hi-Z
tELWH
Data Valid
UB, LB (BYTE ENABLE)
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MR2A16A Rev. 10.1, 7/201311 Copyright © Everspin Technologies 2013
Parameter Symbol Min Max Unit
Writecycletime2 tAVAV 35 - ns
Addressset-uptime tAVBL 0 - ns
Addressvalidtoendofwrite(Ghigh) tAVBH 18 - ns
Addressvalidtoendofwrite(Glow) tAVBH 20 - ns
Writepulsewidth(G high) tBLEHtBLWH
15 - ns
Writepulsewidth(Glow) tBLEHtBLWH
15 - ns
Datavalidtoendofwrite tDVBH 10 - ns
Dataholdtime tBHDX 0 - ns
Writerecoverytime tBHAX 12 - ns
1 AllwriteoccursduringtheoverlapofElowandWlow.Powersuppliesmustbeproperlygroundedanddecoupledandbuscontentionconditionsmustbeminimizedoreliminatedduringreadandwritecycles.IfGgoeslowatthesametimeorafterWgoeslow,theoutputwillremaininahighimpedancestate.AfterW,Eor LB/UBhasbeenbroughthigh,thesignalmustremaininsteady-statehighforaminimumof2ns.Ifbothbytecontrolsignalsareasserted,thetwosignalsmusthavenomorethan2nsskewbetweenthem.TheminimumtimebetweenEbeingassertedlowinonecycletoEbeingassertedlowinasubsequentcycleisthesameastheminimumcycletimeallowedforthedevice.
2 Allwritecycletimingsarereferencedfromthelastvalidaddresstothefirsttransitionaddress.
Timing Specifications
Table 3.6 Write Cycle Timing 3 (LB / UB Controlled)1
Figure 3.6 Write Cycle Timing 3 (LB / UB Controlled)
W (WRITE ENABLE)
A (ADDRESS)
E (CHIP ENABLE)
UB, LB (BYTE ENABLED)
t AVAV
t AVEH t BHAX
t AVBL t BLEHt BLWH
Data Valid
t DVBH t BHDX
Q (DATA OUT)
D (DATA IN)
Hi -Z Hi -Z
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MR2A16A Rev. 10.1, 7/201312 Copyright © Everspin Technologies 2013
MR2A16A4. ORDERING INFORMATION
Figure 4.1 Part Numbering System
Carrier Blank = Tray, R = Tape & ReelSpeed 35 nsPackage (YS = TSOP2, MA = FBGA)Temperature RangeBlank = Commercial 0 to + 70 °C
C = Industrial -40 to + 85°C V = Extended -40 to +105 °CM = AEC-Q100 Grade 1 -40 to +125 °C
Die Revision08 = 8-Bit, 16 = 16-bit
A = 3.3v VDD , D = 3.3v VDD and 1.8v. VDDQ
Density 256 = 256 Kb, 0 = 1Mb, 1 =2Mb, 2 =4Mb, 4 =16MbMagnetoresistive RAM (MR)
MR 2 A 16 A V YS 35 R
Part Number Description - Operating Temperature Grade Package Ship Pack Temp Range
MR2A16AYS35 3.3v256Kx16MRAMCommercial 44-TSOP2 Tray 0to+70°C
MR2A16ACYS35 3.3v256Kx16MRAMIndustrial 44-TSOP2 Tray -40to+85°C
MR2A16AVYS35 3.3v256Kx16MRAMExtended 44-TSOP2 Tray -40to+105°C
MR2A16AMYS351 3.3v256Kx16MRAMAEC-Q100Grade1 44-TSOP2 Tray -40to+125 °C
MR2A16AYS35R 3.3v256Kx16MRAMCommercial 44-TSOP2 Tape&Reel 0to+70°C
MR2A16ACYS35R 3.3v256Kx16MRAMIndustrial 44-TSOP2 Tape&Reel -40to+85°C
MR2A16AVYS35R 3.3v256Kx16MRAMExtended 44-TSOP2 Tape&Reel -40to+105°C
MR2A16AMYS35R1 3.3v256Kx16MRAMAEC-Q100Grade1 44-TSOP2 Tape&Reel -40to+125 °C
MR2A16AMA35 3.3v256Kx16MRAMCommercial 48-BGA Tray 0to+70°C
MR2A16ACMA35 3.3v256Kx16MRAMIndustrial 48-BGA Tray -40to+85°C
MR2A16AVMA35 3.3v256Kx16MRAMExtended 48-BGA Tray -40to+105°C
MR2A16AMA35R 3.3v256Kx16MRAMCommercial 48-BGA Tape&Reel 0to+70°C
MR2A16ACMA35R 3.3v256Kx16MRAMIndustrial 48-BGA Tape&Reel -40to+85°C
MR2A16AVMA35R 3.3v256Kx16MRAMExtended 48-BGA Tape&Reel -40to+105°C1 Preliminary Products: These products are classified as Preliminary until the completion of all qualification tests. The specifications in this data sheet are intended to be final but are subject to change. Please check the Everspin web site www.everspin.com for the latest information on product status.
Table 4.1 Available Parts
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MR2A16A Rev. 10.1, 7/201313 Copyright © Everspin Technologies 2013
Figure 5.1 44-TSOP2
MR2A16A5. MECHANICAL DRAWING
44 PLACES
44 PLACES
Print Version Not To Scale1. DimensionsandtolerancesperASMEY14.5M-1994.2. DimensionsinMillimeters.3. Dimensionsdonotincludemoldprotrusion.4. DimensiondoesnotincludeDAMbarprotrusions. DAMBarprotrusionshallnotcausetheleadwidthtoexceed0.58.
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MR2A16A Rev. 10.1, 7/201314 Copyright © Everspin Technologies 2013
Figure 5.2 48-FBGA
MR2A16AMechanical Drawings
Notes:1. Dimensions in Millimeters.2. Dimensions and tolerances per ASME Y14.5M
- 1994.3. Maximum solder ball diameter measured parallel
to DATUM A4. DATUM A, the seating plane is determined by the
spherical crowns of the solder balls.5. Parallelism measurement shall exclude any effect
of mark on top surface of package.
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MR2A16A Rev. 10.1, 7/201315 Copyright © Everspin Technologies 2013
MR2A16A
Revision Date Description of Change
5 Sept21,2007
ChangedMR2A16ATS35CproductdescriptiontoLegacyCommercial.AddedtheNewCom-mericaltemperatureproduct(MR2A16AYS35)information.Table3:MR2A16AYS35Hmax-write=25Oe.Table4:MR2A16AYS35hasa2mspowerupwaitingperiod.Table6:AppliedvaluestoTBD’sinIDDspecifications.
6 Nov12,2007Table2:ChangedIDDAtoIDDRorIDDW.Table13:AddednoteindicatingthatTSandYSarebothvalidpackagecodes.CurrentPartNumberingSystem:Addedcommercial(missinglet-ter)temperaturerange.
7 Sep12,2008ReformatDatasheetforEverSpin,AddBGAPackagingInformation,AddTape&ReelPartNumbers,AddPowerSequencingInfo,CorrectIOHspecofVOHto-100uA,CorrectacTestConditions.
8 July22,2009 AddTSOP2LeadCross-Section,AddProductionNote.Convertedtonewdocumentformat.
9 Dec16,2011 AddedAEC-Q100Grade1productoptionforTSOP2packagetoTable4.1.RevisedTables2.1,2.2and4.1toincludeAEC-Q100Grade1specifications.Newlogodesign.
10 August29,2012 CorrectederrorinTable1.1.CorrectedFigure2.1.ImprovedmagneticimmunityforIndus-trialandExtendedGrades.CorrectedminorerrorsinTable4.1ProductNumbering.
10.1 July30,2013 CorrectedGtoreadGfor44-TSOPType2inFigure1.2.
6. REVISION HISTORY
Information in this document is provided solely to enable system and software implementers to use Everspin Technologies products. There are no express or implied licenses granted hereunder to design or fabricate any integrated circuit or circuits based on the information in this document. Everspin Technolo-gies reserves the right to make changes without further notice to any products herein. Everspin makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Everspin Technologies assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or inci-dental damages. “Typical” parameters, which may be provided in Everspin Technologies data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters including “Typicals” must be validated for each customer application by customer’s technical experts. Everspin Technologies does not convey any license under its patent rights nor the rights of others. Everspin Technologies products are not designed, intended, or authorized for use as compo-nents in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Everspin Technologies product could create a situation where personal injury or death may occur. Should Buyer purchase or use Everspin Technologies products for any such unintended or unauthorized application, Buyer shall indemnify and hold Everspin Technologies and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Everspin Technologies was negligent regarding the design or manufacture of the part. Everspin™ and the Everspin logo are trademarks of Everspin Technologies, Inc. All other product or service names are the property of their respective owners.
©Everspin Technologies, Inc. 2012
How to Reach Us:HomePage:www.everspin.com
E-Mail:[email protected] @[email protected]
USA/Canada/South and Central AmericaEverspinTechnologies1347N.AlmaSchoolRoad,Suite220Chandler,Arizona85224+1-877-347-MRAM(6726)+1-480-347-1111
Europe, Middle East and [email protected]
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Filename: EST00193_MR2A16B_Datasheet_Rev10.pdf
