4Mb 256K x 16 MRAM Memory

MR2A16A

MR2A16A Rev. 11.2, 6/20151Copyright © Everspin Technologies 2015

256K x 16 MRAM Memory• Fast35nsRead/Writecycle• SRAMcompatibletiming,usesexistingSRAMcontrol-

lerswithoutredesign• UnlimitedRead&Writeendurance• Datanon-volatilefor>20yearsattemperature• OnememoryreplacesFlash,SRAM,EEPROMand

BBSRAMinasystemforsimpler,moreefficientdesign• Replacesbattery-backedSRAMsolutionswithMRAM

toimprovereliability• 3.3voltpowersupply• Automaticdataprotectiononpowerloss• Commercial,Industrial,Extendedtemperatures• AEC-Q100Grade1option• AllproductsmeetMSL-3moisturesensitivitylevel• RoHS-compliantSRAMTSOP2andBGAPackages

TheMR2A16Aisa4,194,304-bitmagnetoresistiverandomaccessmemory(MRAM)deviceorga-nizedas262,144wordsof16bits.TheMR2A16AoffersSRAMcompatible35nsread/writetimingwithunlimitedendurance.Dataisalwaysnon-volatileforgreaterthan20years.Dataisautomati-callyprotectedonpowerlossbylow-voltageinhibitcircuitrytopreventwriteswithvoltageoutofspecification.TheMR2A16Aistheidealmemorysolutionforapplicationsthatmustpermanentlystoreandre-trievecriticaldataandprogramsquickly.TheM2A16Aisavailableinasmallfootprint48-pinballgridarray(BGA)packageanda44-pinthinsmalloutlinepackage(TSOPType2).Thesepackagesarecompatiblewithsimilarlow-powerSRAMproductsandothernonvolatileRAMproducts.TheMR2A16Aprovideshighlyreliabledatastorageoverawiderangeoftemperatures.Theprod-uctisofferedwithCommercial(0to+70°C),Industrial(-40to+85°C),Extended(-40to+105°C),andAEC-Q100Grade1(-40to+125°C)operatingtemperaturerangeoptions.

RoHS

FEATURES

INTRODUCTION

48-ballBGA

44-pinTSOP2


MR2A16ATABLE OF CONTENTS

FEATURES .............................................................................................................................................1

INTRODUCTION ...................................................................................................................................1

BLOCK DIAGRAM AND PIN ASSIGNMENTS .......................................................................................4

Figure1–BlockDiagram........................................................................................................................................... 4

Table1–PinFunctions............................................................................................................................................... 4

Figure2–PinDiagramsforAvailablePackages(TopView).......................................................................... 5

Table2–OperatingModes....................................................................................................................................... 5

ABSOLUTE MAXIMUM RATINGS .........................................................................................................6

Table3–AbsoluteMaximumRatings................................................................................................................... 6

OPERATING CONDITIONS ...................................................................................................................7

Power Up and Power Down Sequencing .......................................................................................8

Figure3–PowerUpandPowerDownDiagram............................................................................................... 8

DC CHARACTERISTICS .........................................................................................................................9

Table4–DCCharacteristics...................................................................................................................................... 9

Table5–PowerSupplyCharacteristics................................................................................................................ 9

TIMING SPECIFICATIONS ................................................................................................................. 10

Table6–Capacitance...............................................................................................................................................10

Table7–ACMeasurementConditions..............................................................................................................10

Figure4–OutputLoadTestLowandHigh.......................................................................................................10

Figure5–OutputLoadTestAllOthers...............................................................................................................10

Read Mode .................................................................................................................................... 11

Table8–ReadCycleTiming...................................................................................................................................11

Figure6–ReadCycle1.............................................................................................................................................11

Figure7–ReadCycle2.............................................................................................................................................11

Write Mode .................................................................................................................................... 12

Table9–WriteCycleTiming1(WControlled).................................................................................................12

MR2A16A


Figure8–WriteCycleTiming1(WControlled)...............................................................................................12

Table10–WriteCycleTiming2(EControlled)................................................................................................13

Figure9–WriteCycleTiming2(EControlled).................................................................................................13

Table11–WriteCycleTiming3(LB/UBControlled)....................................................................................14

Figure10–WriteCycleTiming3(LB/UBControlled)..................................................................................14

ORDERING INFORMATION ............................................................................................................... 15

Table12–OrderingPartNumberSystemforParallelI/OMRAM..............................................................15

Table13–MR2A16AOrderingPartNumbers..................................................................................................16

PACKAGE OUTLINE DRAWINGS ....................................................................................................... 17

Figure11–44-TSOP2PackageOutline...............................................................................................................17

Figure12–48-FBGAPackgeOutline...................................................................................................................18

REVISION HISTORY ........................................................................................................................... 19

HOW TO CONTACT US ....................................................................................................................... 20

TABLE OF CONTENTS (CONT’D)


MR2A16A

Figure 1 – Block Diagram

Table 1 – Pin Functions

Signal Name Function A AddressInput

E ChipEnable

W WriteEnable

G OutputEnable

UB UpperByteEnable

LB LowerByteEnable

DQ DataI/O

VDD PowerSupply

VSS Ground

DC DoNotConnect

NC NoConnection

BLOCK DIAGRAM AND PIN ASSIGNMENTS

MR2A16A


A0A1A2A3

DQL0DQL1

VDD

E

VSS

DQL2DQL3

W

A7A8A9

A4

22212019181716151413121110987654321

A6A5

23242526272829303132333435363738394041424344

A15G

DQL7DQL6

VSS

VDD

DQL5DQL4

A14 A13A12A11A10

DC

A17A16

UB LBDQU15DQU14DQU13DQU12

DQU11DQU10DQU9DQU8

1 2 3 4 5 6

LB G A0 A1 A2 NC A

DQU8 UB A3 A4 E DQL0 B

DQU9 DQU10 A5 A6 DQL1 DQL2 C

VSS DQU11

A15

DQL3 VDD D

VDD DQU12 NC A16 DQL4 VSS E

DQU14 DQU13 A14

A13

DQL5 DQL6 F

DQU15 NC

A10

A17

A11

W DQL7 G

NC

A7

A9A8

A12

DC H

Figure 2 – Pin Diagrams for Available Packages (Top View)

44-Pin TSOP Type2 48-Pin BGA

Table 2 – Operating Modes

E 1 G1 W 1 LB 1 UB1 Mode VDD Current DQL[7:0]2 DQU[15:8]2

H X X X X Notselected ISB1,ISB2 Hi-Z Hi-Z

L H H X X Outputdisabled IDDR Hi-Z Hi-Z

L X X H H Outputdisabled IDDR Hi-Z Hi-Z

L L H L H LowerByteRead IDDR DOut Hi-Z

L L H H L UpperByteRead IDDR Hi-Z DOut

L L H L L WordRead IDDR DOut DOut

L X L L H LowerByteWrite IDDW Din Hi-Z

L X L H L UpperByteWrite IDDW Hi-Z Din

L X L L L WordWrite IDDW Din Din

Notes:

1. H=high,L=low,X=don’tcare

2. Hi-Z=highimpedance


MR2A16A

Thisdevicecontainscircuitrytoprotecttheinputsagainstdamagecausedbyhighstaticvoltagesorelectricfields;however,itisadvisedthatnormalprecautionsbetakentoavoidapplicationofanyvoltagegreaterthanmaximumratedvoltagestothesehigh-impedance(Hi-Z)circuits.Thedevicealsocontainsprotectionagainstexternalmagneticfields.Precautionsshouldbetakentoavoidapplicationofanymagneticfieldmoreintensethanthemaximumfieldintensityspecifiedinthemaximumratings.1

Table 3 – Absolute Maximum Ratings

Symbol Parameter Temp Range Package Value Unit

VDD Supplyvoltage2 - - -0.5to4.0 V

VIN Voltageonanypin2 - - -0.5toVDD+0.5 V

IOUT Outputcurrentperpin - - ±20 mA

PD Packagepowerdissipation3 - Note3 0.600 W

TBIAS Temperatureunderbias

Commercial - -10to85

°CIndustrial - -45to95

Extended - -45to110

AEC-Q100Grade1 - -45to130

Tstg StorageTemperature - - -55to150 °C

TLeadLeadtemperatureduringsolder(3minutemax) - - 260 °C

Hmax_writeMaximummagneticfieldduringwrite

Commercial TSOP2,BGA 2,000

A/mIndustrial,ExtendedBGA 2,000

TSOP2 10,000

AEC-Q100Grade1 TSOP2 2,000

Hmax_readMaximummagneticfieldduringreadorstandby

Commercial TSOP2,BGA 8,000

A/mIndustrial,ExtendedBGA 8,000

TSOP2 10,000

AEC-Q100Grade1 TSOP2 8,000

Notes:1. Permanentdevicedamagemayoccurifabsolutemaximumratingsareexceeded.Functionaloperationshouldberestricted

torecommendedoperatingconditions.Exposuretoexcessivevoltagesormagneticfieldscouldaffectdevicereliability.2. AllvoltagesarereferencedtoVSS.3. Powerdissipationcapabilitydependsonpackagecharacteristicsanduseenvironment.

ABSOLUTE MAXIMUM RATINGS

MR2A16A


Parameter Symbol Min Typical Max UnitPowersupplyvoltage1 VDD 3.0 3.3 3.6 V

Writeinhibitvoltage VWI 2.5 2.7 3.01 V

Inputhighvoltage VIH 2.2 - VDD+0.32 V

Inputlowvoltage VIL -0.53 - 0.8 V

TemperatureunderbiasMR2A16A(Commercial)MR2A16AC(Industrial)MR2A16AV(Extended)MR2A16AM(AEC-Q100Grade1)4

TA

0-40-40-40

7085105125

°C

Notes:

1. Thereisa2msstartuptimeonceVDDexceedsVDD,(max).See“PowerUpandPowerDownSequencing”onpage8.2. VIH(max)=VDD+0.3VDC;VIH(max)=VDD+2.0VAC(pulsewidth≤10ns)forI≤20.0mA.3. VIL(min)=-0.5VDC;VIL(min)=-2.0VAC(pulsewidth≤10ns)forI≤20.0mA.4. AEC-Q100Grade1temperatureprofileassumes10%dutycycleatmaximumtemperature(2yearsoutof20yearslife.)

OPERATING CONDITIONS


MR2A16A

TheMRAMisprotectedfromwriteoperationswheneverVDDislessthanVWI.AssoonasVDDexceedsVDD(min),thereisastartuptimeof2msbeforereadorwriteoperationscanstart.Thistimeallowsmemorypowersuppliestostabilize.

TheEandWcontrolsignalsshouldtrackVDDonpoweruptoVDD-0.2VorVIH(whicheverislower)andremainhighforthestartuptime.Inmostsystems,thismeansthatthesesignalsshouldbepulledupwitharesistorsothatsignalremainshighifthedrivingsignalisHi-Zduringpowerup.AnylogicthatdrivesEandWshouldholdthesignalshighwithapower-onresetsignalforlongerthanthestartuptime.

DuringpowerlossorbrownoutwhereVDDgoesbelowVWI,writesareprotectedandastartuptimemustbeobservedwhenpowerreturnsaboveVDD(min).

Figure 3 – Power Up and Power Down Sequencing Timing Diagram

BROWNOUT or POWER LOSS

NORMAL OPERATION

VDD

READ/WRITE INHIBITED

VWI

2 ms

READ/WRITE INHIBITED

VIH

STARTUP

NORMAL OPERATION

2 ms

E

W

RECOVER

VIH

Power Up and Power Down Sequencing

MR2A16A


Parameter Symbol Min Typical Max Unit

Inputleakagecurrent Ilkg(I) - - ±1 μA

Outputleakagecurrent Ilkg(O) - - ±1 μA

Outputlowvoltage(IOL=+4mA)(IOL=+100μA)

VOL - - 0.4VSS+0.2

V

Outputhighvoltage(IOH=-4mA)(IOH=-100μA)

VOH 2.4VDD-0.2

- - V

Table 4 – DC Characteristics

Table 5 – Power Supply Characteristics

Parameter Symbol Typical Max Unit

ACactivesupplycurrent-readmodes1

(IOUT=0mA,VDD=max) IDDR 55 80 mA

ACactivesupplycurrent-writemodes1

(VDD=max)CommercialGradeIndustrialGradeExtendedGradeAEC-Q100Grade

IDDW

105105105105

155165165165

mA

ACstandbycurrent(VDD=max,E=VIH)no other restrictions on other inputs

ISB1 18 28 mA

CMOSstandbycurrent(E≥VDD-0.2VandVIn≤VSS+0.2Vor≥VDD-0.2V)(VDD=max,f=0MHz)

ISB2 9 12 mA

Notes:

1. Allactivecurrentmeasurementsaremeasuredwithoneaddresstransitionpercycleandatminimumcycletime.

DC CHARACTERISTICS


MR2A16ATIMING SPECIFICATIONS

Table 6 – CapacitanceParameter 1 Symbol Typical Max Unit

Addressinputcapacitance CIn - 6 pF

Controlinputcapacitance CIn - 6 pF

Input/Outputcapacitance CI/O - 8 pFNotes:1. f=1.0MHz,dV=3.0V,TA=25°C,periodicallysampledratherthan100%tested.

Table 7 – AC Measurement Conditions

Figure 4 – Output Load Test Low and High

Figure 5 – Output Load Test All Others

Parameter Value UnitLogicinputtimingmeasurementreferencelevel 1.5 V

Logicoutputtimingmeasurementreferencelevel 1.5 V

Logicinputpulselevels 0or3.0 V

Inputrise/falltime 2 ns

Outputloadforlowandhighimpedanceparameters SeeFigure4

Outputloadforallothertimingparameters SeeFigure5

V

Output

L = 1.5 V

RL = 50 Ω

ZD= 50 Ω

Output

435 Ω

590 Ω

5 pF

3.3 V

MR2A16A


Parameter 1 Symbol Min Max Unit

Readcycletime tAVAV 35 - ns

Addressaccesstime tAVQV - 35 ns

Enableaccesstime2 tELQV - 35 ns

Outputenableaccesstime tGLQV - 15 ns

Byteenableaccesstime tBLQV - 15 ns

Outputholdfromaddresschange tAXQX 3 - ns

Enablelowtooutputactive3 tELQX 3 - ns

Outputenablelowtooutputactive3 tGLQX 0 - ns

Byteenablelowtooutputactive3 tBLQX 0 - ns

EnablehightooutputHi-Z3 tEHQZ 0 15 ns

OutputenablehightooutputHi-Z3 tGHQZ 0 10 ns

BytehightooutputHi-Z3 tBHQZ 0 10 ns

Notes:1. Wishighforreadcycle.Powersuppliesmustbeproperlygroundedanddecoupled,andbuscontentionconditionsmust

beminimizedoreliminatedduringreadorwritecycles.

2. AddressesvalidbeforeoratthesametimeEgoeslow.3. Thisparameterissampledandnot100%tested.Transitionismeasured±200mVfromthesteady-statevoltage.

Table 8 – Read Cycle TimingRead Mode

Figure 6 – Read Cycle 1

Figure 7 – Read Cycle 2

A (ADDRESS)

Q (DATA OUT)

tAVAV

tAXQX

tAVQV

Previous Data Valid

Note: Device is continuously selected (E ≤ VIL, G ≤ VIL).

Data Valid

A (ADDRESS)

E (CHIP ENABLE)

G (OUTPUT ENABLE)

Q (DATA OUT) Data Valid

tAVAV

tAVQVtELQV

tELQX

tBHQZ

tGHQZ

tEHQZ

tBLQVtBLQX

tGLQVtGLQX

LB, UB (BYTE ENABLE)


MR2A16A

Table 9 – Write Cycle Timing 1 (W Controlled)Parameter 1 Symbol Min Max Unit

Writecycletime2 tAVAV 35 - ns

Addressset-uptime tAVWL 0 - ns

Addressvalidtoendofwrite(Ghigh) tAVWH 18 - ns

Addressvalidtoendofwrite(Glow) tAVWH 20 - ns

Writepulsewidth(Ghigh)tWLWHtWLEH 15 - ns

Writepulsewidth(Glow)tWLWHtWLEH 15 - ns

Datavalidtoendofwrite tDVWH 10 - ns

Dataholdtime tWHDX 0 - ns

WritelowtodataHi-Z3 tWLQZ 0 12 ns

Writehightooutputactive3 tWHQX 3 - ns

Writerecoverytime tWHAX 12 - ns

Notes:

1. AllwriteoccursduringtheoverlapofElowandWlow.Powersuppliesmustbeproperlygroundedanddecoupledandbuscontentionconditionsmustbeminimizedoreliminatedduringreadandwritecycles.IfGgoeslowatthesametimeorafterWgoeslow,theoutputwillremaininahighimpedancestate.AfterW,EorUB/LBhasbeenbroughthigh,thesignalmustremaininsteady-statehighforaminimumof2ns.TheminimumtimebetweenEbeingassertedlowinonecycletoEbeingassertedlowinasubsequentcycleisthesameastheminimumcycletimeallowedforthedevice.

2. Allwritecycletimingsarereferencedfromthelastvalidaddresstothefirsttransitionaddress.

3. Thisparameterissampledandnot100%tested.Transitionismeasured±200mVfromthesteady-statevoltage.Atanygivenvoltageortemperate,tWLQZ(max)<tWHQX(min)

W (WRITE ENABLE)

A (ADDRESS)

E (CHIP ENABLE)

t AVAV

t AVWH t WHAX

t AVWL

t WLEHt WLWH

DATA VALID

t DVWH t WHDX

Q (DATA OUT)

D (DATA IN)

t WLQZ

t WHQX

Hi -Z Hi -Z

Figure 8 – Write Cycle Timing 1 (W Controlled)

Write Mode

MR2A16A


Table 10 – Write Cycle Timing 2 (E Controlled)

Figure 9 – Write Cycle Timing 2 (E Controlled)



Addressset-uptime tAVEL 0 - ns

Addressvalidtoendofwrite(Ghigh) tAVEH 18 - ns

Addressvalidtoendofwrite(Glow) tAVEH 20 - ns

Enabletoendofwrite(Ghigh)tELEHtELWH 15 - ns

Enabletoendofwrite(Glow)3tELEHtELWH 15 - ns

Datavalidtoendofwrite tDVEH 10 - ns

Dataholdtime tEHDX 0 - ns

Writerecoverytime tEHAX 12 - ns

Notes:

1. AllwriteoccursduringtheoverlapofElowandWlow.Powersuppliesmustbeproperlygroundedanddecoupledandbuscontentionconditionsmustbeminimizedoreliminatedduringreadandwritecycles.IfGgoeslowatthesametimeorafterWgoeslow,theoutputwillremaininahighimpedancestate.AfterW,EorUB/LBhasbeenbroughthigh,thesignalmustremaininsteady-statehighforaminimumof2ns.TheminimumtimebetweenEbeingassertedlowinonecycletoEbeingassertedlowinasubsequentcycleisthesameastheminimumcycletimeallowedforthedevice.


3. IfEgoeslowatthesametimeorafterWgoeslow,theoutputwillremaininahigh-impedancestate.IfEgoeshighatthesametimeorbeforeWgoeshigh,theoutputwillremaininahigh-impedancestate.

A (ADDRESS)

E (CHIP ENABLE)

W (WRITE ENABLE)

Q (DATA OUT)

D (DATA IN)

tAVAV

tAVEH tEHAX

tELEH

tEHDXtDVEH

tAVEL

Hi-Z

tELWH

Data Valid

UB, LB (BYTE ENABLE)


MR2A16A



Addressset-uptime tAVBL 0 - ns

Addressvalidtoendofwrite(Ghigh) tAVBH 18 - ns

Addressvalidtoendofwrite(Glow) tAVBH 20 - ns

Writepulsewidth(Ghigh)tBLEHtBLWH

15 - ns

Writepulsewidth(Glow)tBLEHtBLWH

15 - ns

Datavalidtoendofwrite tDVBH 10 - ns

Dataholdtime tBHDX 0 - ns

Writerecoverytime tBHAX 12 - ns

Notes:

1. AllwriteoccursduringtheoverlapofElowandWlow.Powersuppliesmustbeproperlygroundedanddecoupledandbuscontentionconditionsmustbeminimizedoreliminatedduringreadandwritecycles.IfGgoeslowatthesametimeorafterWgoeslow,theoutputwillremaininahighimpedancestate.AfterW,EorLB/UBhasbeenbroughthigh,thesignalmustremaininsteady-statehighforaminimumof2ns.Ifbothbytecontrolsignalsareasserted,thetwosignalsmusthavenomorethan2nsskewbetweenthem.TheminimumtimebetweenEbeingassertedlowinonecycletoEbeingassertedlowinasubsequentcycleisthesameastheminimumcycletimeallowedforthedevice.


Figure 10 – Write Cycle Timing 3 (LB / UB Controlled)

W (WRITE ENABLE)

A (ADDRESS)

E (CHIP ENABLE)

UB, LB (BYTE ENABLED)

t AVAV

t AVEH t BHAX

t AVBL t BLEHt BLWH

Data Valid

t DVBH t BHDX

Q (DATA OUT)

D (DATA IN)

Hi -Z Hi -Z

Table 11 – Write Cycle Timing 3 (LB / UB Controlled)

MR2A16A


ORDERING INFORMATION

Memory Density Type I/O Width Rev. Temp Package Speed Packing GradeExample Ordering Part Number MR 2 A 16 A C MA 35 R

MRAM MR 256 Kb 2561 Mb 04 Mb 216 Mb 4Async 3.3v A

Async 3.3v Vdd and 1.8v Vddq D

Async 3.3v Vdd and 1.8v Vddq with 2.7v min. Vdd DL

8-bit 816-bit 16Rev A ARev B BCommercial 0 to 70°C BlankIndustrial -40 to 85°C CExtended -40 to 105°C VAEC Q-100 Grade 1 -40 to 125°C M44-TSOP-2 YS48-FBGA MA16-SOIC SC32-SOIC SO35 ns 3545 ns 45Tray BlankTape and Reel REngineering Samples ESCustomer Samples BlankMass Production Blank

Table 12 – Ordering Part Number System for Parallel I/O MRAM


MR2A16A

Table 13 – MR2A16A Ordering Part Numbers

Temp Grade Temp Package Shipping Ordering Part Number

Commercial 0to+70°C

44-TSOP2Tray MR2A16AYS35

TapeandReel MR2A16AYS35R

48-BGATray MR2A16AMA35

TapeandReel MR2A16AMA35R

Industrial -40to+85°C

44-TSOP2Tray MR2A16ACYS35

TapeandReel MR2A16ACYS35R

48-BGATray MR2A16ACMA35

TapeandReel MR2A16ACMA35R

Extended -40to+105°C44-TSOP2

Tray MR2A16AVYS35

TapeandReel MR2A16AVYS35R

48-BGATray MR2A16AVMA35

TapeandReel MR2A16AVMA35R

AutomotiveAEC-Q100Grade1 -40to+125°C 44-TSOP2

Tray MR2A16AMYS35

TapeandReel MR2A16AMYS35R

MR2A16A


Figure 11 – 44-TSOP2 Package Outline

PACKAGE OUTLINE DRAWINGS

44 PLACES

44 PLACES

Print Version Not To Scale1. DimensionsandtolerancesperASMEY14.5M-1994.2. DimensionsinMillimeters.3. Dimensionsdonotincludemoldprotrusion.4. DimensiondoesnotincludeDAMbarprotrusions. DAMBarprotrusionshallnotcausetheleadwidthtoexceed0.58.


MR2A16A

Figure 12 – 48-FBGA Packge Outline

Notes:1. DimensionsinMillimeters.2. DimensionsandtolerancesperASMEY14.5M

-1994.3. Maximumsolderballdiametermeasuredparal-

leltoDATUMA4. DATUMA,theseatingplaneisdeterminedby

thesphericalcrownsofthesolderballs.5. Parallelismmeasurementshallexcludeanyef-

fectofmarkontopsurfaceofpackage.

MR2A16A


Revision Date Description of Change

5 Sept21,2007

ChangedMR2A16ATS35CproductdescriptiontoLegacyCommercial.AddedtheNewCom-mericaltemperatureproduct(MR2A16AYS35)information.Table3:MR2A16AYS35Hmax-write=25Oe.Table4:MR2A16AYS35hasa2mspowerupwaitingperiod.Table6:AppliedvaluestoTBD’sinIDDspecifications.

6 Nov12,2007Table2:ChangedIDDAtoIDDRorIDDW.Table13:AddednoteindicatingthatTSandYSarebothvalidpackagecodes.CurrentPartNumberingSystem:Addedcommercial(missinglet-ter)temperaturerange.

7 Sep12,2008ReformatDatasheetforEverSpin,AddBGAPackagingInformation,AddTape&ReelPartNumbers,AddPowerSequencingInfo,CorrectIOHspecofVOHto-100uA,CorrectacTestConditions.

8 July22,2009 AddTSOP2LeadCross-Section,AddProductionNote.Convertedtonewdocumentformat.

9 Dec16,2011 AddedAEC-Q100Grade1productoptionforTSOP2packagetoTable4.1.RevisedTables2.1,2.2and4.1toincludeAEC-Q100Grade1specifications.Newlogodesign.

10 August29,2012 CorrectederrorinTable1.1.CorrectedFigure2.1.ImprovedmagneticimmunityforIndus-trialandExtendedGrades.CorrectedminorerrorsinTable4.1ProductNumbering.

10.1 July30,2013 CorrectedGtoreadGfor44-TSOPType2inFigure1.2.

11 October14,2013

MR2A16AMYS35/RisreleasedfromPreliminarytofullyqualified.Reformattedtomeetcur-rentstandards.

11.1 May19,2015 RevisedEverspincontactinformation.

11.2 June11,2015 CorrectedJapanSalesOfficetelephonenumber.

REVISION HISTORY


MR2A16A

Everspin Technologies, Inc.

InformationinthisdocumentisprovidedsolelytoenablesystemandsoftwareimplementerstouseEverspinTechnologiesproducts.Therearenoexpressorimpliedlicensesgrantedhereundertodesignorfabricateanyintegratedcircuitorcircuitsbasedontheinformationinthisdocument.EverspinTechnologiesreservestherighttomakechangeswithoutfurthernoticetoanyproductsherein.Everspinmakesnowarranty,representationorguaranteeregardingthesuitabilityofitsproductsforanyparticularpurpose,nordoesEverspinTechnologiesas-sumeanyliabilityarisingoutoftheapplicationoruseofanyproductorcircuit,andspecificallydisclaimsanyandallliability,includingwithoutlimitationconsequentialorincidentaldamages.“Typical”parameters,whichmaybeprovidedinEverspinTechnologiesdatasheetsand/orspecificationscananddovaryindifferentapplicationsandactualperformancemayvaryovertime.Alloperatingparametersincluding“Typicals”mustbevalidatedforeachcustomerapplicationbycus-tomer’stechnicalexperts.EverspinTechnologiesdoesnotconveyanylicenseunderitspatentrightsnortherightsofothers.EverspinTech-nologiesproductsarenotdesigned,intended,orauthorizedforuseascomponentsinsystemsintendedforsurgicalimplantintothebody,orotherapplicationsintendedtosupportorsustainlife,orforanyotherapplicationinwhichthefailureoftheEverspinTechnologiesproductcouldcreateasituationwherepersonalinjuryordeathmayoccur.ShouldBuyerpurchaseoruseEverspinTechnologiesproductsforanysuchunintendedorunauthorizedapplication,BuyershallindemnifyandholdEverspinTechnologiesanditsofficers,employees,subsidiar-ies,affiliates,anddistributorsharmlessagainstallclaims,costs,dam-ages,andexpenses,andreasonableattorneyfeesarisingoutof,directlyorindirectly,anyclaimofpersonalinjuryordeathassociatedwithsuchunintendedorunauthorizeduse,evenifsuchclaimallegesthatEver-spinTechnologieswasnegligentregardingthedesignormanufactureofthepart.Everspin™andtheEverspinlogoaretrademarksofEverspinTechnologies,Inc.Allotherproductorservicenamesaretheproperty

oftheirrespectiveowners.

Copyright©EverspinTechnologies,Inc.2015

HOW TO CONTACT USHome Page:www.everspin.com

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Filename: EST00193_MR2A16A_Datasheet_Rev11.2061115

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