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Analog to DigitalConverters
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Presentation Outline
Introduction: Analog vs. Digital?Examples of ADC Applications
Types of A/D Converters A/D Subsystem used in themicrocontroller chip
Examples of Analog to Digital SignalConversionSuccessive Approximation ADC
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F ir s t Pr e s e n t e r
Byron Johns
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Analog Signals
Analog signals – directly measurable quantitiesin terms of some other quantity
Examples:Thermometer – mercury height rises astemperature risesCar Speedometer – Needle moves farther
right as you accelerateStereo – Volume increases as you turn theknob.
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Digital Signals
Digital Signals – have only two states. Fordigital computers, we refer to binary states, 0and 1. “1” can be on, “0” can be off.
Examples:Light switch can be either on or offDoor to a room is either open or closed
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Examples of A/D Applications
Microphones - take your voice varying pressure waves in theair and convert them into varying electrical signals
Strain Gages - determines the amount of strain (change in
dimensions) when a stress is applied
Thermocouple – temperature measuring device convertsthermal energy to electric energy
VoltmetersDigital Multimeters
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Just what does anA/D converter DO?
Converts analog signals into binary words
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Analog Digital Conversion2-Step Process:
Quantizing - breaking down analog value is aset of finite statesEncoding - assigning a digital word ornumber to each state and matching it to theinput signal
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Step 1: Quantizing
Example:You have 0-10Vsignals. Separate theminto a set of discretestates with 1.25Vincrements. (How didwe get 1.25V? See
next slide…)
OutputStates
Discrete VoltageRanges (V)
0 0.00-1.25
1 1.25-2.50
2 2.50-3.75
3 3.75-5.00
4 5.00-6.25
5 6.25-7.50
6 7.50-8.75
7 8.75-10.0
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QuantizingThe number of possible states that the
converter can output is:N=2n
where n is the number of bits in the AD converter
Example: For a 3 bit A/D converter, N=2 3=8.
Analog quantization size:Q=(Vmax -Vmin)/N = (10V – 0V)/8 = 1.25V
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Encoding
Here we assign thedigital value (binarynumber) to each
state for thecomputer to read.
OutputStates
Output Binary Equivalent
0 000
1 001
2 010
3 011
4 100
5 101
6 110
7 111
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Accuracy of A/D Conversion
There are two ways to best improve accuracy of A/D conversion:
increasing the resolution which improves theaccuracy in measuring the amplitude of theanalog signal.
increasing the sampling rate which increases themaximum frequency that can be measured.
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Resolution
Resolution (number of discrete values the converter canproduce) = Analog Quantization size (Q)(Q) = Vrange / 2^n, where Vrange is the range of analogvoltages which can be represented
limited by signal-to-noise ratio (should be around 6dB)
In our previous example: Q = 1.25V, this is a highresolution. A lower resolution would be if we used a 2-bitconverter, then the resolution would be 10/2^2 = 2.50V.
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Sampling Rate
Frequency at which ADC evaluates analog signal. As wesee in the second picture, evaluating the signal more oftenmore accurately depicts the ADC signal.
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AliasingOccurs when the input signal is changing muchfaster than the sample rate.
For example, a 2 kHz sine wave being sampledat 1.5 kHz would be reconstructed as a 500 Hz(the aliased signal) sine wave.
Nyquist Rule:Use a sampling frequency at least twice as highas the maximum frequency in the signal to avoidaliasing.
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Overall Better Accuracy
Increasing both the sampling rate and the resolutionyou can obtain better accuracy in your AD signals.
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A/D Converter Types By Danny
Carpenter
Converters
Flash ADCDelta-Sigma ADCDual Slope (integrating) ADCSuccessive Approximation ADC
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Flash ADC
Consists of a series of comparators, eachone comparing the input signal to a uniquereference voltage.
The comparator outputs connect to the inputsof a priority encoder circuit, which produces abinary output
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Flash ADC Circuit
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How Flash Works
As the analog input voltage exceeds thereference voltage at each comparator, thecomparator outputs will sequentially saturateto a high state.The priority encoder generates a binarynumber based on the highest-order active
input, ignoring all other active inputs.
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ADC Output
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Flash
AdvantagesSimplest in terms ofoperational theory
Most efficient in termsof speed, very fast
limited only in terms ofcomparator and gatepropagation delays
Disadvantages
Lower resolution
ExpensiveFor each additionaloutput bit, the numberof comparators is
doubledi.e. for 8 bits, 256comparators needed
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Sigma Delta ADC
Over sampled inputsignal goes to theintegrator
Output of integration iscompared to GNDIterates to produce aserial bit streamOutput is serial bitstream with # of 1’sproportional to V in
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Outputs of Delta Sigma
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Sigma-Delta
Advantages
High resolution
No precision externalcomponents needed
Disadvantages
Slow due tooversampling
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Dual Slope Converter
The sampled signal charges a capacitor for a fixedamount of timeBy integrating over time, noise integrates out of theconversionThen the ADC discharges the capacitor at a fixedrate with the counter counts the ADC’s output bits.
A longer discharge time results in a higher count
t
Vin tFIX tmeas
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Successive Approximation ADC By
Stephanie Pohl
A Successive Approximation Register (SAR)is added to the circuitInstead of counting up in binary sequence,this register counts by trying all values of bitsstarting with the MSB and finishing at theLSB.The register monitors the comparators outputto see if the binary count is greater or lessthan the analog signal input and adjusts thebits accordingly
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Successive ApproximationADC Circuit
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Output
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Successive Approximation Advantages
Capable of high speed andreliable
Medium accuracycompared to other ADCtypesGood tradeoff betweenspeed and cost
Capable of outputting thebinary number in serial (onebit at a time) format.
Disadvantages
Higher resolutionsuccessive approximation
ADC’s will be slower Speed limited to ~5Msps
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ADC Resolution Comparison
0 5 10 15 20 25
Sigma-Delta
Successive Approx
Flash
Dual Slope
Resolution (Bits)
Type Speed (relative) Cost (relative)Dual Slope Slow Med
Flash Very Fast High
Successive Appox Medium – Fast Low
Sigma-Delta Slow Low
ADC Types Comparison
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Successive ApproximationExample
10 bit resolution or0.0009765625V of VrefVin= .6 volts
Vref=1voltsFind the digital value ofVin
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Successive Approximation
MSB (bit 9)Divided V ref by 2Compare V ref /2 with V in If Vin is greater than V ref /2 , turn MSB on (1)If Vin is less than V ref /2 , turn MSB off (0)Vin =0.6V and V=0.5
Since V in>V, MSB = 1 (on)
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Successive Approximation
Next Calculate MSB-1 (bit 8)Compare V in=0.6 V to V=V ref /2 + V ref /4= 0.5+0.25 =0.75VSince 0.6<0.75, MSB is turned off
Calculate MSB-2 (bit 7)Go back to the last voltage that caused it to be turned on(Bit 9) and add it to V ref /8, and compare with V in Compare V in with (0.5+V ref /8)=0.625
Since 0.6<0.625, MSB is turned off
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Successive Approximation
Calculate the state of MSB-3 (bit 6)Go to the last bit that caused it to be turned on (Inthis case MSB-1) and add it to V ref /16, andcompare it to V in Compare V in to V= 0.5 + V ref /16= 0.5625Since 0.6>0.5625, MSB-3=1 (turned on)
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Successive Approximation
This process continues for all the remainingbits.
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The HC11 and ADCBy Harry “Bo” Marr
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ADC Flow Diagram in HC11
8 channel/bit inputVRL = 0 volts
VRH = 5 voltsDigital input on PE
01234567
Port E (analog input)
Pin:
Analog Multiplexer
A/D ConverterResultRegisterInterface
ADR1 - result 1
ADR2 - result 2
ADR3 - result 3
ADR4 - result 4
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PE0
AN0
PE1
AN1
PE2
AN2
PE3 AN3
PE4
AN4
PE5
AN5
PE6
AN6
PE7 AN7
ANALOGMUX
8-bits CAPACITIVE DACWITH SAMPLE AND HOLD
SUCCESSIVE APPROXIMATIONREGISTER AND CONTROL
V RH
VRL
RESULT REGISTER INTERFACE
ADR1 ADR2 ADR3 ADR4
ADCTL A/D CONTROL
C C F
S C A
N
M UL T
C D
C C
C B
C A
INTERNALDATA BUS
P 64 M68HC11 Family Data Sheet
Stuctural Diagram of ADC onHC11
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ADC by Clock cycle
E Clock cycles:
Conversion Sequence
Sample (12) Bit 7 (4) 6 (2) _ (2) 0 (2) End(2)
Successive approximation
0 32 64 96
1st, ADR1 2 nd, ADR2 3 rd, ADR3 4 th, ADR4 CCF
ADPU = 1
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0 0 0 0 0Bit: 014 3 267 5
CCF |No Op| SCAN |MULT | CD | CC | CB | CA
• CCF: (1) after conversion cycle, (0) when written to.• SCAN: Continuous (1) or Not (0)• MULT: Multi-Channel (1) or Single Channel (0)
0 = Single Channel is read 4 times• CD:CC:CB:CA = 0000 – 0111 Chooses input channel
Chooses Channel Group when MULT = 1• Pg 27 – 28 in Reference Manual
0 0
ADCTL Register$1030
0
-
Read
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Options Register$1039
1 0 0 1 0 0
Bit: 014 3 267 5
ADPU |CSEL | IRQE |DLY | CME | NoOp| CR1 | CR0
• ADPU: Power up (1) wait 100ms, No conversion (0)• CSEL: use internal system clock (1), use E-clock (0)• IRQE: Falling Edge interupt (1), low level interrupt(0)• DLY: Delay enabled (1), Delay disabled (0)• CME: Monitor Clock (1), Don ’ t monitor clock (0) • CR[1:0] = Divide E clock by 1, 4, 16, 64.• 38 in reference manual
-1
A l Di i l R l
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Analog to Digital ResultsRegister: $1031 - $1034
0 0 0 0 1 0
Bit: 014 3 267 5
0 0
ADR2 ($1032)
• Register $1032 = $02• Options Register ($1039) = $80• ADCTL Register ($1030) = $00• Just read in signal between 19.2 – 39.0 mV on pin E1!
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Turn on charge pump
and select clock source
OPTION EQU $1039 ADCTL EQU $1030 ADR1 EQU $1031 ADRESULT RMB 1
ORG $2000LDAA #$80 ;ADPU=1,CSEL=0STAA OPTION ; “
Delay for charge pumpto stabilizeLDY #30 ;delay for 105 s
DELAY DEYBNE DELAYLDAA #$10 ;SCAN=0,MULT=1,CHAN GRP=00STAA ADCTL ; start conversionLDX #ADCTL ;check for complete flagBRCLR 0,X #$80 * ;CCF is bit 7LDAA ADR1 ;read chan. 0STAA ADRESULT ;store in resultSWI
Set ADCTL tostart conversion
Wait until conv. complete
Read result
ADPU CR1 CR2OPTION ($1039) CSEL IREQ DLY CME 0
CCF CB CA ADCTL ($1030) 0 SCAN MULT CD CC
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References
Ron Bishop, “Basic Microprocessors and the 6800”,Hayden Book Company Inc., 1979Motorola, “MC68HC11E Family Data Sheet”,
Motorola, Inc., Rev. 5, 2003.Motorola, “MC68HC11 Reference Manual”, Motorola,Inc., Rev. 4, 2002.Motorola, “MC68HC11 Programming ReferenceGuide”, Motorola, Inc., Rev. 2, 2003.
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Any Questions?