5 4 3 2 1 Petra UMA Schematics Document Ivy...

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Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.

Petra Uma -1

Cover PageA3

1 103Wednesday, February 22, 2012

<Core Design>

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Petra Uma -1

Cover PageA3


<Core Design>

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Petra Uma -1

Cover PageA3


<Core Design>

ANNIE: ONLY FOR ANNIE solution.PSL: KBC795 PSL circuit for 10mW solution installed.10mW: External circuit for 10mW solution installed.65W: for 65W adaptor installed.90W: for 90W adaptor installed.

DY :None InstalledDIS:DIS installedDIS_Muxless :BOTH DIS or Muxless installedDIS_PX:BOTH DIS or PX installedDIS_PX_Muxless:DIS or PX or Muxless installed.Muxless: Muxless installed.(PX4.0)PX:MUX installed.(PX3.0)PX_Muxless:BOTH PX or Muxless installed.UMA:UMA installedUMA_Muxless:BOTH UMA or Muxless installedUMA_PX_Muxless:UMA or PX or Muxless installed

Intel PCH

UMA Schematics DocumentIvy Bridge

Petra

WWW.MANUALS.CLAN.SU

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Petra Uma -1

Block DiagramA3

2 103Monday, January 07, 2013

<Core Design>

Title


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Petra Uma -1

Block DiagramA3


<Core Design>

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Petra Uma -1

Block DiagramA3


<Core Design>

286925

69

PCIE x 1USB x 1

60 71LPC debug port

Project code : 91.4VM01.001PCB P/N : 48.4VM02.001PCB No. : 11324Revision : -1

NCT 7718W

ALC271X

DMIx4

LAN

SPI

Flash ROM8MB

51HDMIHDMI

RTL8411

KBC

ThermalInt. KB

LPC Bus

DDRIII1600/1333

Intel CPU17W/GT2 DDRIII 1333/1600 Channel A Slot 0

14

4,5,6,7,8,9,10,11,12,13

Left Side:USB3.0 x 1

CAMERA 49

Mini-Card and BT802.11a/b/g

LVDS

Feature Port(CRT+LAN)

Intel

56

LCD

(RGB CRT)

ODD

56

4 USB 3.0 / 14 USB 2.0/1.1 ports

High Definition Audio

SATA

SATA ports (6)

ACPI 1.1

LPC I/F

HDD

SD/MMC

AzaliaCODEC

USB2.0 x 1

29

SPEAKER

COMBO

Internal Analog MIC

ETHERNET (10/100/1000Mb)

PCIE ports (8)

NPCE885P

28Fan

27

49

17,18,19,20,21,22,23,24,25,26

TouchPAD

FDIx4x2(UMA only)

AZALIA

65

31

50

SMBus

PCIE x 1

Ivy BridgeSandy Bridge

PCH:HM70/77Panther Point

(USB2.0 and USB3.0)co-lay x 1

(SATA3_6Gb/s)

62

74

BT+

40

OUTPUTSBQ24727

INPUTS

CHARGER

DCBATOUT

3D3V_AUX_S5

RT8223MGQW

DCBATOUT 5V_S5

OUTPUTS

3D3V_S5

SYSTEM DC/DC

INPUTS5V_AUX_S5

41

42~43ISL95836HRTZINPUTS

VCC_CORE

OUTPUTS

CPU DC/DC

DCBATOUT

VCC_GFXCORE

ISL95836HRTZ

DCBATOUT

OUTPUTS

SYSTEM DC/DC

INPUTS

44

1D05V_VTT

TPS51218DSCROUTPUTS

DCBATOUT

INPUTS

SYSTEM DC/DC45

0D75V_S0

SYSTEM DC/DCRT8207LGQW

DDR_VREF_S3

OUTPUTS1D5V_S3

INPUTS

DCBATOUT

46

26

INPUTS

LDO

OUTPUTSRT9025-25ZSP

3D3V_S0 1D8V_S0

47

G978INPUTS OUTPUTS

LDO48

1D05V_VTT 0D85V_S0

26

PCB LAYER

L1:TopL2:VCCL3:Signal

L4:SignalL5:GNDL6:Bottom

eDP

co-lay

USB2.0 x 261

Left Side:USB2.0 x 2

Feature Port(CRT+LAN)LAN

50

DDRIII1600/1333

DDRIII 1333/1600 Channel A Slot 115

WWW.MANUALS.CLAN.SU

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

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Petra Uma -1

Table of ContentA3


<Core Design>

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Petra Uma -1

Table of ContentA3


<Core Design>

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Petra Uma -1

Table of ContentA3


<Core Design>

PCIE Routing

LANE2

LANE3 Card Reader

Onboard LANLANE4

Mini Card1(WLAN)SATA Table

Pair

SATA

Device

0

5

4

3

2

1

HDD1

ODD

N/A

HDD2

N/A

ESATA

LANE1 Mini Card2(WWAN)

LANE5

LANE6

LANE7

LANE8 New Card

Intel GBE LAN

CFG[6:5]

CFG[7]

Processor Strapping

CFG[2]

Disabled - No Physical Display Port attached toEmbedded DisplayPort.CFG[4]

Pin Name Strap Description Configuration (Default value for each bit is 1 unless specified otherwise)

1:

Huron River Schematic Checklist Rev.0_7

0:PCI-Express StaticLane Reversal

Normal Operation. Lane Numbers Reversed 15 -> 0, 14 -> 1, ...

DefaultValue

PCI-ExpressPort BifurcationStraps

11 : x16 - Device 1 functions 1 and 2 disabled10 : x8, x8 - Device 1 function 1 enabled ;function 2 disabled01 : Reserved - (Device 1 function 1 disabled ;function 2 enabled)00 : x8, x4, x4 - Device 1 functions 1 and 2enabled

PEG DEFER TRAINING

1

0

1

1:

0:Enabled - An external Display Port device isconnectd to the EMBEDDED display Port

11

1:

0: PEG Train immediately following xxRESETB de assertion PEG Wait for BIOS for training

SPKR

Name Schematics Notes

HAD_DOCK_EN#/GPIO[33]

HDA_SDO Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#.

HDA_SYNC

Huron River Schematic Checklist Rev.0_7

INIT3_3V# Weak internal pull-up. Leave as "No Connect".

GNT3#/GPIO55GNT2#/GPIO53GNT1#/GPIO51

Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#.

GPIO8 on PCH is the Integrated Clock Enable strap and is required to be pulled-downusing a 1k +/- 5% resistor. When this signal is sampled high at the rising edge ofRSMRST#, Integrated Clocking is enabled, When sampled low, Buffer Through Mode isenabled.

PCH Strapping

SPI_MOSI

Internal weak Pull-down. Connect to Vcc3_3 with 8.2-kΩ- 10-kΩ weak pull-up resistor.

NV_ALE

Enable Danbury:

Disable Danbury:

NC_CLE DMI termination voltage. Weak internal pull-up. Do not pull low.

GPIO15

GPIO8

Reboot option at power-upDefault Mode:No Reboot Mode with TCO Disabled:

Connect to Vcc3_3 with 8.2-k? weak pull-up resistor.

Left floating, no pull-down required.

Connect to +NVRAM_VCCQ with 8.2-kohm weak pull-up resistor [CRB has it pulled up with 1-kohm no-stuff resistor]

Leave floating (internal pull-down)

Low (0) - Flash Descriptor Security will be overridden. Also,when this signals is sampled on the rising edge of PWROK then it will also disable Intel ME and its features.High (1) - Security measure defined in the Flash Descriptor will be enabled.Platform design should provide appropriate pull-up or pull-down depending on the desired settings. If a jumper option is used to tie this signal to GND asrequired by the functional strap, the signal should be pulled low through a weakpull-down in order to avoid asserting HDA_DOCK_EN# inadvertently. Note: CRB recommends 1-kohm pull-down for FD Override. There is an internalpull-up of 20 kohm for DA_DOCK_EN# which is only enabled at boot/reset forstrapping functions.

GPIO27

Default = Do not connect (floating)High(1) = Enables the internal VccVRM to have a clean supply foranalog rails. No need to use on-board filter circuit.Low (0) = Disables the VccVRM. Need to use on-board filtercircuits for analog rails.

Voltage RailsVOLTAGE DESCRIPTION

ACTIVE INPOWER PLANE

CPU Core RailGraphics Core Rail

AC Brick Mode only

Legacy WOL

Powered by Li Coin Cell in G3 and +V3ALW in Sx

3D3V_AUX_KBC

3.3V

DSW, Sx ON for supporting Deep Sleep states

S0

S3

All S states

WOL_EN

G3, Sx

5V_S03D3V_S01D8V_S01D5V_S01D05V_VTT0D85V_S00D75V_S0VCC_COREVCC_GFXCORE1D8V_VGA_S03D3V_VGA_S01V_VGA_S0

5V3.3V1.8V1.5V1.05V0.95 - 0.85V0.75V0.35V to 1.5V0.4 to 1.25V1.8V3.3V1V

5V1.5V0.75V

5V_USBX_S31D5V_S3DDR_VREF_S3

BT+DCBATOUT5V_S55V_AUX_S53D3V_S53D3V_AUX_S5

6V-14.1V6V-14.1V5V5V3.3V3.3V

3.3V3D3V_LAN_S5

3.3V

3D3V_AUX_S5

GNT[3:0]# functionality is not available on Mobile.Mobile: Used as GPIO onlyPull-up resistors are not required on these signals. If pull-ups are used, they should be tied to the Vcc3_3power rail.

Enable Danbury:

Disable Danbury:

Low (1) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with noconfidentiality High (1) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with confidentialityNote : This is an un-muxed signal.This signal has a weak internal pull-down of 20 kohm which is enabled when PWROK is low. Sampled at rising edge of RSMRST#.CRB has a 1-kohm pull-up on this signal to +3.3VA rail.

SML1_CLK/SML1_DATA

PCH_SMBDATA/PCH_SMBCLKPCH_SMBDATA/PCH_SMBCLKPCH_SMBDATA/PCH_SMBCLKPCH_SMBDATA/PCH_SMBCLK

Device

I C / SMBus Addresses2

EC SMBus 1BatteryCHARGER

EC SMBus 2PCHeDP

PCH SMBusSO-DIMMA (SPD)SO-DIMMB (SPD)Digital PotG-SensorMINI

BAT_SCL/BAT_SDA

SMBus ADDRESSES

HURON RIVER ORBAddress Hex Bus Ref Des

USB3.0

Dock

USB Table

13

EDP CAMERA

12

X

Mini Card1 (WLAN)

Fingerprint

X

New Card

USB Ext. port 2

10

0

11

USB Ext. port 1 (HS)

Pair

4

5

2

3

1

Device

6

7

8

9

BLUETOOTH

Touch Panel / 3G SIM

CARD READER

USB Ext. port 4 / E-SATA /USB CHARGER

CAMERA

Mini Card2 (WWAN) BAT_SCL/BAT_SDABAT_SCL/BAT_SDA

SML1_CLK/SML1_DATASML1_CLK/SML1_DATA

PCH_SMBDATA/PCH_SMBCLK

PCH_SMBDATA/PCH_SMBCLKWWW.MANUALS.CLAN.SU

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

PEG_IRCOMP_R

DP_COMP

FDI_TXP4FDI_TXP5

DMI_TXN0DMI_TXN1DMI_TXN2DMI_TXN3

DMI_TXP0DMI_TXP1DMI_TXP2DMI_TXP3

DMI_RXN0DMI_RXN1DMI_RXN2DMI_RXN3

DMI_RXP0DMI_RXP1DMI_RXP2DMI_RXP3

FDI_TXP6FDI_TXP7

FDI_TXN0FDI_TXN1

FDI_TXN3FDI_TXN4FDI_TXN5FDI_TXN6FDI_TXN7

FDI_TXN2

FDI_TXP0FDI_TXP1FDI_TXP2FDI_TXP3

DP_HPD#

1D05V_VTT_CPU

1D05V_VTT_CPU

DMI_RXN[3:0]19

DMI_RXP[3:0]19

DMI_TXN[3:0]19

DMI_TXP[3:0]19

FDI_TXN[7:0]19

FDI_TXP[7:0]19

FDI_FSYNC019FDI_FSYNC119

FDI_INT19

FDI_LSYNC019FDI_LSYNC119

DP_HPD#49

DP_AUXP_CPU49DP_AUXN_CPU49

DP_TXP0_CPU49DP_TXP1_CPU49

DP_TXN0_CPU49DP_TXN1_CPU49

Title


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Petra Uma -1

CPU (PCIE/DMI/FDI)A3

4 103Tuesday, July 10, 2012

<Core Design>

Title


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Petra Uma -1



<Core Design>

Title


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Petra Uma -1



<Core Design>

SSID = CPU

12

R403100KR2J-4-GPDY

R403100KR2J-4-GPDY

DMI_RX#0M2

DMI_RX#1P6

DMI_RX#2P1

DMI_RX#3P10

DMI_RX0N3

DMI_RX1P7

DMI_RX2P3

DMI_RX3P11

DMI_TX#0K1

DMI_TX#1M8

DMI_TX#2N4

DMI_TX#3R2

DMI_TX0K3

DMI_TX1M7

DMI_TX3T3DMI_TX2P4

FDI0_TX#0U7

FDI0_TX#1W11

FDI0_TX#2W1

FDI0_TX#3AA6

FDI1_TX#0W6

FDI1_TX#1V4

FDI1_TX#2Y2

FDI1_TX#3AC9

FDI0_TX0U6

FDI0_TX1W10

FDI0_TX2W3

FDI0_TX3AA7

FDI1_TX0W7

FDI1_TX1T4

FDI1_TX2AA3

FDI1_TX3AC8

FDI0_FSYNCAA11

FDI1_FSYNCAC12

FDI_INTU11

FDI0_LSYNCAA10

FDI1_LSYNCAG8

PEG_ICOMPI G3

PEG_ICOMPO G1

PEG_RCOMPO G4

PEG_RX#0 H22

PEG_RX#1 J21

PEG_RX#2 B22

PEG_RX#3 D21

PEG_RX#4 A19

PEG_RX#5 D17

PEG_RX#6 B14

PEG_RX#7 D13

PEG_RX#8 A11

PEG_RX#9 B10

PEG_RX#10 G8

PEG_RX#11 A8

PEG_RX#12 B6

PEG_RX#13 H8

PEG_RX#14 E5

PEG_RX#15 K7

PEG_RX0 K22

PEG_RX1 K19

PEG_RX2 C21

PEG_RX3 D19

PEG_RX4 C19

PEG_RX5 D16

PEG_RX6 C13

PEG_RX7 D12

PEG_RX8 C11

PEG_RX9 C9

PEG_RX10 F8

PEG_RX11 C8

PEG_RX12 C5

PEG_RX13 H6

PEG_RX14 F6

PEG_RX15 K6

PEG_TX#0 G22

PEG_TX#1 C23

PEG_TX#2 D23

PEG_TX#3 F21

PEG_TX#4 H19

PEG_TX#5 C17

PEG_TX#6 K15

PEG_TX#7 F17

PEG_TX#8 F14

PEG_TX#9 A15

PEG_TX#10 J14

PEG_TX#11 H13

PEG_TX#12 M10

PEG_TX#13 F10

PEG_TX#14 D9

PEG_TX#15 J4

PEG_TX0 F22

PEG_TX1 A23

PEG_TX2 D24

PEG_TX3 E21

PEG_TX4 G19

PEG_TX5 B18

PEG_TX6 K17

PEG_TX7 G17

PEG_TX8 E14

PEG_TX9 C15

PEG_TX10 K13

PEG_TX11 G13

PEG_TX12 K10

PEG_TX13 G10

PEG_TX14 D8

PEG_TX15 K4

EDP_AUXAF4EDP_AUX#AG4

EDP_TX0AC1

EDP_TX1AA4

EDP_TX2AE10

EDP_TX3AE6

EDP_COMPIOAF3

EDP_HPD#AG11EDP_ICOMPOAD2

EDP_TX#0AC3

EDP_TX#1AC4

EDP_TX#2AE11

EDP_TX#3AE7PCI EXPRESS -- GRAPHICS

DMI

Intel(R) FDI

eDP

1 OF 9CPU1A

IVY-BRIDGE-GP-NF

71.00IVY.A0U

PCI EXPRESS -- GRAPHICS

DMI

Intel(R) FDI

eDP

1 OF 9CPU1A

IVY-BRIDGE-GP-NF

71.00IVY.A0U

1 2R402 24D9R2F-L-GPR402 24D9R2F-L-GP

1 2R40124D9R2F-L-GPR40124D9R2F-L-GP

WWW.MANUALS.CLAN.SU

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

XDP_DBRESET#

XDP_TDO

BUF_CPU_RST#

H_PROCHOT#

H_PROCHOT#_R

XDP_DBRESET#

BUF_CPU_RST#

XDP_TRST#XDP_TDO

SM_RCOMP_0SM_RCOMP_1SM_RCOMP_2

XDP_TRST#

1D05V_VTT_CPU

3D3V_S0

1D05V_VTT_CPU

H_PM_SYNC19

H_PECI22,27

CLK_EXP_P 20CLK_EXP_N 20

H_SNB_IVB#22

H_PROCHOT#27,42

H_THERMTRIP#22,36

H_CPUPWRGD22,36,97

VDDPWRGOOD37

PLT_RST#18,27,31,36,65,71,97

CLK_DP_P 20CLK_DP_N 20

SM_DRAMRST# 37

Title


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Petra Uma -1

CPU (THERMAL/CLOCK/PM )

Custom


<Core Design>

Title


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Petra Uma -1


Custom


<Core Design>

Title


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Petra Uma -1


Custom


<Core Design>

SSID = CPU

Signal Routing Guideline:SM_RCOMP keep routing length less than 500 mils.

1 2R507 25D5R2F-GPR507 25D5R2F-GPSM_RCOMP1 BE43

SM_RCOMP2 BG43

SM_DRAMRST# AT30

SM_RCOMP0 BF44

BCLK# H2BCLK J3

DPLL_REF_CLK# AG1DPLL_REF_CLK AG3

CATERR#C49

PECIA48

PROCHOT#C45

THERMTRIP#D45

SM_DRAMPWROKBE45

RESET#D44

PRDY# N53

PREQ# N55

TCK L56

TMS L55

TRST# J58

TDI M60

TDO L59

DBR# K58

BPM#0 G58

BPM#1 E55

BPM#2 E59

BPM#3 G55

BPM#4 G59

BPM#5 H60

BPM#6 J59

BPM#7 J61

PM_SYNCC48

PROC_DETECT#C57

PROC_SELECT#F49

UNCOREPWRGOODB46

CLOCKS

MISC

THERMAL

PWR MANAGEMENT

DDR3

MISC

JTAG & BPM

2 OF 9CPU1B

IVY-BRIDGE-GP-NF

71.00IVY.A0U

CLOCKS

MISC

THERMAL

PWR MANAGEMENT

DDR3

MISC

JTAG & BPM

2 OF 9CPU1B

IVY-BRIDGE-GP-NF

71.00IVY.A0U

1 2R5024K99R2F-L-GP

R5024K99R2F-L-GP

12

C502SC47P50V2JN-3GPC502SC47P50V2JN-3GP

1 2R508 200R2F-L-GPR508 200R2F-L-GP

1234 5

678

RN503SRN1K5J-1-GPRN503SRN1K5J-1-GP

1 2R506 140R2F-GPR506 140R2F-GP

12 3

4

RN501SRN51J-GPRN501SRN51J-GP

1 2

R50162R2J-GPR50162R2J-GP

1 2R50310KR2J-L-GP

R50310KR2J-L-GP

1 2R51356R2J-L1-GP

R51356R2J-L1-GP

WWW.MANUALS.CLAN.SU

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

M_A_DQ44

M_A_DQ36

M_A_DQ47

M_A_DQ40M_A_DQ39

M_A_DQ37

M_A_DQ35M_A_DQ34

M_A_DQ59

M_A_DQ54M_A_DQ53

M_A_DQ63

M_A_DQ60M_A_DQ61

M_A_DQ58

M_A_DQ51

M_A_DQ48

M_A_DQ57

M_A_DQ55

M_A_DQ49M_A_DQ50

M_A_DQ62

M_A_DQ52

M_A_DQ56

M_A_DQ0M_A_DQ1M_A_DQ2M_A_DQ3

M_A_DQ7

M_A_DQ5M_A_DQ4

M_A_DQ6

M_A_DQ12

M_A_DQ10

M_A_DQ13

M_A_DQ9M_A_DQ8

M_A_DQ11

M_A_DQ15M_A_DQ14

M_A_DQ27

M_A_DQ25

M_A_DQ20M_A_DQ19

M_A_DQ30

M_A_DQ18

M_A_DQ16

M_A_DQ28

M_A_DQ17

M_A_DQ26

M_A_DQ31

M_A_DQ29

M_A_DQ22M_A_DQ23M_A_DQ24

M_A_DQ21

M_A_DQ46

M_A_DQ42

M_A_DQ38

M_A_DQ32

M_A_DQ45

M_A_DQ33

M_A_DQ43

M_A_DQ41

M_B_DQ0M_B_DQ1M_B_DQ2M_B_DQ3M_B_DQ4M_B_DQ5M_B_DQ6M_B_DQ7M_B_DQ8M_B_DQ9M_B_DQ10M_B_DQ11

M_B_DQ15

M_B_DQ13M_B_DQ12

M_B_DQ14

M_B_DQ16M_B_DQ17M_B_DQ18M_B_DQ19

M_B_DQ23

M_B_DQ21M_B_DQ20

M_B_DQ22

M_B_DQ28

M_B_DQ26

M_B_DQ29

M_B_DQ25

M_B_DQ31

M_B_DQ24

M_B_DQ27

M_B_DQ30


M_B_DQ39

M_B_DQ37M_B_DQ36

M_B_DQ38

M_B_DQ44

M_B_DQ42

M_B_DQ45

M_B_DQ41

M_B_DQ47

M_B_DQ40

M_B_DQ43

M_B_DQ46


M_B_DQ55

M_B_DQ53M_B_DQ52

M_B_DQ54

M_B_DQ60

M_B_DQ58

M_B_DQ61

M_B_DQ57

M_B_DQ63

M_B_DQ56

M_B_DQ59

M_B_DQ62

M_A_DQS4M_A_DQS3

M_A_DQS5M_A_DQS6M_A_DQS7

M_A_DQS2M_A_DQS1M_A_DQS0

M_A_A7

M_A_A12

M_A_A14M_A_A13

M_A_A9

M_A_A15

M_A_A10

M_A_A0

M_A_A6

M_A_A8

M_A_A1M_A_A2M_A_A3M_A_A4M_A_A5

M_A_A11

M_A_DQS#4M_A_DQS#5M_A_DQS#6M_A_DQS#7

M_A_DQS#3M_A_DQS#2M_A_DQS#1M_A_DQS#0

M_B_DQS0M_B_DQS1M_B_DQS2M_B_DQS3M_B_DQS4M_B_DQS5M_B_DQS6M_B_DQS7

M_B_DQS#3M_B_DQS#2M_B_DQS#1M_B_DQS#0

M_B_DQS#7M_B_DQS#6M_B_DQS#5M_B_DQS#4

M_B_A5M_B_A6M_B_A7M_B_A8M_B_A9M_B_A10M_B_A11M_B_A12M_B_A13M_B_A14M_B_A15

M_B_A4M_B_A3M_B_A2M_B_A1M_B_A0

M_A_DQ[63:0]14M_B_DQ[63:0]15

M_A_DQS#[7:0] 14

M_A_A[15:0] 14

M_A_DQS[7:0] 14

M_A_DIM0_CKE0 14

M_A_DIM0_CKE1 14

M_A_DIM0_CS#0 14M_A_DIM0_CS#1 14

M_A_DIM0_ODT0 14M_A_DIM0_ODT1 14

M_A_DIM0_CLK_DDR0 14M_A_DIM0_CLK_DDR#0 14


M_B_A[15:0] 15

M_B_DQS[7:0] 15

M_B_DQS#[7:0] 15

M_B_DIM0_CKE0 15

M_B_DIM0_CKE1 15

M_B_DIM0_CS#0 15M_B_DIM0_CS#1 15

M_B_DIM0_ODT0 15M_B_DIM0_ODT1 15

M_B_DIM0_CLK_DDR0 15M_B_DIM0_CLK_DDR#0 15


M_A_BS014

M_A_CAS#14M_A_RAS#14M_A_WE#14

M_A_BS114M_A_BS214

M_B_CAS#15M_B_RAS#15M_B_WE#15

M_B_BS015M_B_BS115M_B_BS215

Title


Date: Sheet of


Petra Uma -1

CPU (DDR)A3


<Core Design>

Title


Date: Sheet of


Petra Uma -1

CPU (DDR)A3


<Core Design>

Title


Date: Sheet of


Petra Uma -1

CPU (DDR)A3


<Core Design>

SSID = CPU

SA_CK0 AU36

SA_CK1 AT40

SA_CK#0 AV36

SA_CK#1 AU40

SA_CKE0 AY26

SA_CKE1 BB26

SA_CS#0 BB40

SA_CS#1 BC41

SA_ODT0 AY40

SA_ODT1 BA41

SA_DQS0 AJ11

SA_DQS#0 AL11

SA_DQS1 AR10

SA_DQS#1 AR8

SA_DQS2 AY11

SA_DQS#2 AV11

SA_DQS3 AU17

SA_DQS4 AW45

SA_DQS#4 AV45

SA_DQS5 AV51

SA_DQS#5 AY51

SA_DQS6 AT56

SA_DQS#6 AT55

SA_DQS7 AK54

SA_DQS#7 AK55

SA_MA0 BG35

SA_MA1 BB34

SA_MA2 BE35

SA_MA3 BD35

SA_MA4 AT34

SA_MA5 AU34

SA_MA6 BB32

SA_MA7 AT32

SA_MA8 AY32

SA_MA9 AV32

SA_MA10 BE37

SA_MA11 BA30

SA_MA12 BC30

SA_MA13 AW41

SA_MA14 AY28

SA_MA15 AU26

SA_DQ0AG6

SA_DQ1AJ6

SA_DQ2AP11

SA_DQ3AL6

SA_DQ4AJ10

SA_DQ5AJ8

SA_DQ6AL8

SA_DQ7AL7

SA_DQ8AR11

SA_DQ9AP6

SA_DQ10AU6

SA_DQ11AV9

SA_DQ12AR6

SA_DQ13AP8

SA_DQ14AT13

SA_DQ15AU13

SA_DQ16BC7

SA_DQ17BB7

SA_DQ18BA13

SA_DQ19BB11

SA_DQ20BA7

SA_DQ21BA9

SA_DQ22BB9

SA_DQ23AY13

SA_DQ24AV14

SA_DQ25AR14

SA_DQ26AY17

SA_DQ27AR19

SA_DQ28BA14

SA_DQ29AU14

SA_DQ30BB14

SA_DQ31BB17

SA_DQ32BA45

SA_DQ33AR43

SA_DQ34AW48

SA_DQ35BC48

SA_DQ36BC45

SA_DQ37AR45

SA_DQ38AT48

SA_DQ39AY48

SA_DQ40BA49

SA_DQ41AV49

SA_DQ42BB51

SA_DQ43AY53

SA_DQ44BB49

SA_DQ45AU49

SA_DQ46BA53

SA_DQ47BB55

SA_DQ48BA55

SA_DQ49AV56

SA_DQ50AP50

SA_DQ51AP53

SA_DQ52AV54

SA_DQ53AT54

SA_DQ54AP56

SA_DQ55AP52

SA_DQ56AN57

SA_DQ57AN53

SA_DQ58AG56

SA_DQ59AG53

SA_DQ60AN55

SA_DQ61AN52

SA_DQ62AG55

SA_DQ63AK56

SA_CAS#BE39

SA_RAS#BD39

SA_WE#AT41

SA_BS0BD37

SA_BS1BF36

SA_BS2BA28

SA_DQS#3 AT17

DDR SYSTEM MEMORY A

3 OF 9CPU1C

IVY-BRIDGE-GP-NF

71.00IVY.A0U

DDR SYSTEM MEMORY A

3 OF 9CPU1C

IVY-BRIDGE-GP-NF

71.00IVY.A0U

SB_CK0 BA34

SB_CK1 BA36

SB_CK#0 AY34

SB_CK#1 BB36

SB_CKE0 AR22

SB_CKE1 BF27

SB_ODT0 AT43

SB_ODT1 BG47

SB_DQS4 BE51

SB_DQS#4 BG51

SB_DQS5 BA61

SB_DQS#5 BA59

SB_DQS6 AR59

SB_DQS#6 AT60

SB_DQS7 AK61

SB_DQS#7 AK59

SB_DQS0 AM2

SB_DQS#0 AL3

SB_DQS1 AV1

SB_DQS#1 AV3

SB_DQS2 BE11

SB_DQS#2 BG11

SB_DQS3 BD18

SB_DQS#3 BD17

SB_MA0 BF32

SB_MA1 BE33

SB_MA2 BD33

SB_MA3 AU30

SB_MA4 BD30

SB_MA5 AV30

SB_MA6 BG30

SB_MA7 BD29

SB_MA8 BE30

SB_MA9 BE28

SB_MA10 BD43

SB_MA11 AT28

SB_MA12 AV28

SB_MA13 BD46

SB_MA14 AT26

SB_MA15 AU22

SB_DQ0AL4

SB_DQ1AL1

SB_DQ2AN3

SB_DQ3AR4

SB_DQ4AK4

SB_DQ5AK3

SB_DQ6AN4

SB_DQ7AR1

SB_DQ8AU4

SB_DQ9AT2

SB_DQ10AV4

SB_DQ11BA4

SB_DQ12AU3

SB_DQ13AR3

SB_DQ14AY2

SB_DQ15BA3

SB_DQ16BE9

SB_DQ17BD9

SB_DQ18BD13

SB_DQ19BF12

SB_DQ20BF8

SB_DQ21BD10

SB_DQ22BD14

SB_DQ23BE13

SB_DQ24BF16

SB_DQ25BE17

SB_DQ26BE18

SB_DQ27BE21

SB_DQ28BE14

SB_DQ29BG14

SB_DQ30BG18

SB_DQ31BF19

SB_DQ32BD50

SB_DQ33BF48

SB_DQ34BD53

SB_DQ35BF52

SB_DQ36BD49

SB_DQ37BE49

SB_DQ38BD54

SB_DQ39BE53

SB_DQ40BF56

SB_DQ41BE57

SB_DQ42BC59

SB_DQ43AY60

SB_DQ44BE54

SB_DQ45BG54

SB_DQ46BA58

SB_DQ47AW59

SB_DQ48AW58

SB_DQ49AU58

SB_DQ50AN61

SB_DQ51AN59

SB_DQ52AU59

SB_DQ53AU61

SB_DQ54AN58

SB_DQ55AR58

SB_DQ56AK58

SB_DQ57AL58

SB_DQ58AG58

SB_DQ59AG59

SB_DQ60AM60

SB_DQ61AL59

SB_DQ62AF61

SB_DQ63AH60

SB_CS#0 BE41

SB_CS#1 BE47

SB_CAS#AV43

SB_RAS#BF40

SB_WE#BD45

SB_BS0BG39

SB_BS1BD42

SB_BS2AT22

DDR SYSTEM MEMORY B

4 OF 9CPU1D

IVY-BRIDGE-GP-NF

71.00IVY.A0U

DDR SYSTEM MEMORY B

4 OF 9CPU1D

IVY-BRIDGE-GP-NF

71.00IVY.A0U

WWW.MANUALS.CLAN.SU

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

CFG2

CFG4CFG5CFG6

CFG5 CFG6

CFG0_TPCFG1_TP

CFG3_TP

CFG7

CFG7

CFG2

CFG4

Title


Date: Sheet of


Petra Uma -1

CPU (RESERVED)A3


<Core Design>

Title


Date: Sheet of


Petra Uma -1

CPU (RESERVED)A3


<Core Design>

Title


Date: Sheet of


Petra Uma -1

CPU (RESERVED)A3


<Core Design>

SSID = CPU

0:Lane Reversed

1: Normal Operation; Lane # definition matches socket pin map definition

PEG Static Lane Reversal

CFG2

0:Enable

1:Disable

Enabl EDP function

CFG4

10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

CFG[6:5] 11: x16 - Device 1 functions 1 and 2 disabled

PCIE Port Bifurcation Straps

1: PEG Train immediately following xxRESETB de assertionCFG7

PEG DEFER TRAINING

0: PEG Wait for BIOS for training

1TP702TPAD14-OP-GP TP702TPAD14-OP-GP

12

R7051KR2J-L2-GP

DY

R7051KR2J-L2-GP

DY



12

R7061KR2J-L2-GP

DY

R7061KR2J-L2-GP

DY

12

R7031KR2J-L2-GPEDP

R7031KR2J-L2-GPEDP

CFG0B50

CFG1C51

CFG2B54

CFG3D53

CFG4A51

CFG5C53

CFG6C55

CFG7H49

CFG8A55

CFG9H51

CFG10K49

CFG11K53

CFG12F53

CFG13G53

CFG14L51

CFG15F51

CFG16D52

CFG17L53

DC_TEST_A4 A4

DC_TEST_A58 A58

DC_TEST_A59 A59

DC_TEST_A61 A61

DC_TEST_BD1 BD1

DC_TEST_BD61 BD61

DC_TEST_BE1 BE1

DC_TEST_BE3 BE3

DC_TEST_BE59 BE59DC_TEST_BE61 BE61

DC_TEST_BG1 BG1

DC_TEST_BG3 BG3DC_TEST_BG4 BG4

DC_TEST_BG58 BG58DC_TEST_BG59 BG59DC_TEST_BG61 BG61

DC_TEST_C4 C4

DC_TEST_C59 C59

DC_TEST_C61 C61

DC_TEST_D1 D1DC_TEST_D3 D3

DC_TEST_D61 D61

VCC_VAL_SENSEH43

VSS_VAL_SENSEK43

VAXG_VAL_SENSEH45

VSSAXG_VAL_SENSEK45

VCC_DIE_SENSEF48

RSVD41 AH2

RSVD42 AG13

RSVD43 AM14

RSVD44 AM15

RSVD8BA19

RSVD9AV19

RSVD10AT21

RSVD11BB21

RSVD12BB19

RSVD13AY21

RSVD14BA22

RSVD15AY22

RSVD16AU19

RSVD17AU21

RSVD18BD21

RSVD19BD22

RSVD20BD25

RSVD21BD26

RSVD22BG22

RSVD23BE22

RSVD24BG26

RSVD25BE26

RSVD26BF23

RSVD27BE24

RSVD45 N50

RSVD30 N42

RSVD31 L42

RSVD32 L45

RSVD33 L47

RSVD34 M13

RSVD35 M14

RSVD36 U14

RSVD37 W14

RSVD38 P13

RSVD39 AT49

RSVD40 K24

RSVD6H48

RSVD7K48

RSVD47G48

BCLK_ITP N59

BCLK_ITP# N58

RESERVED

5 OF 9CPU1E

IVY-BRIDGE-GP-NF

71.00IVY.A0U

RESERVED

5 OF 9CPU1E

IVY-BRIDGE-GP-NF

71.00IVY.A0U

12

R7041KR2J-L2-GP

DY

R7041KR2J-L2-GP

DY

12

R7021KR2J-L2-GPDY

R7021KR2J-L2-GPDY

WWW.MANUALS.CLAN.SU

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

H_CPU_SVIDCLKH_CPU_SVIDALRT#

H_VCCP_SEL_L

+V1.05S_VCCPQE

H_CPU_SVIDDAT

VCC_CORE

VCC_CORE

1D05V_VTT_CPU

VCC_CORE

1D05V_VTT_CPU

1D05V_VTT_CPU

1D05V_VTT 1D05V_VTT_CPU

3D3V_S5

1D05V_VTT_CPU

1D05V_VTT_CPU

1D05V_VTT_CPU

H_CPU_SVIDDAT 42

VR_SVID_ALERT# 42H_CPU_SVIDCLK 42

VSSSENSE 42VCCSENSE 42

VSSIO_SENSE 45VCCIO_SENSE 45

Title


Date: Sheet of


Petra Uma -1

CPU (VCC_CORE)Custom


<Core Design>

Title


Date: Sheet of


Petra Uma -1



<Core Design>

Title


Date: Sheet of


Petra Uma -1



<Core Design>

SSID = CPU

ULV:17WIccmax:33AICC_TDC:25A

Iccmax:8.5AICC_TDC:8.5A

Place near processor

Place near processor

12

C8 02

SC

2D2U

6D3V

2KX

-GP

C8 02

SC

2D2U

6D3V

2KX

-GP

1 2R80610R1F-GP

DY

R80610R1F-GP

DY

12

C818

SC

2D2U

6D3V

2KX

-GP

DY

C818

SC

2D2U

6D3V

2KX

-GP

DY

12

C812

SC

1U6D

3V2K

X-L-1-G

PC

812S

C1U

6D3V

2KX

-L-1-GP

12

C8 01

SC

2D2U

6D3V

2KX

-GP

C8 01

SC

2D2U

6D3V

2KX

-GP

12

C8 16

SC

2D2U

6D3V

2KX

-GP

C8 16

SC

2D2U

6D3V

2KX

-GP

12

C811

SC

2D2U

6D3V

2KX

-GP

C811

SC

2D2U

6D3V

2KX

-GP

12

C8 35

SC

10U6D

3V5K

X-1G

P

DY

C8 35

SC

10U6D

3V5K

X-1G

P

DY

1 2R8080R2J-L-GP

R8080R2J-L-GP

12

C829

SC

10U6D

3V5K

X-1G

P

DY

C829

SC

10U6D

3V5K

X-1G

P

DY

12

C838

SC

10U6D

3V5K

X-1G

P

DY

C838

SC

10U6D

3V5K

X-1G

P

DY

12

C8 15

SC

2D2U

6D3V

2KX

-GP

C8 15

SC

2D2U

6D3V

2KX

-GP

12

C844

SC

10U6D

3V5K

X-1G

P

DY

C844

SC

10U6D

3V5K

X-1G

P

DY

12

C840

SC

10U6D

3V5K

X-1G

PC

840S

C10U

6D3V

5KX

-1GP

12

R804130R2F-1-GPR804130R2F-1-GP

12

C813

SC

1U6D

3V2K

X-L-1-G

PC

813S

C1U

6D3V

2KX

-L-1-GP

12

R802100R2F-L1-GP-UR802100R2F-L1-GP-U

12

C845

SC

10U6D

3V5K

X-1G

PC

845S

C10U

6D3V

5KX

-1GP

12

C806

SC

1U6D

3V2K

X-L-1-G

PC

806S

C1U

6D3V

2KX

-L-1-GP

12

C8 32

SC

10U6D

3V5K

X-1G

PC

8 32S

C10U

6D3V

5KX

-1GP

12

C8 25

SC

10U6D

3V5K

X-1G

PC

8 25S

C10U

6D3V

5KX

-1GP

12

C814

SC

1U6D

3V2K

X-L-1-G

PC

814S

C1U

6D3V

2KX

-L-1-GP

12

C808

SC

2D2U

6D3V

2KX

-GP

C808

SC

2D2U

6D3V

2KX

-GP

12

C831

SC

10U6D

3V5K

X-1G

PC

831S

C10U

6D3V

5KX

-1GP

1 2PG803

GAP-CLOSE-PWR

PG803

GAP-CLOSE-PWR

12

C823

SC

1U6D

3V2K

X-L-1-G

PC

823S

C1U

6D3V

2KX

-L-1-GP

12

C828

SC

10U6D

3V5K

X-1G

PC

828S

C10U

6D3V

5KX

-1GP

12

C821

SC

1U6D

3V2K

X-L-1-G

P

DY

C821

SC

1U6D

3V2K

X-L-1-G

P

DY

12

C805

SC

10U6D

3V5K

X-1G

P

DY

C805

SC

10U6D

3V5K

X-1G

P

DY

1 2PG806

GAP-CLOSE-PWR

PG806

GAP-CLOSE-PWR

1 2PG801

GAP-CLOSE-PWR

PG801

GAP-CLOSE-PWR

12

C819

SC

2D2U

6D3V

2KX

-GP

DY

C819

SC

2D2U

6D3V

2KX

-GP

DY

1 2PG804

GAP-CLOSE-PWR

PG804

GAP-CLOSE-PWR

12

C834

SC

10U6D

3V5K

X-1G

PC

834S

C10U

6D3V

5KX

-1GP

12

C804

SC

2D2U

6D3V

2KX

-GP

C804

SC

2D2U

6D3V

2KX

-GP

12

C817

SC

2D2U

6D3V

2KX

-GP

DY

C817

SC

2D2U

6D3V

2KX

-GP

DY

12

R80710R1F-GP

DY

R80710R1F-GP

DY

12

C822

SC

1U6D

3V2K

X-L-1-G

PDY

C822

SC

1U6D

3V2K

X-L-1-G

PDY

1 2R80343R2J-GPR80343R2J-GP

12

C810

SC

10U6D

3V5K

X-1G

PC

810S

C10U

6D3V

5KX

-1GP

12

R810100KR2J-4-GPR810100KR2J-4-GP

12

C827

SC

10U6D

3V5K

X-1G

P

DY

C827

SC

10U6D

3V5K

X-1G

P

DY

12

R801100R2F-L1-GP-UR801100R2F-L1-GP-U

VCC_SENSE F43

VSS_SENSE G43

VIDALERT# A44

VIDSCLK B43

VIDSOUT C44

VSS_SENSE_VCCIO AN17

VCC1A26

VCC2A29

VCC3A31

VCC4A34

VCC5A35

VCC6A38

VCC7A39

VCC8A42

VCC9C26

VCC10C27

VCC11C32

VCC12C34

VCC13C37

VCC14C39

VCC15C42

VCC16D27

VCC17D32

VCC18D34

VCC19D37

VCC20D39

VCC21D42

VCC22E26

VCC23E28

VCC24E32

VCC25E34

VCC26E37

VCC27E38

VCC28F25

VCC29F26

VCC30F28

VCC31F32

VCC32F34

VCC33F37

VCC34F38

VCC35F42

VCC36G42

VCC37H25

VCC38H26

VCC39H28

VCC40H29

VCC41H32

VCC42H34

VCC43H35

VCC44H37

VCC45H38

VCC46H40

VCC47J25

VCC48J26

VCC49J28

VCC50J29

VCC51J32

VCC52J34

VCC53J35

VCC54J37

VCC55J38

VCC56J40

VCC57J42

VCC58K26

VCC59K27

VCC60K29

VCC61K32

VCC62K34

VCC63K35

VCC64K37

VCC66K39

VCC67K42

VCC68L25

VCC69L28

VCC70L33

VCC71L36

VCC72L40

VCC73N26

VCC74N30

VCC75N34

VCC76N38

VCCIO1 AF46

VCCIO3 AG48

VCCIO4 AG50

VCCIO5 AG51

VCCIO6 AJ17

VCCIO7 AJ21

VCCIO8 AJ25

VCCIO9 AJ43

VCCIO10 AJ47

VCCIO11 AK50

VCCIO12 AK51

VCCIO13 AL14

VCCIO14 AL15

VCCIO15 AL16

VCCIO16 AL20

VCCIO17 AL22

VCCIO18 AL26

VCCIO19 AL45

VCCIO20 AL48

VCCIO21 AM16

VCCIO22 AM17

VCCIO23 AM21

VCCIO24 AM43

VCCIO25 AM47

VCCIO26 AN20

VCCIO27 AN42

VCCIO28 AN45

VCCIO29 AN48

VCCIO30 AA14

VCCIO31 AA15

VCCIO32 AB17

VCCIO33 AB20

VCCIO34 AC13

VCCIO35 AD16

VCCIO36 AD18

VCCIO37 AD21

VCCIO38 AE14

VCCIO39 AE15

VCCIO40 AF16

VCCIO41 AF18

VCCIO42 AF20

VCCIO43 AG15

VCCIO44 AG16

VCCIO45 AG17

VCCIO46 AG20

VCCIO47 AG21

VCCIO48 AJ14

VCCIO49 AJ15

VCCIO50 W16

VCCIO51 W17

VCCPQE1 AM25

VCCPQE2 AN22

VCCIO_SENSE AN16

VCCIO_SEL BC22

POWER

CORE SUPPLY

PEG IO AND DDR IO

SENSE LINES

SVID

QUIET

RAILS

6 OF 9CPU1F

IVY-BRIDGE-GP-NF

71.00IVY.A0U

POWER

CORE SUPPLY

PEG IO AND DDR IO

SENSE LINES

SVID

QUIET

RAILS

6 OF 9CPU1F

IVY-BRIDGE-GP-NF

71.00IVY.A0U

12

C830

SC

10U6D

3V5K

X-1G

PC

830S

C10U

6D3V

5KX

-1GP

12

C839

SC

10U6D

3V5K

X-1G

P

DY

C839

SC

10U6D

3V5K

X-1G

P

DY

12

C836

SC

10U6D

3V5K

X-1G

PC

836S

C10U

6D3V

5KX

-1GP

12

C843

SC

10U6D

3V5K

X-1G

PC

843S

C10U

6D3V

5KX

-1GP

12

C803

SC

2D2U

6D3V

2KX

-GP

DY

C803

SC

2D2U

6D3V

2KX

-GP

DY

12

R80575R3J-L-GPR80575R3J-L-GP

12

C807

SC

1U6D

3V2K

X-L-1-G

PC

807S

C1U

6D3V

2KX

-L-1-GP

1 2PG802

GAP-CLOSE-PWR

PG802

GAP-CLOSE-PWR

12

C824

SC

1U6D

3V2K

X-L-1-G

PC

824S

C1U

6D3V

2KX

-L-1-GP

12

C833

SC

10U6D

3V5K

X-1G

PC

833S

C10U

6D3V

5KX

-1GP

12

C8 26

SC

10U6D

3V5K

X-1G

PC

8 26S

C10U

6D3V

5KX

-1GP

12

C820

SC

2D2U

6D3V

2KX

-GP

DY

C820

SC

2D2U

6D3V

2KX

-GP

DY

12

C853SC1U6D3V2KX-L-1-GPC853SC1U6D3V2KX-L-1-GP

1 2PG805

GAP-CLOSE-PWR

PG805

GAP-CLOSE-PWR

12

C809

SC

1U6D

3V2K

X-L-1-G

PC

809S

C1U

6D3V

2KX

-L-1-GP

WWW.MANUALS.CLAN.SU

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

VSS_AXG_SENSEVCC_AXG_SENSE

VCCSA_VID0VCCSA_VID1

M_VREF_DQ_DIMM1_CM_VREF_DQ_DIMM0_C

VCCSA_VID1VCCSA_VID0

TP_VDDQ_SENSETP_VDDQ_VSS

+1.5S_VCCD_Q

VCCSA_SENSE

+1.5S_VCCD_Q

VCC_GFXCORE

1D8V_S0

VCC_GFXCORE

0D85V_S0

1D05V_VTT_CPU1D05V_VTT_CPU

1D5V_S0

0D85V_S0

1D5V_S0

VCC_AXG_SENSE42VSS_AXG_SENSE42

+V_SM_VREF_CNT 37

M_VREF_DQ_DIMM0_C 37M_VREF_DQ_DIMM1_C 37

VCCSA_VID0 48VCCSA_VID1 48

Title


Date: Sheet of


Petra Uma -1

CPU (VCC_GFXCORE)Custom


<Core Design>

Title


Date: Sheet of


Petra Uma -1



<Core Design>

Title


Date: Sheet of


Petra Uma -1



<Core Design>

SSID = CPU

R906,R907 close to CPU

Routing Guideline:Power from DDR_VREF_S3 and +V_SM_VREF_CNTshould have 10 mils trace width.

R902 need be close to pin U10.

PROCESSOR DDR 1.5V QUIET RAIL (BGA only)

+V1.5S_VCCD_Q should be short to +V1.5S_VCCDDQ on board

Iccmax:18A(GT1)ICC_TDC:12A(GT1)

ICC_MAX:6A

ICC_MAX:1.2A

Iccmax:5A

BE7 and BG7 is NC ball in HR

12

C910

SC

10U6D

3V5K

X-1G

PC

910S

C10U

6D3V

5KX

-1GP

12

C903

SC

10U6D

3V5K

X-1G

PC

903S

C10U

6D3V

5KX

-1GP

12

R91410KR2J-L-GPR91410KR2J-L-GP

1 2R9090R2J-L-GP

R9090R2J-L-GP

12

C902

SC

10U6D

3V5K

X-1G

PC

9 02S

C10U

6D3V

5KX

-1GP

12

C911

SC

10U6D

3V5K

X-1G

PC

911S

C10U

6D3V

5KX

-1GP

12

C904

SC

10U6D

3V5K

X-1G

P

DY

C904

SC

10U6D

3V5K

X-1G

P

DY

12

C926

SC

1U6D

3V2K

X-L-1-G

P

DY

C926

SC

1U6D

3V2K

X-L-1-G

P

DY

12

C916

SC

1U6D

3V2K

X-L-1-G

PC

916S

C1U

6D3V

2KX

-L-1-GP

12

C918

SC

1U6D

3V2K

X-L-1-G

PC

918S

C1U

6D3V

2KX

-L-1-GP

12

C919

SC

10U6D

3V5K

X-1G

PC

919S

C10U

6D3V

5KX

-1GP

1 2


12

C915SC10U6D3V5KX-1GP

C915SC10U6D3V5KX-1GP

12

C922SC1U10V2KX-1GPC922SC1U10V2KX-1GP

12

C921

SC

10U6D

3V5K

X-1G

P

DY

C921

SC

10U6D

3V5K

X-1G

P

DY1

2

R907100R2F-L1-GP-U

R907100R2F-L1-GP-U

12

R906100R2F-L1-GP-U

R906100R2F-L1-GP-U

12

C925

SC

1U6D

3V2K

X-L-1-G

PC

925S

C1U

6D3V

2KX

-L-1-GP

12

R91210KR2J-L-GP

DY

R91210KR2J-L-GP

DY

123 4

RN902SRN1KJ-7-GPDY

RN902SRN1KJ-7-GPDY

12

R91310KR2J-L-GP

R91310KR2J-L-GP

12

C909

SC

1U6D

3V2K

X-L-1-G

PC

909S

C1U

6D3V

2KX

-L-1-GP

1 TP901 TPAD14-OP-GPTP901 TPAD14-OP-GP

12

C912

SC

10U6D

3V5K

X-1G

P

DY

C912

SC

10U6D

3V5K

X-1G

P

DY


12

C913

SC

10U6D

3V5K

X-1G

PC

913S

C10U

6D3V

5KX

-1GP

12

C917

SC

1U6D

3V2K

X-L-1-G

PC

917S

C1U

6D3V

2KX

-L-1-GP

12

C9 07

SC

1U6D

3V2K

X-L-1-G

PC

9 07S

C1U

6D3V

2KX

-L-1-GP

12

C924

SC

1U6D

3V2K

X-L-1-G

P

DY

C924

SC

1U6D

3V2K

X-L-1-G

P

DY

12

C914

SC

1U6D

3V2K

X-L-1-G

PC

914S

C1U

6D3V

2KX

-L-1-GP

12

C905

SC

10U6D

3V5K

X-1G

PC

905S

C10U

6D3V

5KX

-1GP

12

C908

SC

10U6D

3V5K

X-1G

PC

908S

C10U

6D3V

5KX

-1GP

12

C920

SC

10U6D

3V5K

X-1G

PC

920S

C10U

6D3V

5KX

-1GP

12

R902100R2F-L1-GP-UR902100R2F-L1-GP-U

SM_VREF AY43

VAXG1AA46

VAXG2AB47

VAXG3AB50

VAXG4AB51

VAXG5AB52

VAXG6AB53

VAXG7AB55

VAXG8AB56

VAXG9AB58

VAXG10AB59

VAXG11AC61

VAXG12AD47

VAXG13AD48

VAXG14AD50

VAXG15AD51

VAXG16AD52

VAXG17AD53

VAXG18AD55

VAXG19AD56

VAXG20AD58

VAXG21AD59

VAXG22AE46

VAXG23N45

VAXG24P47

VAXG25P48

VAXG26P50

VAXG27P51

VAXG28P52

VAXG29P53

VAXG30P55

VAXG31P56

VAXG32P61

VAXG33T48

VAXG34T58

VAXG35T59

VAXG36T61

VAXG37U46

VAXG38V47

VAXG39V48

VAXG40V50

VAXG41V51

VAXG42V52

VAXG43V53

VAXG44V55

VAXG45V56

VAXG46V58

VAXG47V59

VAXG48W50

VAXG49W51

VAXG50W52

VAXG51W53

VAXG52W55

VAXG53W56

VAXG54W61

VDDQ11 AM40

VDDQ12 AN30

VDDQ13 AN34

VDDQ14 AN38

VDDQ15 AR26

VDDQ1 AJ28

VDDQ2 AJ33

VDDQ3 AJ36

VDDQ4 AJ40

VDDQ5 AL30

VDDQ6 AL34

VDDQ7 AL38

VDDQ8 AL42

VDDQ9 AM33

VDDQ10 AM36

VCCPLL1BB3

VCCPLL2BC1

VCCSA_SENSE U10

VCCSA_VID1 D49

VAXG55Y48

VAXG56Y61

VCCPLL3BC4

VAXG_SENSEF45

VSSAXG_SENSEG45

VCCSA1L17

VCCSA10R21

VCCSA12V16

VCCSA13V17

VCCSA14V18

VCCSA4N20

VCCSA5N22

VCCSA6P17

VCCSA9R18

VDDQ16 AR28

VDDQ17 AR30

VDDQ18 AR32

VDDQ19 AR34

VDDQ20 AR36

VDDQ21 AR40

VDDQ22 AV41

VDDQ23 AW26

VDDQ24 BA40

VDDQ25 BB28

VDDQ26 BG33

VCCSA11U15

VCCSA15V21

VCCSA16W20

VCCSA2L21

VCCSA3N16

VCCDQ1 AM28

VCCDQ2 AN26

VCCSA7P20

VCCSA8R16

VDDQ_SENSE BC43

VSS_SENSE_VDDQ BA43

VCCSA_VID0 D48

SA_DIMM_VREFDQ BE7

SB_DIMM_VREFDQ BG7

POWER

GRAPHICS

DDR3 - 1.5V RAILS

1.8V RAIL

SENSE

LINES

SA RAIL

SENSE LINES

QUIET RAILS

VREF

VCCSA VID

lines

7 OF 9CPU1G

IVY-BRIDGE-GP-NF

71.00IVY.A0U

POWER

GRAPHICS

DDR3 - 1.5V RAILS

1.8V RAIL

SENSE

LINES

SA RAIL

SENSE LINES

QUIET RAILS

VREF

VCCSA VID

lines

7 OF 9CPU1G

IVY-BRIDGE-GP-NF

71.00IVY.A0U

12

R90810KR2J-L-GP

DY

R90810KR2J-L-GP

DY

WWW.MANUALS.CLAN.SU

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of


Petra Uma -1

CPU (VSS)A3


<Core Design>

Title


Date: Sheet of


Petra Uma -1

CPU (VSS)A3


<Core Design>

Title


Date: Sheet of


Petra Uma -1

CPU (VSS)A3


<Core Design>

SSID = CPU

VSS1A13

VSS2A17

VSS3A21

VSS4A25

VSS5A28

VSS6A33

VSS7A37

VSS8A40

VSS9A45

VSS10A49

VSS11A53

VSS12A9

VSS13AA1

VSS14AA13

VSS15AA50

VSS16AA51

VSS17AA52

VSS18AA53

VSS19AA55

VSS20AA56

VSS21AA8

VSS22AB16

VSS23AB18

VSS24AB21

VSS25AB48

VSS26AB61

VSS27AC10

VSS28AC14

VSS29AC46

VSS30AC6

VSS31AD17

VSS32AD20

VSS33AD4

VSS34AD61

VSS35AE13

VSS36AE8

VSS37AF1

VSS38AF17

VSS39AF21

VSS40AF47

VSS41AF48

VSS42AF50

VSS43AF51

VSS44AF52

VSS45AF53

VSS46AF55

VSS47AF56

VSS48AF58

VSS49AF59

VSS50AG10

VSS51AG14

VSS52AG18

VSS53AG47

VSS54AG52

VSS55AG61

VSS56AG7

VSS57AH4

VSS58AH58

VSS59AJ13

VSS60AJ16

VSS61AJ20

VSS62AJ22

VSS63AJ26

VSS64AJ30

VSS65AJ34

VSS66AJ38

VSS67AJ42

VSS68AJ45

VSS69AJ48

VSS70AJ7

VSS71AK1

VSS72AK52

VSS73AL10

VSS74AL13

VSS75AL17

VSS76AL21

VSS77AL25

VSS78AL28

VSS79AL33

VSS80AL36

VSS81AL40

VSS82AL43

VSS83AL47

VSS84AL61

VSS85AM13

VSS86AM20

VSS87AM22

VSS88AM26

VSS89AM30

VSS90AM34

VSS91 AM38

VSS92 AM4

VSS93 AM42

VSS94 AM45

VSS95 AM48

VSS96 AM58

VSS97 AN1

VSS98 AN21

VSS99 AN25

VSS100 AN28

VSS101 AN33

VSS102 AN36

VSS103 AN40

VSS104 AN43

VSS105 AN47

VSS106 AN50

VSS107 AN54

VSS108 AP10

VSS109 AP51

VSS110 AP55

VSS111 AP7

VSS112 AR13

VSS113 AR17

VSS114 AR21

VSS115 AR41

VSS116 AR48

VSS117 AR61

VSS118 AR7

VSS119 AT14

VSS120 AT19

VSS121 AT36

VSS122 AT4

VSS123 AT45

VSS124 AT52

VSS125 AT58

VSS126 AU1

VSS127 AU11

VSS128 AU28

VSS129 AU32

VSS130 AU51

VSS131 AU7

VSS132 AV17

VSS133 AV21

VSS134 AV22

VSS135 AV34

VSS136 AV40

VSS137 AV48

VSS138 AV55

VSS139 AW13

VSS140 AW43

VSS141 AW61

VSS142 AW7

VSS143 AY14

VSS144 AY19

VSS145 AY30

VSS146 AY36

VSS147 AY4

VSS148 AY41

VSS149 AY45

VSS150 AY49

VSS151 AY55

VSS152 AY58

VSS153 AY9

VSS154 BA1

VSS155 BA11

VSS156 BA17

VSS157 BA21

VSS158 BA26

VSS159 BA32

VSS160 BA48

VSS161 BA51

VSS162 BB53

VSS163 BC13

VSS164 BC5

VSS165 BC57

VSS166 BD12

VSS167 BD16

VSS168 BD19

VSS169 BD23

VSS170 BD27

VSS171 BD32

VSS172 BD36

VSS173 BD40

VSS174 BD44

VSS175 BD48

VSS176 BD52

VSS177 BD56

VSS178 BD8

VSS179 BE5

VSS180 BG13

VSS

8 OF 9CPU1H

IVY-BRIDGE-GP-NF

71.00IVY.A0U

VSS

8 OF 9CPU1H

IVY-BRIDGE-GP-NF

71.00IVY.A0U

VSS181BG17

VSS182BG21

VSS183BG24

VSS184BG28

VSS185BG37

VSS186BG41

VSS187BG45

VSS188BG49

VSS189BG53

VSS190BG9

VSS191C29

VSS192C35

VSS193C40

VSS194D10

VSS195D14

VSS196D18

VSS197D22

VSS198D26

VSS199D29

VSS200D35

VSS201D4

VSS202D40

VSS203D43

VSS204D46

VSS205D50

VSS206D54

VSS207D58

VSS208D6

VSS209E25

VSS210E29

VSS211E3

VSS212E35

VSS213E40

VSS214F13

VSS215F15

VSS216F19

VSS217F29

VSS218F35

VSS219F40

VSS220F55

VSS221G51

VSS222G6

VSS223G61

VSS224H10

VSS225H14

VSS226H17

VSS227H21

VSS228H4

VSS229H53

VSS230H58

VSS231J1

VSS232J49

VSS233J55

VSS234K11

VSS235K21

VSS236K51

VSS237K8

VSS238L16

VSS239L20

VSS240L22

VSS241L26

VSS242L30

VSS243L34

VSS244L38

VSS245L43

VSS246L48

VSS268 P14

VSS269 P16

VSS270 P18

VSS271 P21

VSS272 P58

VSS273 P59

VSS274 P9

VSS275 R17

VSS276 R20

VSS277 R4

VSS278 R46

VSS279 T1

VSS280 T47

VSS281 T50

VSS282 T51

VSS283 T52

VSS284 T53

VSS285 T55

VSS286 T56

VSS287 U13

VSS288 U8

VSS289 V20

VSS290 V61

VSS_NCTF_1#A5 A5

VSS_NCTF_2#A57 A57

VSS_NCTF_3#BC61 BC61

VSS_NCTF_8#BG5 BG5

VSS_NCTF_9#BG57 BG57

VSS_NCTF_10#C3 C3

VSS_NCTF_13#E1 E1

VSS_NCTF_14#E61 E61

VSS250 M4

VSS251 M58

VSS252 M6

VSS253 N1

VSS254 N17

VSS255 N21

VSS256 N25

VSS257 N28

VSS258 N33

VSS259 N36

VSS260 N40

VSS261 N43

VSS262 N47

VSS263 N48

VSS264 N51

VSS265 N52

VSS266 N56

VSS267 N61

VSS247L61

VSS248M11

VSS291 W13

VSS292 W15

VSS293 W18

VSS294 W21

VSS295 W46

VSS296 W8

VSS297 Y4

VSS298 Y47

VSS299 Y58

VSS300 Y59

VSS249M15

VSS_NCTF_4 BD3

VSS_NCTF_5 BD59

VSS_NCTF_6 BE4

VSS_NCTF_7 BE58

VSS_NCTF_11 C58

VSS_NCTF_12 D59

VSS

9 OF 9

NCTF

NCTF TEST PIN：

A5,A57,BC61,BG5

BG57,C3,E1,E61

CPU1I

IVY-BRIDGE-GP-NF

71.00IVY.A0U

VSS

9 OF 9

NCTF

NCTF TEST PIN：

A5,A57,BC61,BG5

BG57,C3,E1,E61

CPU1I

IVY-BRIDGE-GP-NF

71.00IVY.A0U

WWW.MANUALS.CLAN.SU

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of


Petra Uma -1

XDPA4


<Core Design>

Title


Date: Sheet of


Petra Uma -1

XDPA4


<Core Design>

Title


Date: Sheet of


Petra Uma -1

XDPA4


<Core Design>

(Blanking)

WWW.MANUALS.CLAN.SU

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of


Petra Uma -1

ReservedA4


<Core Design>

Title


Date: Sheet of


Petra Uma -1

ReservedA4


<Core Design>

Title


Date: Sheet of


Petra Uma -1

ReservedA4


<Core Design>

(Blanking)

WWW.MANUALS.CLAN.SU

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of


Petra Uma -1

ReservedA4


<Core Design>

Title


Date: Sheet of


Petra Uma -1

ReservedA4


<Core Design>

Title


Date: Sheet of


Petra Uma -1

ReservedA4


<Core Design>

(Blanking)

WWW.MANUALS.CLAN.SU

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

M_A_A1

M_A_DQS#0



M_A_DQS3

M_A_DQ0

M_A_DQS#5

M_A_A2



M_A_DQS4

M_A_A3

M_A_DQS#6



M_A_DQ1

M_A_A4

M_A_DQS5

M_A_DQS#7



M_A_DQS#1

M_A_A5

M_A_DQ2

M_A_DQS6


M_A_DQS0


M_A_A7M_A_A8M_A_A9M_A_A10M_A_A11

M_A_A6

M_A_DQ3

M_A_DQS#2

M_A_DQS7



M_A_DQS1

M_A_A13M_A_A14M_A_A15

M_A_A12


M_A_DQS#3

M_A_A0



M_A_DQS2

M_A_DQS#4

TS#_DIMM0_1

1D5V_S3

3D3V_S0

0D75V_S0

3D3V_S0

1D5V_S3

DDR_VREF_S3

0D75V_S0

DDR_VREF_S3 M_VREF_DQ_DIMM0

M_VREF_DQ_DIMM0

DDR3_DRAMRST#15,37

M_A_DIM0_ODT06M_A_DIM0_ODT16

M_A_BS26

M_A_BS06M_A_BS16

M_A_DQ[63:0]6

TS#_DIMM0_1 15

PCH_SMBCLK 15,20,69PCH_SMBDATA 15,20,69

M_A_WE# 6

M_A_DIM0_CS#0 6

M_A_CAS# 6

M_A_DIM0_CKE0 6M_A_DIM0_CKE1 6

M_A_DIM0_CS#1 6



M_A_RAS# 6M_A_A[15:0] 6

M_A_DQS#[7:0] 6

M_A_DQS[7:0] 6

DDR_WR_VREF01_B4 37

Title


Date: Sheet of


Petra Uma -1

DDR3-SODIMM1Custom

14 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1

DDR3-SODIMM1Custom

14 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1

DDR3-SODIMM1Custom

14 103Tuesday, July 10, 2012

<Core Design>

SSID = MEMORY

Thermal EVENT

Tracew should be at least 20 mils wide

12

C1404

SC

10U6D

3V5K

X-1G

PC

1404S

C10U

6D3V

5KX

-1GP

12

C1407

SC

10U6D

3V5K

X-1G

PC

1407S

C10U

6D3V

5KX

-1GP

1 2R1403

10KR2J-L-GP

R1403

10KR2J-L-GP

12

C1421

SC

1U6D

3V2K

X-L-1-G

PC

1421S

C1U

6D3V

2KX

-L-1-GP

12 R14050R3J-4-GP

IVB

R14050R3J-4-GP

IVB

12

C1417

SC

D1U

10V2K

X-L1-G

PC

1417S

CD

1U10V

2KX

-L1-GP

12

C1411SCD1U10V2KX-L1-GPC1411SCD1U10V2KX-L1-GP

12

C1405

SC

10U10V

5ZY

-1GP

DY

C1405

SC

10U10V

5ZY

-1GP

DY

12

C1406

SC

10U6D

3V5K

X-1G

PC

1406S

C10U

6D3V

5KX

-1GP

12

C1419

SC

1U6D

3V2K

X-L-1-G

PC

1419S

C1U

6D3V

2KX

-L-1-GP

12 R14040R3J-4-GP

SNB

R14040R3J-4-GP

SNB

A098

A197

A296

A395

A492

A591

A690

A786

A889

A985

A10/AP107

A1184

A1283

A13119

A1480

A1578

A16/BA279

BA0109

BA1108

DQ05

DQ17

DQ215

DQ317

DQ44

DQ56

DQ616

DQ718

DQ821

DQ923

DQ1033

DQ1135

DQ1222

DQ1324

DQ1434

DQ1536

DQ1639

DQ1741

DQ1851

DQ1953

DQ2040

DQ2142

DQ2250

DQ2352

DQ2457

DQ2559

DQ2667

DQ2769

DQ2856

DQ2958

DQ3068

DQ3170

DQ32129

DQ33131

DQ34141

DQ35143

DQ36130

DQ37132

DQ38140

DQ39142

DQ40147

DQ41149

DQ42157

DQ43159

DQ44146

DQ45148

DQ46158

DQ47160

DQ48163

DQ49165

DQ50175

DQ51177

DQ52164

DQ53166

DQ54174

DQ55176

DQ56181

DQ57183

DQ58191

DQ59193

DQ60180

DQ61182

DQ62192

DQ63194

DQS0#10

DQS1#27

DQS2#45

DQS3#62

DQS4#135

DQS5#152

DQS6#169

DQS7#186

DQS012

DQS129

DQS247

DQS364

DQS4137

DQS5154

DQS6171

DQS7188

ODT0116

ODT1120

VREF_DQ1

VSS 2

NP1 NP1

NP2 NP2

RAS# 110

WE# 113

CAS# 115

CS0# 114

CS1# 121

CKE0 73

CKE1 74

CK0 101

CK0# 103

CK1 102

CK1# 104

DM0 11

DM1 28

DM2 46

DM3 63

DM4 136

DM5 153

DM6 170

DM7 187

SDA 200

SCL 202

VDDSPD 199

SA0 197

SA1 201

VREF_CA126

VDD18 124

NC#1 77

NC#2 122

NC#/TEST 125

VDD3 81

VDD4 82

VDD5 87

VDD6 88

VDD7 93

VDD8 94

VDD9 99

VDD10 100

VDD13 111

VDD14 112

VDD15 117

VDD16 118

VSS 3

VSS 8

VSS 9

VSS 13

VSS 14

VSS 19

VSS 20

VSS 25

VSS 26

VSS 31

VSS 32

VSS 37

VSS 38

VSS 43

VSS 44

VSS 48

VSS 49

VSS 54

VSS 55

VSS 60

VSS 61

VDD1 75

VSS 65

VSS 66

VSS 71

VSS 72

VDD2 76

VDD11 105

VDD12 106

VDD17 123

VSS 127

VSS 128

VSS 134VSS 133

VSS 138

VSS 139

VSS 144

VSS 145

VSS 151VSS 150

VSS 155

VSS 156

VSS 161

VSS 162

VSS 167

VSS 168

VSS 173VSS 172

VSS 179VSS 178

VSS 185VSS 184

VSS 189

VSS 190

VSS 195

VSS 196

RESET#30

EVENT# 198

VSS 205

VSS 206VTT1203

VTT2204

DM1DDR3-204P-122-GP62.10017.Z512nd = 62.10017.M513rd = 62.10024.G21


12

C1416

SC

D1U

10V2K

X-L1-G

PC

1416S

CD

1U10V

2KX

-L1-GP

12

C1403

SC

10U6D

3V5K

X-1G

PC

1403S

C10U

6D3V

5KX

-1GP

12


12


WWW.MANUALS.CLAN.SU

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

M_B_A1

M_B_DQ42M_B_DQ41M_B_DQ40

M_B_DQS#0

M_B_DQ43


M_B_DQ15

M_B_DQS3

M_B_DQ0

M_B_A2

M_B_DQS#5


M_B_DQ47


M_B_DQS4

M_B_A3

M_B_DQS#6



SA1_DIM1

M_B_DQ1

M_B_A4

M_B_DQS5

M_B_DQS#7

M_B_DQ53M_B_DQ52

M_B_DQ24

M_B_DQ55M_B_DQ54


M_B_DQS#1

M_B_DQ2

M_B_A5

M_B_DQS6

M_B_DQ57M_B_DQ56

M_B_DQS0

M_B_DQ59M_B_DQ58


M_B_A7M_B_A6

M_B_A11M_B_A10M_B_A9M_B_A8

M_B_DQ3

M_B_DQS#2

M_B_DQS7


M_B_DQ33M_B_DQ32

M_B_DQ35M_B_DQ34

M_B_DQS1

M_B_A12

M_B_A15M_B_A14M_B_A13

M_B_DQ5M_B_DQ4

M_B_DQ7M_B_DQ6

M_B_DQS#3

M_B_A0


M_B_DQ8


M_B_DQS2

M_B_DQS#4

1D5V_S3

3D3V_S0

0D75V_S0

1D5V_S3

DDR_VREF_S3

0D75V_S0

M_VREF_DQ_DIMM1DDR_VREF_S3

M_VREF_DQ_DIMM1

DDR3_DRAMRST#14,37

M_B_BS06

M_B_BS26

M_B_BS16M_B_DQ[63:0]6

TS#_DIMM0_1 14

PCH_SMBCLK 14,20,69PCH_SMBDATA 14,20,69

M_B_A[15:0] 6

M_B_DQS[7:0] 6

M_B_DQS#[7:0] 6

M_B_DIM0_ODT06M_B_DIM0_ODT16

M_B_WE# 6

M_B_DIM0_CS#0 6

M_B_CAS# 6

M_B_DIM0_CKE0 6M_B_DIM0_CKE1 6

M_B_DIM0_CS#1 6



M_B_RAS# 6

DDR_WR_VREF01_D1 37

Title


Date: Sheet of


Petra Uma -1

DDR3-SODIMM2Custom

15 102Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1

DDR3-SODIMM2Custom

15 102Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1

DDR3-SODIMM2Custom

15 102Tuesday, July 10, 2012

<Core Design>

SSID = MEMORY

SA_20111229A

12

C1513

SC

D1U

10V2K

X-L1-G

PC

1513S

CD

1U10V

2KX

-L1-GP

12


12

C1503

SC

5D6P

50V2C

N-1G

P

DY

C1503

SC

5D6P

50V2C

N-1G

P

DY

12 R150110KR2J-L-GPR150110KR2J-L-GP

12

C1507

SC

10U6D

3V5K

X-1G

PC

1507S

C10U

6D3V

5KX

-1GP

12

C1504

SC

56P50V

2JN-2G

P

DY

C1504

SC

56P50V

2JN-2G

P

DY

12R1503

0R3J-4-GPIVB

R1503

0R3J-4-GPIVB

A098

A197

A296

A395

A492

A591

A690

A786

A889

A985

A10/AP107

A1184

A1283

A13119

A1480

A1578

A16/BA279

BA0109

BA1108

DQ05

DQ17

DQ215

DQ317

DQ44

DQ56

DQ616

DQ718

DQ821

DQ923

DQ1033

DQ1135

DQ1222

DQ1324

DQ1434

DQ1536

DQ1639

DQ1741

DQ1851

DQ1953

DQ2040

DQ2142

DQ2250

DQ2352

DQ2457

DQ2559

DQ2667

DQ2769

DQ2856

DQ2958

DQ3068

DQ3170

DQ32129

DQ33131

DQ34141

DQ35143

DQ36130

DQ37132

DQ38140

DQ39142

DQ40147

DQ41149

DQ42157

DQ43159

DQ44146

DQ45148

DQ46158

DQ47160

DQ48163

DQ49165

DQ50175

DQ51177

DQ52164

DQ53166

DQ54174

DQ55176

DQ56181

DQ57183

DQ58191

DQ59193

DQ60180

DQ61182

DQ62192

DQ63194

DQS0#10

DQS1#27

DQS2#45

DQS3#62

DQS4#135

DQS5#152

DQS6#169

DQS7#186

DQS012

DQS129

DQS247

DQS364

DQS4137

DQS5154

DQS6171

DQS7188

ODT0116

ODT1120

VREF_DQ1

VSS 2

NP1 NP1

NP2 NP2

RAS# 110

WE# 113

CAS# 115

CS0# 114

CS1# 121

CKE0 73

CKE1 74

CK0 101

CK0# 103

CK1 102

CK1# 104

DM0 11

DM1 28

DM2 46

DM3 63

DM4 136

DM5 153

DM6 170

DM7 187

SDA 200

SCL 202

VDDSPD 199

SA0 197

SA1 201

VREF_CA126

VDD18 124

NC#1 77

NC#2 122

NC#/TEST 125

VDD3 81

VDD4 82

VDD5 87

VDD6 88

VDD7 93

VDD8 94

VDD9 99

VDD10 100

VDD13 111

VDD14 112

VDD15 117

VDD16 118

VSS 3

VSS 8

VSS 9

VSS 13

VSS 14

VSS 19

VSS 20

VSS 25

VSS 26

VSS 31

VSS 32

VSS 37

VSS 38

VSS 43

VSS 44

VSS 48

VSS 49

VSS 54

VSS 55

VSS 60

VSS 61

VDD1 75

VSS 65

VSS 66

VSS 71

VSS 72

VDD2 76

VDD11 105

VDD12 106

VDD17 123

VSS 127

VSS 128

VSS 134VSS 133

VSS 138

VSS 139

VSS 144

VSS 145

VSS 151VSS 150

VSS 155

VSS 156

VSS 161

VSS 162

VSS 167

VSS 168

VSS 173VSS 172

VSS 179VSS 178

VSS 185VSS 184

VSS 189

VSS 190

VSS 195

VSS 196

RESET#30

EVENT# 198

VSS 205

VSS 206VTT1203

VTT2204



12

C1519

SC

1U6D

3V2K

X-L-1-G

PC

1519S

C1U

6D3V

2KX

-L-1-GP

12

C1514

SC

D1U

10V2K

X-L1-G

PC

1514S

CD

1U10V

2KX

-L1-GP

12

C1506

SC

10U6D

3V5K

X-1G

PC

1506S

C10U

6D3V

5KX

-1GP

12


12

C1509

SC

10U6D

3V5K

X-1G

PC

1509S

C10U

6D3V

5KX

-1GP

12

C1505

SC

10U6D

3V5K

X-1G

PC

1505S

C10U

6D3V

5KX

-1GP

12 R15020R3J-4-GPSNB

R15020R3J-4-GPSNB

12

C1521

SC

1U6D

3V2K

X-L-1-G

PC

1521S

C1U

6D3V

2KX

-L-1-GP

12


WWW.MANUALS.CLAN.SU

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of


Petra Uma -1

DDR3-SODIMM2A4


<Core Design>

Title


Date: Sheet of


Petra Uma -1

DDR3-SODIMM2A4


<Core Design>

Title


Date: Sheet of


Petra Uma -1

DDR3-SODIMM2A4


<Core Design>

(Blanking)

WWW.MANUALS.CLAN.SU

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

LVDS_IBG

DAC_IREF_R

LVDS_VREFHLVDS_VREFL

L_CTRL_DATAL_CTRL_CLK

LVDS_VDD_EN

CRT_RED

CRT_BLUE

L_BKLT_EN

CRT_GREEN

DDBP_DATA0DDBP_DATA0#

DDBP_DATA2#DDBP_DATA2

DDBP_CLK#

DDBP_DATA1#

DDBP_CLK

DDBP_DATA1

L_CTRL_DATAL_CTRL_CLK

LVDS_DDC_CLK_RLVDS_DDC_DATA_R

3D3V_S0

3D3V_S0

3D3V_S0

CRT_HSYNC50CRT_VSYNC50

LVDS_DDC_CLK_R49LVDS_DDC_DATA_R49

LVDSA_DATA049LVDSA_DATA149LVDSA_DATA249

LVDSA_DATA0#49LVDSA_DATA1#49LVDSA_DATA2#49

LVDSA_CLK#49LVDSA_CLK49

L_BKLT_CTRL49

LVDS_VDD_EN49L_BKLT_EN27

CRT_BLUE50CRT_GREEN50CRT_RED50

CRT_DDC_CLK50CRT_DDC_DATA50

HDMI_PCH_DET 51

PCH_HDMI_CLK 51PCH_HDMI_DATA 51

HDMI_DATA0_R 51HDMI_DATA0_R# 51

HDMI_CLK_R 51

HDMI_DATA1_R 51

HDMI_CLK_R# 51

HDMI_DATA1_R# 51HDMI_DATA2_R 51HDMI_DATA2_R# 51

Title


Date: Sheet of


Petra Uma -1

PCH (LVDS/CRT/DDI)A3

17 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1


17 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1


17 103Tuesday, July 10, 2012

<Core Design>

Place near PCH 12

R17012K37R2F-GP

R17012K37R2F-GP

12 3

4

RN1704SRN0J-6-GPRN1704SRN0J-6-GP

1 2C1702 SCD1U10V2KX-L1-GPC1702 SCD1U10V2KX-L1-GP1 2C1701 SCD1U10V2KX-L1-GPC1701 SCD1U10V2KX-L1-GP

1 2C1706 SCD1U10V2KX-L1-GPC1706 SCD1U10V2KX-L1-GP

1 234



12 3

4


1 234


12345 6 7 8

RN1705SRN150F-1-GPRN1705SRN150F-1-GP




12 3

4

RN1702SRN100KJ-6-GPRN1702SRN100KJ-6-GP


12

R17021KR2D-1-GP

R17021KR2D-1-GP

L_BKLTCTLP45

L_BKLTENJ47

L_CTRL_CLKT45

L_CTRL_DATAP39

L_DDC_CLKT40

L_DDC_DATAK47

L_VDD_ENM45

LVDSA_CLK#AK39

LVDSA_CLKAK40

LVDSA_DATA#0AN48

LVDSA_DATA#1AM47

LVDSA_DATA#2AK47

LVDSA_DATA#3AJ48

LVDSA_DATA0AN47

LVDSA_DATA1AM49

LVDSA_DATA2AK49

LVDSA_DATA3AJ47

LVDSB_CLK#AF40

LVDSB_CLKAF39

LVDSB_DATA#0AH45

LVDSB_DATA#1AH47

LVDSB_DATA#2AF49

LVDSB_DATA#3AF45

LVDSB_DATA0AH43

DDPB_0N AV42

DDPB_1N AV45

LVD_VREFHAE48

LVD_VREFLAE47

DDPD_2N BF42

DDPD_3N BJ42

DDPB_2N AU48

DDPB_3N AV47

DDPC_0N AY47

DDPC_1N AY43

DDPC_2N BA47

DDPC_3N BB47

DDPD_0N BB43

DDPD_1N BF44

DDPB_0P AV40

DDPB_1P AV46

DDPD_2P BE42

DDPD_3P BG42

DDPB_2P AU47

DDPB_3P AV49

LVDSB_DATA1AH49

LVDSB_DATA2AF47

LVDSB_DATA3AF43

LVD_IBGAF37

LVD_VBGAF36

DDPC_1P AY45

DDPC_0P AY49

DDPC_2P BA48

DDPC_3P BB49

DDPD_0P BB45

DDPD_1P BE44

CRT_BLUEN48

CRT_DDC_CLKT39

CRT_DDC_DATAM40

CRT_GREENP49

CRT_HSYNCM47

CRT_IRTNT42

CRT_REDT49

CRT_VSYNCM49

DAC_IREFT43

SDVO_CTRLCLK P38

SDVO_CTRLDATA M39

DDPC_CTRLCLK P46

DDPC_CTRLDATA P42

DDPD_CTRLCLK M43

DDPD_CTRLDATA M36

DDPB_AUXN AT49

DDPC_AUXN AP47

DDPD_AUXN AT45

DDPB_AUXP AT47

DDPC_AUXP AP49

DDPD_AUXP AT43

DDPB_HPD AT40

DDPC_HPD AT38

DDPD_HPD BH41

SDVO_TVCLKINP AP45SDVO_TVCLKINN AP43

SDVO_STALLP AM40SDVO_STALLN AM42

SDVO_INTP AP40SDVO_INTN AP39

LVDS

Digital Display Interface

CRT

4 OF 10PCH1D

PANTHER-GP-NF

71.PANTH.00U

LVDS

Digital Display Interface

CRT

4 OF 10PCH1D

PANTHER-GP-NF

71.PANTH.00U

WWW.MANUALS.CLAN.SU

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

TP_IN#

CLK_PCI_LPC_R

INT_PIRQF#INT_PIRQE#

CLK_PCI_FB_RCLK_PCI_KBC_R

INT_PIRQB#INT_PIRQC#INT_PIRQD#

INT_PIRQA#

DGPU_PWM_SELECT#

DGPU_PWR_EN#

DGPU_HOLD_RST#

USB_RBIAS

INT_PIRQG#INT_PIRQC#

DGPU_SELECT#

INT_PIRQG#

DGPU_PWR_EN#DGPU_HOLD_RST#

OC_PWR

CLK_PCI_LPC

INT_PIRQF#INT_PIRQB# INT_PIRQA#

INT_PIRQE#

INT_PIRQD#

3D3V_S0

3D3V_S0

3D3V_S5

3D3V_S0

CLK_PCI_FB20CLK_PCI_KBC27

PLT_RST#5,27,31,36,65,71,97

USB_PN9 61USB_PP9 61


SATA_ODD_DA#56

CLK_PCI_LPC71

USB30_TN262

USB30_TP262

USB30_RN262

USB30_RP262



TP_IN#69


Title


Date: Sheet of


Petra Uma -1

PCH (PCI/USB/NVRAM)Custom

18 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1


18 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1


18 103Tuesday, July 10, 2012

<Core Design>

Reserved 01

11

BOOT BIOS Strap

GNT1#/GPIO51 BOOT BIOS LocationSATA1GP/GPIO19

0 1 Reserved

SPI(Default)

SSID = PCH

0 0 LPC

USB Table

13

12

may not be available

Mini Card1 (WLAN+BT)

USB2.0 Ext. port 3

10

0

11

USB3.0/USB2.0 Ext. port 2

Pair

4

5

2

3

1

Device

6

7

8

9

may not be available

CCD

USB2.0 Ext. port 1

1 2R1805 22R2J-2-GPR1805 22R2J-2-GP

1 2R181122D6R2F-L1-GPR181122D6R2F-L1-GP

1 2R1804 22R2J-2-GPR1804 22R2J-2-GP

1 2R1806 22R2J-2-GPR1806 22R2J-2-GP

12 3

4

RN1803

SRN10KJ-L-GP

RN1803

SRN10KJ-L-GP

RSVD23 AV5

RSVD1 AY7

RSVD2 AV7

RSVD3 AU3

RSVD4 BG4

RSVD5 AT10

RSVD6 BC8

RSVD7 AU2

RSVD8 AT4

RSVD17 BB5

RSVD18 BB3

RSVD19 BB7

RSVD20 BE8

RSVD21 BD4

RSVD22 BF6

RSVD9 AT3

RSVD10 AT1

RSVD11 AY3

RSVD12 AT5

RSVD13 AV3

RSVD14 AV1

RSVD15 BB1

RSVD16 BA3

RSVD25 AT8

RSVD24 AV10

RSVD26 AY5

RSVD27 BA2

RSVD28 AT12

RSVD29 BF3

PIRQA#K40

PIRQB#K38

PIRQC#H38

PIRQD#G38

REQ1#/GPIO50C46

REQ2#/GPIO52C44

REQ3#/GPIO54E40

GNT1#/GPIO51D47

GNT2#/GPIO53E42

GNT3#/GPIO55F46

PIRQE#/GPIO2G42

PIRQF#/GPIO3G40

PIRQG#/GPIO4C42

PIRQH#/GPIO5D44

USBP0N C24

USBP0P A24

USBP1N C25

USBP1P B25

USBP2N C26

USBP2P A26

USBP3N K28

USBP3P H28

USBP4N E28

USBP4P D28

USBP5N C28

USBP5P A28

USBP6N C29

USBP6P B29

USBP7N N28

USBP7P M28

USBP8N L30

USBP8P K30

USBP9N G30

USBP9P E30

USBP10N C30

USBP10P A30

USBP11N L32

USBP11P K32

USBP12N G32

USBP12P E32

USBP13N C32

USBP13P A32

PME#K10

CLKOUT_PCI0H49

CLKOUT_PCI1H43

CLKOUT_PCI2J48

USBRBIAS# C33

USBRBIAS B33

OC0#/GPIO59 A14

OC1#/GPIO40 K20

OC2#/GPIO41 B17

OC3#/GPIO42 C16

OC4#/GPIO43 L16

OC5#/GPIO9 A16

OC6#/GPIO10 D14

OC7#/GPIO14 C14CLKOUT_PCI4H40CLKOUT_PCI3K42

PLTRST#C6

TP1BG26

TP2BJ26

TP3BH25

TP6AH38

TP7AH37

TP8AK43

TP9AK45

TP16Y13

TP17K24

TP18L24

TP19AB46

TP20AB45

TP21B21

TP22M20

TP23AY16

USB3RN1BE28

USB3RN2BC30

USB3RN3BE32

USB3RN4BJ32

USB3RP1BC28

USB3RP2BE30

USB3RP3BF32

USB3RP4BG32

USB3TN1AV26

USB3TN2BB26

USB3TN3AU28

USB3TN4AY30

USB3TP1AU26

USB3TP2AY26

USB3TP3AV28

USB3TP4AW30

TP4BJ16

TP5BG16

TP15AM5TP14AM4TP13AH12TP12H3TP11N30TP10C18

TP24BG46

RSVD

PCI

USB

5 OF 10PCH1E

PANTHER-GP-NF

71.PANTH.00U

RSVD

PCI

USB

5 OF 10PCH1E

PANTHER-GP-NF

71.PANTH.00U

12345 6

78910

RN1801SRN8K2J-2-GP-URN1801SRN8K2J-2-GP-U

12



12

EC1801SC33P50V2JN-3GPDYEC1801SC33P50V2JN-3GPDY


1 2R18130R0402-PAD

R18130R0402-PAD

WWW.MANUALS.CLAN.SU

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

BATLOW#

PM_CLKRUN#

RBIAS_CPY

SUS_PWR_ACK_R

DSWODVREN

PCIE_WAKE#

PM_RSMRST#

BATLOW#PM_RI#AC_PRESENT

SUS_PWR_ACK#

DSWODVREN

SYS_RESET#

PCH_DPWROKPM_RSMRST#

DMI_COMP_R

PM_RI#

SUS_PWR_ACK_R

PM_RSMRST#

3V_5V_POK_#

PWROK

PM_RSMRST#

PCIE_WAKE#

PWROK

SYS_PWROK

SUS_PWR_ACK#

SLLP_SUS#_TP

RTC_AUX_S5

3D3V_S5

1D05V_VTT

3D3V_S0

3D3V_S0

RTC_AUX_S5

3D3V_AUX_S5

DMI_RXP[3:0]4DMI_RXN[3:0]4

PM_SLP_S4# 27,46

PM_CLKRUN# 27

H_PM_SYNC 5

PM_SLP_S3# 27,29,36,37,47

PCH_SUSCLK_KBC 27

DMI_RXP04

S0_PWR_GOOD27

PM_PWRBTN#27,97

DMI_RXP34DMI_RXP24DMI_RXP14

DMI_TXN14DMI_TXN04

DMI_TXP04

DMI_TXN34DMI_TXN24

DMI_TXP34DMI_TXP24DMI_TXP14

DMI_RXN04

PM_DRAM_PWRGD37

AC_PRESENT27

DMI_RXN34DMI_RXN24DMI_RXN14

FDI_LSYNC0 4

FDI_FSYNC1 4

FDI_TXP0 4

FDI_TXN0 4

FDI_INT 4

FDI_TXP6 4

FDI_TXP4 4

FDI_TXN6 4

FDI_TXP5 4

FDI_TXP2 4

FDI_TXN4 4

FDI_TXN7 4

FDI_TXP7 4

FDI_TXN5 4

FDI_TXN2 4FDI_TXN3 4

FDI_LSYNC1 4

FDI_FSYNC0 4

FDI_TXP1 4

FDI_TXP3 4

FDI_TXN1 4

RSMRST#_KBC 27

3V_5V_POK 41

DMI_TXP[3:0]4DMI_TXN[3:0]4

FDI_TXP[7:0] 4

SYS_PWROK36

FDI_TXN[7:0] 4

Title


Date: Sheet of


Petra Uma -1

PCH (DM I/FDI/PM)A3

19 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1

PCH (DM I/FDI/PM)A3

19 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1

PCH (DM I/FDI/PM)A3

19 103Tuesday, July 10, 2012

<Core Design>

Signal Routing Guideline:DMI_ZCOMP keep W=4 mils androuting length less than 500mils.DMI_IRCOMP keep W=4 mils androuting length less than 500mils.

DSWODVREN - On Die DSW VR Enable

HIGH Enabled (DEFAULT)

LOW Disabled

SSID = PCH

S0_PWR_GOOD after PM_SLP_S3# delay 200 ms

12 R1909100KR2J-4-GP

R1909100KR2J-4-GP

1 2R191110KR2J-L-GP

DY

R191110KR2J-L-GP

DY

12 R192110KR2J-L-GP

R192110KR2J-L-GP

1 2R19121KR2J-L2-GP

R19121KR2J-L2-GP


1 2R1918 330KR2J-L1-GPDYR1918 330KR2J-L1-GPDY

1 2R190510KR2J-L-GP

R190510KR2J-L-GP

1 2R192610KR2J-L-GP

DYR1926

10KR2J-L-GP

DY

1 2R1901 49D9R2F-GPR1901 49D9R2F-GP

1 2R1902 750R2F-GPR1902 750R2F-GP

1 2R1904100KR2J-4-GP

R1904100KR2J-4-GP

1 2R1917 330KR2J-L1-GPR1917 330KR2J-L1-GP

12R19240R0402-PADR19240R0402-PAD

1 2R19100R0402-PADR19100R0402-PAD

DMI0RXNBC24

DMI1RXNBE20

DMI2RXNBG18

DMI3RXNBG20

DMI0RXPBE24

DMI1RXPBC20

DMI2RXPBJ18

DMI3RXPBJ20

DMI0TXNAW24

DMI1TXNAW20

DMI2TXNBB18

DMI3TXNAV18

DMI0TXPAY24

DMI1TXPAY20

DMI2TXPAY18

DMI3TXPAU18

DMI_ZCOMPBJ24

DMI_IRCOMPBG25

FDI_RXN0 BJ14

FDI_RXN1 AY14

FDI_RXN2 BE14

FDI_RXN3 BH13

FDI_RXN4 BC12

FDI_RXN5 BJ12

FDI_RXN6 BG10

FDI_RXN7 BG9

FDI_RXP0 BG14

FDI_RXP1 BB14

FDI_RXP2 BF14

FDI_RXP3 BG13

FDI_RXP4 BE12

FDI_RXP5 BG12

FDI_RXP6 BJ10

FDI_RXP7 BH9

FDI_FSYNC0 AV12

FDI_FSYNC1 BC10

FDI_LSYNC0 AV14

FDI_LSYNC1 BB10

FDI_INT AW16

PMSYNCH AP14

SLP_SUS# G16

SLP_S3# F4

SLP_S4# H4

SLP_S5#/GPIO63 D10

SYS_RESET#K3

SYS_PWROKP12

PWRBTN#E20

RI#A10

WAKE# B9

SUS_STAT#/GPIO61 G8

SUSCLK/GPIO62 N14

ACPRESENT/GPIO31H20

BATLOW#/GPIO72E10

PWROKL22

CLKRUN#/GPIO32 N3

SUSWARN#/SUSPWRDNACK/GPIO30K16

RSMRST#C21

DRAMPWROKB13

SLP_LAN#/GPIO29 K14

APWROKL10

DPWROK E22

DMI2RBIASBH21

SLP_A# G10

DSWVRMEN A18

SUSACK#C12

DMI

FDI

System Power Management

3 OF 10PCH1C

PANTHER-GP-NF

71.PANTH.00U

DMI

FDI

System Power Management

3 OF 10PCH1C

PANTHER-GP-NF

71.PANTH.00U

1 2R19198K2R2J-3-GPR19198K2R2J-3-GP

12345

678


12 R192210KR2J-L-GP

R192210KR2J-L-GP 1

2


1

2

34

5

6 Q19012N7002KDW-GP84.2N702.A3F2nd = 84.DM601.03F

Q19012N7002KDW-GP84.2N702.A3F2nd = 84.DM601.03F12 R1908

100KR2J-4-GPR1908100KR2J-4-GP

WWW.MANUALS.CLAN.SU

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

XTAL25_IN

PCIE_CLK_REQ6#

CLK_BUF_EXP_NCLK_BUF_EXP_P

XTAL25_OUT

CLK_BUF_CKSSCD_P

XTAL25_IN

XTAL25_OUT

PCH_GPIO74

DGPU_PRSNT#

PEG_B_CLKRQ#

PCIE_CLK_REQ1#

CLK_BUF_CKSSCD_NCLK_BUF_CKSSCD_PCLK_BUF_REF14

CLK_BUF_EXP_NCLK_BUF_EXP_P

CLK_BUF_DOT96_NCLK_BUF_DOT96_P

PCIE_CLK_REQ4#

XCLK_RCOMP

CLK_BUF_REF14

SMB_DATA

SML0_CLK

PCIE_TXP4_CPCIE_TXN4_C

CLK_BUF_DOT96_PCLK_BUF_DOT96_N

CLK_BUF_CKSSCD_N

SMB_CLK

SML0_DATA

PCIE_CLK_REQ7#

SMB_CLK

SMB_DATA

CLK_BUF_CPYCLK_NCLK_BUF_CPYCLK_P

DGPU_PRSNT#

PCIE_CLK_REQ1#

SMB_CLK

DRAMRST_CNTRL_PCH

SMB_DATA

SML0_DATASML0_CLK

SML1_DATASML1_CLK

PCIE_CLK_REQ4#

CLK_PCIE_WLAN_REQ#

PCH_GPIO74

PCIE_CLK_REQ5#

PEG_B_CLKRQ#PCIE_CLK_REQ7#

EC_SWI#

CLKOUT_DP_N_CCLKOUT_DP_P_C

PEG_CLKREQ#

PCIE_TXP3_CPCIE_TXN3_C

PCIE_CLK_REQ5#

PCIE_CLK_REQ6#

PCIE_CLK_REQ0#

PCIE_CLK_REQ0#

PCIE_CLK_REQ0#

PCIE_CLK_LAN_REQ# PCIE_CLK_LAN_REQ#

1D05V_VTT

3D3V_S0

3D3V_S0 3D3V_S0

3D3V_S0

3D3V_S5

3D3V_S5

3D3V_S0

3D3V_S0

PCIE_RXN465PCIE_RXP465

PCIE_TXN465PCIE_TXP465

CLK_PCI_FB 18

PCH_SMBDATA 14,15,69

PCH_SMBCLK 14,15,69

SML1_DATA 27,28,49

SML1_CLK 27,28,49

DRAMRST_CNTRL_PCH 37

EC_SWI# 27

UMA_DIS# 22

PCIE_CLK_WLAN65PCIE_CLK_WLAN#65

CLK_PCIE_WLAN_REQ#65

CLK_EXP_N 5CLK_EXP_P 5

CLK_DP_P 5CLK_DP_N 5

PCIE_RXN331PCIE_RXP331

PCIE_TXN331PCIE_TXP331

PCIE_CLK_LAN#31PCIE_CLK_LAN31

PCIE_CLK_LAN_REQ#31

Title


Date: Sheet of


Petra Uma -1

PCH (PCI-E/SMBUS/CLOCK/CL)Custom

20 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1


20 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1


20 103Tuesday, July 10, 2012

<Core Design>

SSID = PCH

UMA_DISCRETE#UMA: 1 1DIS :0 1

Optimus(Muxless) : 1 0

WLAN

need very close to PCH

WLAN

PCIECLKRQ1# and PCIECLKRQ2# Support S0 power only

Lan

LAN

-1_20120302A

1234 5

678


12

R20061MR2J-1-GPR20061MR2J-1-GP


12 3

4 RN2006SRN10KJ-L-GPRN2006SRN10KJ-L-GP

12

R201110KR2J-L-GP

DY

R201110KR2J-L-GP

DY


123

4RN2004SRN2K2J-1-GPRN2004SRN2K2J-1-GP

12 3

4RN2018

SRN10KJ-L-GP

RN2018

SRN10KJ-L-GP

12 3

4

RN2008

SRN10KJ-L-GP

RN2008

SRN10KJ-L-GP


PERN1BG34

PERP1BJ34

PERN2BE34

PERP2BF34

PERN3BG36

PERP3BJ36

PERN4BF36

PERP4BE36

PERN5BG37

PERP5BH37

PERN6BJ38

PERP6BG38

PERN7BG40

PERP7BJ40

PERN8BE38

PERP8BC38

PETN1AV32

PETP1AU32

PETN2BB32

PETP2AY32

PETN3AV34

PETP3AU34

PETN4AY34

PETP4BB34

PETN5AY36

PETP5BB36

PETN6AU36

PETP6AV36

PETN7AY40

PETP7BB40

PETN8AW38

PETP8AY38

CLKOUT_PCIE0NY40

CLKOUT_PCIE0PY39

CLKOUT_PCIE1NAB49

CLKOUT_PCIE1PAB47

CLKOUT_PCIE2NAA48

CLKOUT_PCIE2PAA47

CLKOUT_PCIE3NY37

CLKOUT_PCIE3PY36

CLKOUT_PCIE4NY43

CLKOUT_PCIE4PY45

CLKOUT_PCIE5NV45

CLKOUT_PCIE5PV46

CLKIN_GND1_N BJ30

CLKIN_GND1_P BG30

CLKIN_DMI_N BF18

CLKIN_DMI_P BE18

CLKIN_DOT_96N G24

CLKIN_DOT_96P E24

CLKIN_SATA_N AK7

CLKIN_SATA_P AK5

XTAL25_IN V47

XTAL25_OUT V49

REFCLK14IN K45

CLKIN_PCILOOPBACK H45

CLKOUT_PEG_A_N AB37

CLKOUT_PEG_A_P AB38

PEG_A_CLKRQ#/GPIO47 M10

PCIECLKRQ0#/GPIO73J2

PCIECLKRQ1#/GPIO18M1

PCIECLKRQ2#/GPIO20V10

PCIECLKRQ3#/GPIO25A8

PCIECLKRQ4#/GPIO26L12

PCIECLKRQ5#/GPIO44L14

CLKOUTFLEX0/GPIO64 K43

CLKOUTFLEX1/GPIO65 F47

CLKOUTFLEX2/GPIO66 H47

CLKOUTFLEX3/GPIO67 K49

CLKOUT_DMI_N AV22

CLKOUT_DMI_P AU22

PEG_B_CLKRQ#/GPIO56E6

CLKOUT_PEG_B_PAB40CLKOUT_PEG_B_NAB42

XCLK_RCOMP Y47

CLKOUT_DP_P AM13CLKOUT_DP_N AM12

CLKOUT_PCIE6NV40

CLKOUT_PCIE6PV42

PCIECLKRQ7#/GPIO46K12

CLKOUT_PCIE7NV38

CLKOUT_PCIE7PV37

CLKOUT_ITPXDP_NAK14

CLKOUT_ITPXDP_PAK13

SMBALERT#/GPIO11 E12

SMBCLK H14

SMBDATA C9

SML0ALERT#/GPIO60 A12

SML0CLK C8

SML0DATA G12

SML1ALERT#/PCHHOT#/GPIO74 C13

SML1CLK/GPIO58 E14

SML1DATA/GPIO75 M16

CL_CLK1 M7

CL_DATA1 T11

CL_RST1# P10

PCIECLKRQ6#/GPIO45T13

PCI-E*

CLOCKS

FLEX CLOCKS

SMBUS

Controller

Link

2 OF 10PCH1B

PANTHER-GP-NF

71.PANTH.00U

PCI-E*

CLOCKS

FLEX CLOCKS

SMBUS

Controller

Link

2 OF 10PCH1B

PANTHER-GP-NF

71.PANTH.00U

12 3

4RN2005SRN2K2J-1-GPRN2005SRN2K2J-1-GP

12


12

C2008SC15P50V2JN-2-GP



12

R20010R2J-L-GPDY

R20010R2J-L-GPDY

12

R201210KR2J-L-GP

R201210KR2J-L-GP

123

4 RN2003SRN2K2J-1-GPRN2003SRN2K2J-1-GP

1 2R2009

1KR2J-L2-GP

R2009

1KR2J-L2-GP

12

R201010KR2J-L-GP

DY

R201010KR2J-L-GP

DY

12 X2001

XTAL-25MHZ-102-GP82.30020.8512nd = 82.30020.791

X2001XTAL-25MHZ-102-GP82.30020.8512nd = 82.30020.791

12 3

4


12



1234 5

678


12


1 2R200790D9R2F-1-GP

R200790D9R2F-1-GP

1

2

34

5

6

Q20012N7002KDW-GP84.2N702.A3F2nd = 84.DM601.03F


12345 6

78910

RN2009SRN10KJ-L3-GPRN2009SRN10KJ-L3-GP

12 3

4

RN2017SRN0J-6-GP

EDP

RN2017SRN0J-6-GP

EDP

12


WWW.MANUALS.CLAN.SU

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

HDA_SYNC

HDA_CODEC_SYNC

HDA_RST#HDA_BITCLK

HDA_SDOUT

RTC_X2

RTC_X1

HDA_SYNC_R HDA_SYNC

HDA_SYNC

HDA_SDOUT

RTC_RST#_S

RTC_RST#

PCH_SPI_CLK

PCH_SPI_SI

PCH_SPI_CS0#

HDA_BITCLK

HDA_RST#

HDA_SYNC

SATA_DET#0

LPC_AD0LPC_AD1LPC_AD2LPC_AD3

INT_SERIRQ

HDA_SDOUT

RBIAS_SATA3

SATA_COMP

SATA_DET#0

PCH_JTAG_TCK_BUF

RTC_X2

SM_INTRUDER#

SRTC_RST#

PCH_INTVRMEN

RTC_X1

RTC_RST#

SATA3_COMP

SPI_CS0#_RHDA_CODEC_BITCLK HDA_CODEC_SDOUT

SATA_LED#

SATA_LED#

+3VS_+1.5VS_HDA_IO

RTC_AUX_S5

+3VS_+1.5VS_HDA_IO

5V_S0

RTC_AUX_S5

1D05V_VTT

3D3V_S0

1D05V_VTT

HDA_CODEC_BITCLK29HDA_CODEC_RST#29

HDA_CODEC_SDOUT29

HDA_CODEC_SYNC29

RTCRST_ON27

HDA_SPKR29

INT_SERIRQ 27

LPC_AD[0..3] 27,71

HDA_SDIN029

SPI_CS0#_R27,60

SPI_SO_R27,60

SPI_SI_R27,60

SPI_CLK_R27,60

SATA_RXN0 56SATA_RXP0 56SATA_TXN0 56SATA_TXP0 56

ME_UNLOCK27

LPC_FRAME# 27,71

PSW_CLR#22

SATA_RXN4 56SATA_RXP4 56SATA_TXN4 56SATA_TXP4 56

Title


Date: Sheet of


Petra Uma -1

PCH (SPI/RTC/LPC/SATA/IHDA)Custom

21 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1


21 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1


21 103Tuesday, July 10, 2012

<Core Design>

PLL ODVR VOLTAGE

HDA_SYNCLow = 1.8V (Default)High = 1.5V

SSID = PCH

HDA_SDOUTLow = DefaultHigh = Enable

Flash Descriptor Security Overide

HDA_SYNC: This strap is sampled on rising edge of RSMRST# and is used tosample 1.5V VccVRM supply mode. 1K external pull-up resistor is required on thissignal on the board. Signal may have leakage paths via powered off devices (AudioCodec) and hence contend with the external pull-up. A blocking FET isrecommended in such a case to isolate HDA_SYNC from the Audio Codec deviceuntil after the Strap sampling is complete.

ODD

RTC Reset

INTVRMEN- Integrated SUS1.05V VRM EnableHigh - Enable internal VRsLow - Enable external VRs

HDD1

-1_20120223

-1_20120301

12R2122 33R2J-L1-GP

DY

R2122 33R2J-L1-GP

DY

12

R21112KR2F-3-GPR21112KR2F-3-GP

12

EC2101SC4D7P50V2CN-1GPDY


12 R21041MR2J-1-GPR21041MR2J-1-GP

1 2R211620KR2F-L-GPR211620KR2F-L-GP

1 2R2112 37D4R2F-GPR2112 37D4R2F-GP1

2


12


1234 5

678


1 2R2109 33R2J-L1-GPR2109 33R2J-L1-GP

1 2R2124

33R2J-L1-GP

R2124

33R2J-L1-GP

1 2R210833R2J-L1-GPR210833R2J-L1-GP

1 2R211520KR2F-L-GPR211520KR2F-L-GP

1 2R21021KR2J-L2-GP

DY

R21021KR2J-L2-GP

DY

12



12



12

R2106100KR2F-L1-GPR2106100KR2F-L1-GP

1

2 3

4

X2101X-32D768KHZ-34GPU82.30001.6612nd = 82.30001.B21

X2101X-32D768KHZ-34GPU82.30001.6612nd = 82.30001.B21

12R2123 33R2J-L1-GPR2123 33R2J-L1-GP

21

G2101GAP-OPENG2101GAP-OPEN

12

C2101

SC

6P50V

2CN

-1GP

C2 101

SC

6P50V

2CN

-1GP

12 3

4

RN2102SRN33J-5-GP-URN2102SRN33J-5-GP-U

1 2R2113 49D9R2F-GPR2113 49D9R2F-GP

1 2R2105330KR2F-L-GPR2105330KR2F-L-GP

G

S

D

Q21012N7002K-2-GP84.2N702.J312ND = 84.2N702.031

Q21012N7002K-2-GP84.2N702.J312ND = 84.2N702.031

12 R21214K7R2J-L-GP

R21214K7R2J-L-GP

12

C2102SC6P50V2CN-1GP

C2102SC6P50V2CN-1GP

G

S

D

Q21022N7002K-2-GP84.2N702.J312ND = 84.2N702.031

Q21022N7002K-2-GP84.2N702.J312ND = 84.2N702.031

1 2R210110MR2J-L-GPR210110MR2J-L-GP

1 2R211033R2J-L1-GP

R211033R2J-L1-GP

1 2R2103

1KR2J-L2-GP

R2103

1KR2J-L2-GP

1 2R21071KR2J-L2-GP

R21071KR2J-L2-GP

RTCX1A20

RTCX2C20

INTVRMENC17

INTRUDER#K22

HDA_BCLKN34

HDA_SYNCL34

HDA_RST#K34

HDA_SDIN0E34

HDA_SDIN1G34

HDA_SDIN2C34

HDA_SDOA36

SATALED# P3

FWH0/LAD0 C38

FWH1/LAD1 A38

FWH2/LAD2 B37

FWH3/LAD3 C37

LDRQ1#/GPIO23 K36

FWH4/LFRAME# D36

LDRQ0# E36

RTCRST#D20

HDA_SDIN3A34

HDA_DOCK_EN#/GPIO33C36

HDA_DOCK_RST#/GPIO13N32

SRTCRST#G22

SATA0RXN AM3

SATA0RXP AM1

SATA0TXN AP7

SATA0TXP AP5

SATA1RXN AM10

SATA1RXP AM8

SATA1TXN AP11

SATA1TXP AP10

SATA2RXN AD7

SATA2RXP AD5

SATA2TXN AH5

SATA2TXP AH4

SATA3RXN AB8

SATA3RXP AB10

SATA3TXN AF3

SATA3TXP AF1

SATA4RXN Y7

SATA4RXP Y5

SATA4TXN AD3

SATA4TXP AD1

SATA5RXN Y3

SATA5RXP Y1

SATA5TXN AB3

SATA5TXP AB1

SATAICOMPI Y10

SPI_CLKT3

SPI_CS0#Y14

SPI_CS1#T1

SPI_MOSIV4

SPI_MISOU3

SATA0GP/GPIO21 V14

SATA1GP/GPIO19 P1

JTAG_TCKJ3

JTAG_TMSH7

JTAG_TDIK5

JTAG_TDOH1

SERIRQ V5

SPKRT10

SATAICOMPO Y11

SATA3COMPI AB13

SATA3RCOMPO AB12

SATA3RBIAS AH1

RTC

IHDA

SATA

LPC

SPI

JTAG

SATA 6G

1 OF 10PCH1A

PANTHER-GP-NF

71.PANTH.00U

RTC

IHDA

SATA

LPC

SPI

JTAG

SATA 6G

1 OF 10PCH1A

PANTHER-GP-NF

71.PANTH.00U

1 2R2114 750R2F-GPR2114 750R2F-GP

WWW.MANUALS.CLAN.SU

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

USB3_SUPPORT

FDI_OVRVLTG

DMI_OVRVLTG

H_PECI_R

PLL_ODVR_EN

PCH_GPIO12

PCH_GPIO22

PCH_GPIO24

PCH_GPIO15

EC_SMI#

DGPU_HPD_INTR#

PCH_GPIO27

PLL_ODVR_EN

DMI_OVRVLTG

ICC_EN#

SPK_HPD_C

ICC_EN#

VRAM_SIZE1

VRAM_SIZE2

VRAM_SIZE1VRAM_SIZE2

FP_DET#

DGPU_HPD_INTR#

PCH_NCTF_4

PCH_NCTF_1

H_RCIN#

S_GPIO

H_A20GATE

EC_SCI#

FP_DET#

PCH_THERMTRIP_R

EC_SMI#

S_GPIO

PCH_GPIO15

PCH_NCTF_3

PCH_NCTF_2

PCH_GPIO22

FDI_OVRVLTG

NV_CLE

NV_CLE

SPK_HPD_C

PCH_GPIO24

PCH_GPIO27

PCH_GPIO12

USB3_SUPPORT

PCH_GPIO48

PCH_GPIO48

PCH_GPIO49PCH_GPIO49

3D3V_S0

3D3V_S0

3D3V_S0

3D3V_S5

3D3V_S0

3D3V_S0

1D8V_S0

3D3V_S5

H_A20GATE 27

H_CPUPWRGD 5,36,97

H_RCIN# 27

H_PECI 5,27

EC_SCI#27

UMA_DIS# 20

PSW_CLR#21

H_THERMTRIP# 5,36

SATA_ODD_PWRGT 56

SATA_ODD_PRSNT#56

H_SNB_IVB# 5

EDP#_LVDS49

Title


Date: Sheet of


Petra Uma -1

PCH (GPIO/CPU)Custom

22 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1


22 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1


22 103Tuesday, July 10, 2012

<Core Design>

SSID = PCH

ICC_EN#

GPIO36(DMI_OVRVLTG)

DMI TERMINATION VOLTAGE OVERRIDE

LOW - Tx, Rx terminated to same voltage(DC Coupling Model DEFAULT)

PLL ON DIE VR ENABLE

NOTE:This signal has a weak internal pull-up 20KENABLED -- HIGH (R2212 UNSTUFFED) DEFAULTDISABLED -- LOW (R2212 STUFFED)

LOW (R2211)- ENABLED

Integrated Clock Chip Enable

HIGH (R2211 DY)- DISABLED [DEFAULT]

Integrated Clock Enable functionality is achievedvia soft-strap. The default is integrated clockenable.

GPIO37(FDI_OVRVLTG)

FDI TERMINATION VOLTAGE OVERRIDE

LOW - Tx, Rx terminated to same voltage(DC Coupling Model DEFAULT)

GPIO8 has a weak[20K] internal pull up.

Pass Word Clear

12

R221410KR2J-L-GP

DY

R221410KR2J-L-GP

DY

1 2R2204390R2J-1-GP

R2204390R2J-1-GP

12

R221610KR2J-L-GPDY

R221610KR2J-L-GPDY

12


12


12

R221910KR2J-L-GPDY

R221910KR2J-L-GPDY

1234 5

678


12

R22121KR2J-L2-GPDY

R22121KR2J-L2-GPDY


1 2R2202

10KR2J-L-GP

R2202

10KR2J-L-GP

12

R222210KR2J-L-GPNo-USB30

R222210KR2J-L-GPNo-USB30

12

R221510KR2J-L-GP

DY

R221510KR2J-L-GP

DY

12


1234 5

678


1 2R22051KR2J-L2-GP

R22051KR2J-L2-GP

1 2R22030R2J-L-GP

DY R22030R2J-L-GP

DY

12 3

4RN2203

SRN10KJ-L-GP

RN2203

SRN10KJ-L-GP

12

R221710KR2J-L-GPDY

R221710KR2J-L-GPDY

21

G2201GAP-OPENG2201GAP-OPEN

12

R22111KR2J-L2-GPDY

R22111KR2J-L2-GPDY

12

R222110KR2J-L-GPUSB30

R222110KR2J-L-GPUSB30

GPIO27E16

GPIO28P8

GPIO24E8

GPIO57D6

LAN_PHY_PWR_CTRL/GPIO12C4

VSS_NCTF_1#A4A4

VSS_NCTF_2#A44A44

VSS_NCTF_3#A45A45

VSS_NCTF_4#A46A46

VSS_NCTF_5#A5A5

VSS_NCTF_6#A6A6

VSS_NCTF_7#B3B3

VSS_NCTF_8#B47B47

VSS_NCTF_9#BD1BD1

VSS_NCTF_10#BD49BD49

VSS_NCTF_11#BE1BE1

VSS_NCTF_12#BE49BE49

TACH2/GPIO6H36

TACH0/GPIO17D40

TACH3/GPIO7E38

SATA3GP/GPIO37M5

SATA5GP/GPIO49/TEMP_ALERT#V3

SCLOCK/GPIO22T5

SLOAD/GPIO38N2

SDATAOUT0/GPIO39M3

SDATAOUT1/GPIO48V13

PROCPWRGD AY11

RCIN# P5

PECI AU16

THRMTRIP# AY10

GPIO8C10

BMBUSY#/GPIO0T7

GPIO15G2

TACH1/GPIO1A42

SATA2GP/GPIO36V8

INIT3_3V# T14

STP_PCI#/GPIO34K1

GPIO35K4

SATA4GP/GPIO16U2

VSS_NCTF_32#F49 F49

A20GATE P4

TACH4/GPIO68 C40

TACH6/GPIO70 C41

TACH7/GPIO71 A40

TACH5/GPIO69 B41

VSS_NCTF_17#BH3 BH3

VSS_NCTF_18#BH47 BH47

VSS_NCTF_19#BJ4 BJ4

VSS_NCTF_20#BJ44 BJ44



VSS_NCTF_23#BJ5 BJ5

VSS_NCTF_24#BJ6 BJ6

VSS_NCTF_25#C2 C2

VSS_NCTF_26#C48 C48

VSS_NCTF_27#D1 D1

VSS_NCTF_28#D49 D49

VSS_NCTF_29#E1 E1

VSS_NCTF_30#E49 E49

VSS_NCTF_31#F1 F1

TS_VSS4 AK10

TS_VSS3 AH10

TS_VSS2 AK11

TS_VSS1 AH8

NC_1 P37

VSS_NCTF_13#BF1BF1

VSS_NCTF_14#BF49BF49

VSS_NCTF_15#BG2 BG2

VSS_NCTF_16#BG48 BG48

DF_TVS AY1

CPU/MISC

NCTF

GPIO

6 OF 10

NCTF TEST PIN:

A4,A44,A45,A46,A5,A6,B3,B47,

BD1,BD49,BE1,BE49,BF1,BF49,

BG2,BG48,BH3,BH47,BJ4,BJ44,

BJ45,BJ46,BJ5,BJ6,C2,C48,D1,

D49,E1,E49,F1,F49

PCH1F

PANTHER-GP-NF

71.PANTH.00U

CPU/MISC

NCTF

GPIO

6 OF 10

NCTF TEST PIN:

A4,A44,A45,A46,A5,A6,B3,B47,

BD1,BD49,BE1,BE49,BF1,BF49,

BG2,BG48,BH3,BH47,BJ4,BJ44,

BJ45,BJ46,BJ5,BJ6,C2,C48,D1,

D49,E1,E49,F1,F49

PCH1F

PANTHER-GP-NF

71.PANTH.00U

1 2R22011KR2J-L2-GP

R22011KR2J-L2-GP

1234 5

678


12

R22092K2R2J-2-GPR22092K2R2J-2-GP




12


WWW.MANUALS.CLAN.SU

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

+1.05VS_VCC_DMI_CCI

+1.8VS_VCCTX_LVDS

+VCCA_DAC_1_2

+3VS_VCCA_LVDS+3VS_VCCA_LVDS

VCCVRM_S0

VCCVRM_S0

1D05V_VTT

1D05V_VTT

1D05V_VTT

1D05V_VTT

3D3V_S0

1D05V_VTT

3D3V_S0

1D05V_VTT

1D8V_S0

3D3V_DAC_S0

3D3V_S0

1D8V_S0

5V_S0 3D3V_DAC_S0

1D05V_VTT3D3V_S5

VCCVRM_S01D5V_S0_PCH

1D5V_S0_PCH1D5V_S0

Title


Date: Sheet of


Petra Uma -1

PCH (POWER1)A3

23 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1

PCH (POWER1)A3

23 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1

PCH (POWER1)A3

23 103Tuesday, July 10, 2012

<Core Design>

SSID = PCH

1.7A

3.711A(Total)

228mA(Total)

167mA(Total)

47mA(Total)10mA

2mA

70mA

40mA

1mA

63mA

12

C2310SCD1U10V2KX-L1-GP


1 2R23050R0603-PADR23050R0603-PAD

1 2PG4317

GAP-CLOSE-PWR

PG4317

GAP-CLOSE-PWR

12

C2309

SC

1U6D

3V2K

X-L-1-G

PC

2309S

C1U

6D3V

2KX

-L-1-GP

12

C2306

SC

1U6D

3V2K

X-L-1-G

P

DY

C2306

SC

1U6D

3V2K

X-L-1-G

P

DY

12

C2303

SC

1U6D

3V2K

X-L-1-G

PC

2303S

C1U

6D3V

2KX

-L-1-GP

12

C2317

SC

D01U

16V2K

X-L1-G

PC

2317S

CD

01U16V

2KX

-L1-GP

12

C2327

SC

10U6D

3V3M

X-L-G

PC

2327S

C10U

6D3V

3MX

-L-GP

12

C2314

SC

D1U

10V2K

X-L1-G

PC

2314S

CD

1U10V

2KX

-L1-GP

12

C2321

SC

1U6D

3V2K

X-L-1-G

PC

2321S

C1U

6D3V

2KX

-L-1-GP

12


1 2PG4318

GAP-CLOSE-PWR

PG4318

GAP-CLOSE-PWR

1 2

L2303IND-10UH-218-GP

68.10050.10Y2nd = 68.10090.10B


68.10050.10Y2nd = 68.10090.10B

12

C2313

SC

D01U

16V2K

X-L1-G

PC

2313S

CD

01U16V

2KX

-L1-GP

12

C2325

SC

10U6D

3V5K

X-1G

P

DY

C2325

SC

10U6D

3V5K

X-1G

P

DY

12

C2318

SC

1U25V

3KX

-1-GP

DY

C2318

SC

1U25V

3KX

-1-GP

DY

1 2R23040R0603-PADR23040R0603-PAD

12

C2307

SC

1U6D

3V2K

X-L-1-G

PC

2307S

C1U

6D3V

2KX

-L-1-GP

12

C2304

SC

1U6D

3V2K

X-L-1-G

PC

2304S

C1U

6D3V

2KX

-L-1-GP

12

C2301

SC

10U6D

3V5K

X-1G

PC

2301S

C10U

6D3V

5KX

-1GP

12

C2308

SC

1U6D

3V2K

X-L-1-G

PC

2308S

C1U

6D3V

2KX

-L-1-GP

12

C2316

SC

D01U

16V2K

X-L1-G

PC

2316S

CD

01U16V

2KX

-L1-GP

12


12

C2311SC

1U10V

2KX

-1GP

C2311SC

1U10V

2KX

-1GP

12


12



12

C2312

SC

1U6D

3V2K

X-L-1-G

PC

2312S

C1U

6D3V

2KX

-L-1-GP

12 R23020R0603-PADR23020R0603-PAD

1 2PG4319

GAP-CLOSE-PWR

PG4319

GAP-CLOSE-PWR

12

C2315

SC

10U6D

3V5K

X-1G

P

DY

C2315

SC

10U6D

3V5K

X-1G

P

DY

1 2R23150R0402-PADR23150R0402-PAD

12


VCCCORE1AA23

VCCCORE2AC23

VCCCORE3AD21

VCCCORE4AD23

VCCCORE5AF21

VCCCORE6AF23

VCCCORE7AG21

VCCCORE8AG23

VCCCORE9AG24

VCCCORE10AG26

VCCCORE11AG27

VCCCORE12AG29

VCCCORE13AJ23

VCCCORE14AJ26

VCCCORE15AJ27

VCCDFTERM4 AJ17

VCCDFTERM3 AJ16

VCCIO17AN21

VCCIO18AN26

VCCIO19AN27

VCCIO20AP21

VCCIO23AP26

VCCIO24AT24

VCCIO15AN16

VCCIO16AN17

VCCIO21AP23

VCCIO22AP24

VCCADAC U48

VCCTX_LVDS1 AM37

VCCTX_LVDS2 AM38

VCCALVDS AK36

VCCVRM3 AT16

VCCVRM2AP16

VCCAPLLEXPBJ22

VCCAFDIPLLBG6

VCCIO28AN19VCCTX_LVDS4 AP37

VCCTX_LVDS3 AP36

VSSADAC U47

VSSALVDS AK37

VCCIO27AP17

VCC3_3_6 V33

VCC3_3_7 V34

VCC3_3_3BH29 VCCDFTERM2 AG17

VCCDFTERM1 AG16

VCCDMI1 AT20

VCCIO25AN33

VCCIO26AN34

VCCCORE16AJ29

VCCCORE17AJ31

VCCSPI V1

VCCCLKDMI AB36

VCCDMI2AU20

POWER

VCC CORE

DMI

VCCIO

CRT

LVDS

FDI

DFT / SPI

HVCMOS

7 OF 10PCH1G

PANTHER-GP-NF

71.PANTH.00U

POWER

VCC CORE

DMI

VCCIO

CRT

LVDS

FDI

DFT / SPI

HVCMOS

7 OF 10PCH1G

PANTHER-GP-NF

71.PANTH.00U

NC#4 4

OUT 5IN1

GND2

EN3

U2301

TLV70233DBVR-GP

2nd = 74.08818.B3F74.70233.03F

U2301

TLV70233DBVR-GP

2nd = 74.08818.B3F74.70233.03F

12

C2302

SC

1U6D

3V2K

X-L-1-G

PC

2302S

C1U

6D3V

2KX

-L-1-GP

WWW.MANUALS.CLAN.SU

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

+1.05VS_VCCA_A_DPL

+VCCRTCEXT

+1.05VS_VCCA_A_DPL+1.05VS_VCCA_A_DPL

+VCCSST

+1.05VS_VCCA_B_DPL

+5VA_PCH_VCC5REFSUS

+5VS_PCH_VCC5REF

+1.05VS_VCCA_B_DPL+1.05VS_VCCA_B_DPL

VCCDSW3_3

1D5V_S0_PCH

3D3V_S5

3D3V_S5

1D05V_VTT

1D05V_VTT

3D3V_S0

3D3V_S0

1D05V_VTT

1D05V_VTT

1D05V_VTT

RTC_AUX_S5

1D05V_VTT

1D05V_VTT

3D3V_S0

VCCVRM_S0

1D05V_VTT

1D05V_VTT

3D3V_S5

1D05V_VTT

3D3V_S5

5V_S0

5V_S5

VCCVRM_S0

+3VS_+1.5VS_HDA_IO

+3VS_+1.5VS_HDA_IO

3D3V_S5

1D05V_VTT

1D05V_VTT

3D3V_S5

3D3V_S5

3D3V_S0

1D5V_S53D3V_S5

1D5V_S5

3D3V_AUX_S5

Title


Date: Sheet of


Petra Uma -1

PCH (POWER2)Custom

24 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1

PCH (POWER2)Custom

24 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1

PCH (POWER2)Custom

24 103Tuesday, July 10, 2012

<Core Design>

SSID = PCH

1mA

903mA

80mA

80mA

55mA

1mA

6uA

10mA

1mA

1mA

95mA

12


12


12

C2406

SC

1U6D

3V2K

X-L-1-G

PC

2406S

C1U

6D3V

2KX

-L-1-GP

12

C2417

SC

4D7U

6D3V

3KX

-L-GP

C2417

SC

4D7U

6D3V

3KX

-L-GP

12

C2402SC1U10V2KX-1GP

C2402SC1U10V2KX-1GP

1 2R240810R2J-2-GPR240810R2J-2-GP1

2


1 2

C2412

SC1U6D3V2KX-L-1-GP

C2412

SC1U6D3V2KX-L-1-GP

1 2R24090R0603-PADR24090R0603-PAD

12


12


12

C2403

SC

10U6D

3V5K

X-1G

PC

2403S

C10U

6D3V

5KX

-1GP

1 2R24150R3J-4-GP

DYR24150R3J-4-GP

DY

DCPSUSBYPV12

VCCASW1AA19

VCCASW2AA21

VCCASW3AA24

VCCASW5AA27

VCCASW6AA29

VCCSUSHDA P32

VCCSUS3_3_6 P24

VCCIO34 T26

VCCIO4 AD17

VCCASW7AA31

VCCASW8AC26

VCCASW9AC27

VCCASW10AC29

VCCASW11AC31

VCCASW12AD29

V5REF P34

VCC3_3_4 T34

VCCRTCA22

VCCSUS3_3_10 V24

VCCSUS3_3_9 V23

VCCSUS3_3_8 T24

VCCSUS3_3_7 T23

VCCIO2 AC16

VCCADPLLBBF47

VCCDIFFCLKN1AF33

V5REF_SUS M26

VCCIO3 AC17

DCPSUS1T17

VCCSSCAG33

VCCADPLLABD47

VCCVRM4Y49

VCCACLKAD49

DCPRTCN16

VCCASW4AA26

VCCDIFFCLKN2AF34

VCCIO7AF17

DCPSSTV16

VCCIO5 AF13

VCCASW22 T21

VCCASW23 V21

VCCASW21 T19

VCC3_3_1 AA16

VCC3_3_8 W16

VCCSUS3_3_2 N20

VCCSUS3_3_3 N22

VCCSUS3_3_4 P20

VCCSUS3_3_5 P22

VCCIO29 N26

VCCIO30 P26

VCCIO31 P28

VCCIO32 T27

V_PROC_IOBJ8

VCCIO33 T29

VCCDIFFCLKN3AG34

VCCASW13AD31

VCCASW14W21

VCCASW15W23

VCCASW16W24

VCCASW17W26

VCCASW18W29

VCCASW19W31

VCCASW20W33

VCCIO6 AF14

VCCVRM1 AF11

VCCIO12 AH13

VCCIO13 AH14

VCC3_3_2 AJ2

VCCAPLLSATA AK1

DCPSUS3AL24

VCCIO14AL29

DCPSUS4 AN23

VCCSUS3_3_1 AN24

VCCAPLLDMI2BH23

DCPSUS2V19

VCCDSW3_3T16

VCC3_3_5T38

POWER

SATA

USB

Clock and Miscellaneous

HDA

CPU

RTC

PCI/GPIO/LPC

MISC

10 OF 10PCH1J

PANTHER-GP-NF

71.PANTH.00U

POWER

SATA

USB

Clock and Miscellaneous

HDA

CPU

RTC

PCI/GPIO/LPC

MISC

10 OF 10PCH1J

PANTHER-GP-NF

71.PANTH.00U

12



12


1 2


68.10050.10Y2nd = 68.10090.10B


68.10050.10Y2nd = 68.10090.10B

12

C2437

SC

1U10V

3ZY

-6GP

DY

C2437

SC

1U10V

3ZY

-6GP

DY

12


12 R24030R2J-L-GPDY

R24030R2J-L-GPDY

12



12


12

C2407

SC

1U6D

3V2K

X-L-1-G

PC

2407S

C1U

6D3V

2KX

-L-1-GP

12


VIN1

GND2

EN3 NC#4 4

VOUT 5

U2401

G9090-150T11U-GP

DY

74.09090.A3F

U2401

G9090-150T11U-GP

DY

74.09090.A3F

1 2


68.10050.10Y2nd = 68.10090.10B


68.10050.10Y2nd = 68.10090.10B

12


12

C2414SC1U6D3V2KX-L-1-GP


12


12

C2418

SC

D1U

10V2K

X-L1-G

PC

2418S

CD

1U10V

2KX

-L1-GP

12

C2419

SC

D1U

10V2K

X-L1-G

P

DY

C2419

SC

D1U

10V2K

X-L1-G

P

DY

12

C2421

SC

1U10V

3ZY

-6GP

DY

C2421

SC

1U10V

3ZY

-6GP

DY

1 2C2413

SC1U6D3V2KX-L-1-GP

C2413

SC1U6D3V2KX-L-1-GP

12


21

D2401CH751H-40PT-GP83.R0304.A8F

2nd = 83.R0304.D8F

D2401CH751H-40PT-GP83.R0304.A8F

2nd = 83.R0304.D8F

12


DY


DY

21

D2402CH751H-40PT-GP83.R0304.A8F2nd = 83.R0304.D8F

D2402CH751H-40PT-GP83.R0304.A8F2nd = 83.R0304.D8F

1 2R24100R3J-4-GP

DYR24100R3J-4-GP

DY

1 2R24020R0402-PADR24020R0402-PAD

12

C2408

SC

1U6D

3V2K

X-L-1-G

P

DY

C2408

SC

1U6D

3V2K

X-L-1-G

P

DY

12

C2404

SC

10U6D

3V5K

X-1G

PC

2404S

C10U

6D3V

5KX

-1GP

12


12


12

C2416

SC

10U6D

3V5K

X-1G

P

DY

C2416

SC

10U6D

3V5K

X-1G

P

DY

1 2R240710R2J-2-GPR240710R2J-2-GP

WWW.MANUALS.CLAN.SU

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of


Petra Uma -1

PCH (VSS)A3


<Core Design>

Title


Date: Sheet of


Petra Uma -1

PCH (VSS)A3


<Core Design>

Title


Date: Sheet of


Petra Uma -1

PCH (VSS)A3


<Core Design>

SSID = PCH

VSS159AY4

VSS160AY42

VSS161AY46

VSS162AY8

VSS163B11

VSS164B15

VSS165B19

VSS166B23

VSS167B27

VSS168B31

VSS169B35

VSS170B39

VSS171B7

VSS173BB12

VSS174BB16

VSS175BB20

VSS176BB22

VSS177BB24

VSS178BB28

VSS179BB30

VSS180BB38

VSS181BB4

VSS182BB46

VSS183BC14

VSS184BC18

VSS185BC2

VSS186BC22

VSS187BC26

VSS188BC32

VSS189BC34

VSS190BC36

VSS191BC40

VSS192BC42

VSS193BC48

VSS194BD46

VSS195BD5

VSS196BE22

VSS197BE26

VSS198BE40

VSS199BF10

VSS200BF12

VSS201BF16

VSS202BF20

VSS203BF22

VSS204BF24

VSS205BF26

VSS206BF28

VSS207BD3

VSS208BF30

VSS209BF38

VSS210BF40

VSS211BF8

VSS212BG17

VSS213BG21

VSS214BG33

VSS215BG44

VSS216BG8

VSS217BH11

VSS218BH15

VSS219BH17

VSS220BH19

VSS222BH27

VSS223BH31

VSS224BH33

VSS225BH35

VSS226BH39

VSS227BH43

VSS228BH7

VSS229D3

VSS230D12

VSS231D16

VSS232D18

VSS233D22

VSS234D24

VSS235D26

VSS236D30

VSS237D32

VSS264 K7

VSS265 L18

VSS266 L2

VSS267 L20

VSS268 L26

VSS269 L28

VSS270 L36

VSS271 L48

VSS272 M12

VSS273 P16

VSS274 M18

VSS275 M22

VSS276 M24

VSS277 M30

VSS278 M32

VSS279 M34

VSS280 M38

VSS281 M4

VSS282 M42

VSS283 M46

VSS284 M8

VSS285 N18

VSS286 P30

VSS288 P11

VSS289 P18

VSS290 T33

VSS291 P40

VSS292 P43

VSS293 P47

VSS294 P7

VSS295 R2

VSS296 R48

VSS297 T12

VSS298 T31

VSS299 T37

VSS300 T4

VSS301 W34

VSS302 T46

VSS303 T47

VSS304 T8

VSS305 V11

VSS306 V17

VSS307 V26

VSS308 V27

VSS309 V29

VSS310 V31

VSS311 V36

VSS312 V39

VSS313 V43

VSS314 V7

VSS315 W17

VSS316 W19

VSS238D34

VSS239D38

VSS240D42

VSS241D8

VSS242E18

VSS243E26

VSS244G18

VSS245G20

VSS246G26

VSS247G28

VSS248G36

VSS249G48

VSS250H12

VSS251H18

VSS317 W2

VSS318 W27

VSS319 W48

VSS320 Y12

VSS321 Y38

VSS322 Y4

VSS323 Y42

VSS324 Y46

VSS325 Y8

VSS328 BG29

VSS329 N24

VSS330 AJ3

VSS287 N47

VSS252H22

VSS253H24

VSS254H26

VSS255H30

VSS256H32

VSS257H34

VSS258F3

VSS262 K39

VSS263 K46

VSS259 H46

VSS260 K18

VSS261 K26

VSS331 AD47

VSS333 B43

VSS334 BE10

VSS335 BG41

VSS337 G14

VSS338 H16

VSS340 T36

VSS342 BG22

VSS343 BG24

VSS344 C22

VSS345 AP13

VSS172F45

VSS221H10

VSS346 M14

VSS347 AP3

VSS348 AP1

VSS349 BE16

VSS350 BC16

VSS351 BG28

VSS352 BJ28

9 OF 10PCH1I

PANTHER-GP-NF

71.PANTH.00U

9 OF 10PCH1I

PANTHER-GP-NF

71.PANTH.00U

VSS1AA17

VSS2AA2

VSS3AA3

VSS5AA34

VSS6AB11

VSS7AB14

VSS8AB39

VSS9AB4

VSS10AB43

VSS11AB5

VSS12AB7

VSS13AC19

VSS14AC2

VSS15AC21

VSS16AC24

VSS17AC33

VSS18AC34

VSS19AC48

VSS20AD10

VSS21AD11

VSS22AD12

VSS23AD13

VSS24AD19

VSS25AD24

VSS26AD26

VSS27AD27

VSS28AD33

VSS29AD34

VSS30AD36

VSS31AD37

VSS33AD39

VSS34AD4

VSS35AD40

VSS36AD42

VSS37AD43

VSS38AD45

VSS39AD46

VSS43AF10

VSS44AF12

VSS46AD16

VSS47AF16

VSS48AF19

VSS49AF24

VSS50AF26

VSS51AF27

VSS52AF29

VSS53AF31

VSS54AF38

VSS55AF4

VSS56AF42

VSS57AF46

VSS59AF7

VSS60AF8

VSS61AG19

VSS62AG2

VSS63AG31

VSS64AG48

VSS65AH11

VSS66AH3

VSS67AH36

VSS68AH39

VSS69AH40

VSS70AH42

VSS71AH46

VSS72AH7

VSS73AJ19

VSS76AJ33

VSS77AJ34

VSS78AK12

VSS79AK3

VSS80 AK38

VSS81 AK4

VSS82 AK42

VSS83 AK46

VSS84 AK8

VSS85 AL16

VSS86 AL17

VSS87 AL19

VSS88 AL2

VSS89 AL21

VSS90 AL23

VSS91 AL26

VSS92 AL27

VSS93 AL31

VSS96 AL48

VSS97 AM11

VSS98 AM14

VSS99 AM36

VSS100 AM39

VSS102 AM45

VSS103 AM46

VSS104 AM7

VSS105 AN2

VSS106 AN29

VSS107 AN3

VSS108 AN31

VSS109 AP12

VSS110 AP19

VSS111 AP28

VSS112 AP30

VSS113 AP32

VSS114 AP38

VSS116 AP42

VSS117 AP46

VSS118 AP8

VSS119 AR2

VSS120 AR48

VSS121 AT11

VSS122 AT13

VSS123 AT18

VSS124 AT22

VSS125 AT26

VSS126 AT28

VSS127 AT30

VSS128 AT32

VSS131 AT42

VSS132 AT46

VSS133 AT7

VSS134 AU24

VSS135 AU30

VSS136 AV16

VSS137 AV20

VSS138 AV24

VSS139 AV30

VSS140 AV38

VSS141 AV4

VSS142 AV43

VSS143 AV8

VSS144 AW14

VSS145 AW18

VSS146 AW2

VSS147 AW22

VSS148 AW26

VSS149 AW28

VSS150 AW32

VSS151 AW34

VSS152 AW36

VSS153 AW40

VSS154 AW48

VSS155 AV11

VSS156 AY12

VSS157 AY22

VSS158 AY28

VSS40AD8

VSS42AE3

VSS45AD14

VSS115 AP4

VSS0H5

VSS58AF5

VSS32AD38

VSS4AA33

VSS74AJ21

VSS75AJ24

VSS41AE2

VSS129 AT34

VSS130 AT39

VSS101 AM43

VSS95 AL34VSS94 AL33

8 OF 10PCH1H

PANTHER-GP-NF

71.PANTH.00U

8 OF 10PCH1H

PANTHER-GP-NF

71.PANTH.00U

WWW.MANUALS.CLAN.SU

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of


Petra Uma -1

Clock(colay)A4


<Core Design>

Title


Date: Sheet of


Petra Uma -1

Clock(colay)A4


<Core Design>

Title


Date: Sheet of


Petra Uma -1

Clock(colay)A4


<Core Design>

(Blanking)

WWW.MANUALS.CLAN.SU

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

EC_SPI_DI_C

PCB_VER_AD

DISCRETE#

ADT_TYPE

BAT_SCLBAT_SDA

ECSWI#_KBC

BLUETOOTH_EN

AD_OFF

STOP_CHG#CHG_ON#

PROCHOT_EC

H_PROCHOT#_EC

ECRST#_BPURE_HW_SHUTDOWN#_R PURE_HW_SHUTDOWN#

FAN_TACH1

ECRST#

ECSCI#_KBC

AD

_IA

KBC_PWRBTN#_R

BAT_IN#

ECRST#

PCH_SUSCLK_KBC

EC_ENABLE#

S5_ENABLE

MODEL_ID

KBC_VCORF

PCB_VER_AD

EC_VBKUP

EC_ENABLE#EC_SPI_CLK_C

PROCHOT_EC

EC_SPI_DO_C KBC_PWRBTN#_R

ECSWI#_KBC

MODEL_ID

EC_SPI_CS#_C

EC_VSBY

EC_VSBY

EC_VBKUP

LPC_AD0LPC_AD1LPC_AD2LPC_AD3

DISCRETE#

EC_SPI_DI_C

ECSCI#_KBC

ADT_TYPE

KROW0KROW1

KROW3KROW4

KROW2

KROW5KROW6KROW7

KCOL10KCOL9

KCOL16KCOL15KCOL14KCOL13KCOL12KCOL11

KCOL2KCOL1

KCOL4KCOL3

KCOL6KCOL5

KCOL8KCOL7

KCOL17

KCOL0

PECI

ECRST#

LAN_WAKE#

WLAN_WAKE#

WLAN_PWR_EN#

3D3V_SRC_EN

AP_DET#

3D3V_SRC_EN

AP_DET#

3D3V_AUX_KBC 3D3V_AUX_S5

3D3V_AUX_KBC

3D3V_SRC

3D3V_AUX_KBC

3D3V_S0

3D3V_AUX_KBC

3D3V_AUX_KBC3D3V_AUX_S5

3D3V_SRC

3D3V_S0

3D3V_AUX_KBC3D3V_AUX_KBC

RTC_AUX_S5

1D05V_VTT

3D3V_IOAC

3D3V_SRC

3D3V_AUX_KBC

3D3V_IOAC

VDD33

EC_SCI#22

EC_SWI#20

PURE_HW_SHUTDOWN#28,36

H_PROCHOT# 5,42

KBC_PWRBTN#29,68,82

DC_BATFULL 68

CHG_ON# 40

BLON_OUT 49

H_A20GATE 22H_RCIN# 22

CLK_PCI_KBC 18

ALL_POWER_OK37,42,48

WIFI_RF_EN65

AD_IA40

AD_OFF38

PLT_RST# 5,18,31,36,65,71,97

SPI_CLK_R21,60

RSMRST#_KBC19

BAT_SDA 39,40BAT_SCL 39,40

SML1_DATA 20,28,49SML1_CLK 20,28,49

AC_PRESENT19

LID_CLOSE#70TPCLK 69TPDATA 69

INT_SERIRQ 21

SPI_SI_R21,60

S0_PWR_GOOD19

PM_CLKRUN# 19

SPI_CS0#_R21,60

PM_PWRBTN#19,97

BAT_IN#39

LPC_AD[0..3] 21,71

BLUETOOTH_EN65

LPC_FRAME# 21,71

SPI_SO_R21,60

S5_ENABLE36,97

PM_SLP_S4#19,46

USB_PWR_EN#61,62

STOP_CHG#40

CHARGE_LED68

KROW[0..7] 69

AMP_MUTE#29

KCOL[0..17] 69

FAN1_PWM28

PM_SLP_S3#19,29,36,37,47

KBC_BEEP29

H_PECI5,22

FAN_TACH128

PCH_SUSCLK_KBC19

E51_RxD65E51_TxD65

ME_UNLOCK21

STDBY_LED68

PWRLED68L_BKLT_EN 17

AC_IN# 40

RTCRST_ON21

MODEL_ID_R 49

WLAN_PWR_EN# 65

WLAN_WAKE#65

LAN_WAKE#31

3D3V_SRC_EN41

3D3V_SRC_EN41

AP_DET# 65

LAN_PWR_EN31

KB_BL_PWM69

KB_BL_DET69

WLAN_PERST#65

Title


Date: Sheet of


Petra Uma -1

KBC NPCE885Custom

27 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1

KBC NPCE885Custom

27 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1

KBC NPCE885Custom

27 103Tuesday, July 10, 2012

<Core Design>

Reserved

1.3VReserved 100.0K

ADT_TYPE A/D(PIN99) PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE

N/A65W

90W

3.3V

0V

30W

100.0K

0.3V

40W

100.0K

20.0K

10.0K

47.0K

64.9K

0.55V

120W 0.82V33.0K

1.06V

100.0K

N/A

-2

47.0K

1.65V-3

64.9K

76.8

SSID = KBC

100K

PCB VERSION A/D(PIN98) PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE

100.0KSA

SB

3.0V

2.75V

PSL Function

SC

100.0K

2.48V

-1

100.0K

100.0K

100.0K

100.0K

100.0K

10.0K

2.24V

-1M

20.0K

2.0V

33.0K

1.87V

100.0K

100.0K

100.0K

-3M

-1M For PCH B3

100.0K

100.0K

143.0K

174.0K

1.358V

1.204V

64.17435.6DL

-4 100.0K 215.0K 1.047V

FAE suggest

PSL

AC_IN# KBC_PWRBTN# EC_ENABLE#

DISCRETE# will change to internal pull up

-1_20120221

-1_20120221

-1_20120223

12


12 3

4RN2709

SRN10KJ-L-GP

RN2709

SRN10KJ-L-GP

12

C2707

SC

D1U

10V2K

X-L1-G

PC

2707S

CD

1U10V

2KX

-L1-GP

12


12

R2708

100KR

2F-L1-GP

90W

R2708

100KR

2F-L1-GP

90W

1 2R2774

10KR2J-L-GPDY

R2774

10KR2J-L-GPDY

1 2R27030R2J-L-GP R27030R2J-L-GP

1 2R27060R0402-PADR27060R0402-PAD

KBSOUT0/GPOB0/JENK# 53

KBSOUT1/GPIOB1/TCK 52

KBSOUT2/GPIOB2/TMS 51

KBSOUT3/GPIOB3/TDI 50

KBSOUT4/GPOB4/JEN0# 49

KBSOUT5/GPIOB5/TDO 48

KBSOUT6/GPIOB6/RDY# 47

KBSOUT7/GPIOB7 43

KBSOUT8/GPIOC0 42

KBSOUT9/GPOC1/SDP_VIS# 41

KBSOUT10&P80_CLK/GPIOC2 40

KBSOUT11&P80_DAT/GPIOC3 39

KBSOUT12/GPIO64 38

KBSOUT13/GPIO63 37

KBSOUT14/GPIO62 36

KBSOUT15/GPIO61/XOR_OUT 35

GPIO60/KBSOUT16 34

GPIO57/KBSOUT17 33

KBSIN0/GPIOA0/N2TCK 54

KBSIN1/GPIOA1/N2TMS 55

KBSIN2/GPIOA2 56

KBSIN3/GPIOA3 57

KBSIN4/GPIOA4 58

KBSIN5/GPIOA5 59

KBSIN6/GPIOA6 60

KBSIN7/GPIOA7 61

GPIO56/TA131

GPIO14/TB163

GPIO1/TB264

GPIO15/A_PWM32

GPIO21/B_PWM118

GPIO13/C_PWM62

GPIO32/D_PWM65

GPIO66/G_PWM81

GPIO33/H_PWM66

GPIO45/E_PWM22

GPIO40/F_PWM16

VCC_POR#85

GPIO0/EXTCLK77

PECI13

VTT12

GPIO87/CIRRXM/SIN_CR113GPIO46/CIRRXM/TRIST#23

GP/I/O83/SOUT_CR/TRIST#111

GPIO55/CLKOUT/IOX_DIN_DIO30

2 0F 2U2701B

NPCE885PA0DX-GP

2 0F 2U2701B

NPCE885PA0DX-GP

12 R2775100KR2J-4-GPR2775100KR2J-4-GP

21

G2701GAP-OPEN

G2701GAP-OPEN

12

R278210KR2J-L-GP

DY R278210KR2J-L-GP

DY

12 3

4RN2705

SRN10KJ-L-GP

RN2705

SRN10KJ-L-GP

12

C2736

SC

20P50V

2JN-1G

PC

2736S

C20P

50V2JN

-1GP

G

S

D

Q27022N7002K-2-GP84.2N702.J312ND = 84.2N702.031

Q27022N7002K-2-GP84.2N702.J312ND = 84.2N702.031

12

C2 704

SC

D1U

10V2K

X-L1-G

PC

2 704S

CD

1U10V

2KX

-L1-GP

1 2R271543R2J-GP

R271543R2J-GP

12

R2726100KR2F-L1-GPR2726100KR2F-L1-GP

12


1 2R27330R0402-PAD

R27330R0402-PAD

12

R271010KR2J-L-GP

DY

R271010KR2J-L-GP

DY

VC

C1

19

VC

C2

46

VC

C3

76

VC

C4

88

VC

C5

11

5

AV

CC

10

2

VD

D4

GN

D1

18

GN

D2

45

GN

D3

78

GN

D4

89

GN

D5

11

6

GN

D6

5

AG

ND

10

3

GPIO11/CLKRUN# 8

LAD3/GPIOF4 1

LAD2/GPIOF3 128

LAD1/GPIOF2 127

LAD0/GPIOF1 126

LFRAME#/GPIOF6 3LCLK/GPIOF5 2

LRESET#/GPIOF7 7

SERIRQ/GPIOF0 125

GPIO85/GA20 121

KBRST#/GPIO86 122

ECSCI#/GPIO54 29GPIO65/SMI# 9

GPIO10/LPCPD# 124

GPIO67N2TMS123

GPIO17/SCL1/N2TCK 70

GPIO73/SCL2 67

GPIO23/SCL3 119

GPIO22/SDA1/N2TMS 69

GPIO74/SDA2 68

GPIO31/SDA3 120

F_SDI&F_SDIO186

F_SDIO&F_SDIO087

F_SCK92F_CS0#90

VREF104

GPIO90/AD097

GPIO91/AD198

GPIO92/AD299

GPIO93/AD3100

GPIO94/DA0101

GPIO95/DA1105

GPIO96/DA2106

GPIO37/PSCLK1 72

GPIO26/PSCLK2 10

GPIO35/PSDAT1 71

GPIO27/PSDAT2 11GPIO246

GPIO42/TCK17

GPIO43/TMS20

GPIO44/TDI21

GPIO34/CIRRXL14

GPIO47/SCL4 24

GPIO50/PSCLK3/TDO 25GPIO52/PSDAT3/RDY# 27

GPIO53/SDA4 28

PSL_IN1_GPI70# 73

PSL_OUT_GPIO71# 74

VS

BY

75

GPIO41/F_WP#80

GPIO7582

GPIO7683

GPIO7784

GPIO81/F_WP#91PSL_IN2_GPI06# 93

GPIO7/AD794GPIO3/AD695GPIO4/AD596

GPIO97/DA3107

GPIO5/AD4108

GPIO30/F_WP#109

GPO82/IOX_LDSH/TEST#110GP/I/O84/IOX_SCLK/XORTR#112

VB

KU

P1

14

VCORF 44

GPIO0279

GPIO20/TA2/IOX_DIN_DIO117

GPIO3615

GPIO51/N2TCK26

1 0F 2U2701A

NPCE885PA0DX-GP

71.00885.A0G

1 0F 2U2701A

NPCE885PA0DX-GP

71.00885.A0G

12


12

R2707

100KR

2F-L1-GP

65W

R2707

100KR

2F-L1-GP

65W

12

R2773

100KR2J-4-GP

R2773

100KR2J-4-GP

12

R2732100KR2J-4-GPR2732100KR2J-4-GP

1 2R270133R2J-L1-GP R270133R2J-L1-GP

12

C2710

SC

D1U

10V2K

X-L1-G

PC

2710S

CD

1U10V

2KX

-L1-GP

12 3

4


12

C2711

SC

2D2U

10V3K

X-L-G

P

DY

C2711

SC

2D2U

10V3K

X-L-G

P

DY

12

R2727100KR2F-L1-GPR2727100KR2F-L1-GP

12


DY


DY

12

C2 702

SC

2D2U

10V3K

X-L-G

P

DY

C2 702

SC

2D2U

10V3K

X-L-G

P

DY

12

C2708

SC

2D2U

10V3K

X-L-G

P

DY

C2708

SC

2D2U

10V3K

X-L-G

P

DY

12

R2713330KR2J-L1-GPR2713330KR2J-L1-GP

12

R277647KR2F-GPR277647KR2F-GP

1 2R2758

0R2J-L-GP

DY R2758

0R2J-L-GP

DY

1 2R27590R0402-PADR27590R0402-PAD

12

R270910KR2J-L-GP

DY

R270910KR2J-L-GP

DY

C

B

E

Q2701MMBT3906-4-GP

2nd = 84.03906.F1184.T3906.A11

Q2701MMBT3906-4-GP

2nd = 84.03906.F1184.T3906.A11

1 2R27701KR2J-L2-GPR27701KR2J-L2-GP

12 3

4


12


DY


DY

12


12

C2709

SC

D1U

10V2K

X-L1-G

P

DY

C2709

SC

D1U

10V2K

X-L1-G

P

DY

12


1 2R270233R2J-L1-GP R270233R2J-L1-GP

1 2

R2717

40K2R2F-GP

R2717

40K2R2F-GP

12


1 2R27050R0402-PADR27050R0402-PAD

12

R2711100KR2F-L1-GPR2711100KR2F-L1-GP

1 2R2772

0R2J-L-GP

Non-10mWR2772

0R2J-L-GP

Non-10mW

12

C2717SC220P50V2KX-3GPDYC2717SC220P50V2KX-3GPDY

12

C2 703

SC

D1U

10V2K

X-L1-G

P

DY

C2 703

SC

D1U

10V2K

X-L1-G

P

DY

12

C2713SC1U10V3KX-L1-GPC2713SC1U10V3KX-L1-GP

12 3

4RN2708

SRN10KJ-L-GP

RN2708

SRN10KJ-L-GP

12

R271230KR2F-GP

DY

R271230KR2F-GP

DY

12

C2 705

SC

D1U

10V2K

X-L1-G

PC

2 705S

CD

1U10V

2KX

-L1-GP

1 2R270433R2J-L1-GP R270433R2J-L1-GP

12 R2757470R2J-2-GPR2757470R2J-2-GP

12

C2706

SC

D1U

10V2K

X-L1-G

PC

2706S

CD

1U10V

2KX

-L1-GP

G

D S

Q2703DMP2305U-7-GP

10mW

Q2703DMP2305U-7-GP

10mW

WWW.MANUALS.CLAN.SU

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

FAN_TACH1_C

FAN1_PWM_RP2800_DXP

THERM_SYS_SHDN#P2800_DXN

FAN_TACH1_C

IMVP_PWRGD_R

THERM_SYS_SHDN#

ALERT#

NCT_CLKNCT_DATA

ALERT#

NCT_DATA

NCT_CLK

5V_S0

3D3V_S0

3D3V_S0

3D3V_S0

5V_S0

3D3V_S0

3D3V_S0

3D3V_S0

FAN1_PWM27

FAN_TACH127

PURE_HW_SHUTDOWN#27,36

IMVP_PWRGD 36,42

SML1_DATA 20,27,49

SML1_CLK 20,27,49

Title


Date: Sheet of


Petra Uma -1

Thermal 7718/Fan Controllor P2793Custom

28 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1


28 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1


28 103Tuesday, July 10, 2012

<Core Design>

SSID = Thermal

Thermal sensor NCT 7718W

Layout notice :Both DXN and DXP routing 10 miltrace width and 10 mil spacing.

1.H/W T8 Shutdown2.System Sensor, Put on palm rest

*Layout* 15 mil

R7

R5

SB T8=85 degree

1 2R28030R2J-L-GP DY

R28030R2J-L-GP DY

G

S

D

Q28022N7002K-2-GP84.2N702.J312ND = 84.2N702.031

Q28022N7002K-2-GP84.2N702.J312ND = 84.2N702.031

21

D2801CH551H-30PT-GP

2ND = 83.R5003.H8H3rd = 83.5R003.08F

83.R5003.C8F

D2801CH551H-30PT-GP

2ND = 83.R5003.H8H3rd = 83.5R003.08F

83.R5003.C8F

12

R28092KR2F-3-GPR28092KR2F-3-GP

432

15

6

FAN1

ACES-CON4-29-GP

20.F1639.0042nd = 20.F1804.0043rd = 20.F1352.004

FAN1

ACES-CON4-29-GP

20.F1639.0042nd = 20.F1804.0043rd = 20.F1352.004

12

R2808NTC-100K-8-GPDYR2808NTC-100K-8-GPDY

1 2R28110R0402-PADR28110R0402-PAD

12

C2811

SC

D1U

10V2K

X-L1-G

P

DYC

2811S

CD

1U10V

2KX

-L1-GP

DY

1 234


3

1

2

Q2801PMBS3904-1-GP84.03904.L062nd = 84.03904.T11

Q2801PMBS3904-1-GP84.03904.L062nd = 84.03904.T11

1

2

3 4

5

6



1 2R28060R0402-PADR28060R0402-PAD

12

C2808

SC

D1U

10V2K

X-L1-G

PC

2808S

CD

1U10V

2KX

-L1-GP

1 2R28020R2J-L-GP DY

R28020R2J-L-GP DY

VDD1

D+2

D-3

T_CRIT#4 GND 5ALERT# 6

SDA 7SCL 8

U2801

NCT7718W-GP

U2801

NCT7718W-GP

12

C2807

SC

2200P50V

2KX

-2GP

C2807

SC

2200P50V

2KX

-2GP

12

C2809

SC

4D7U

10V3K

X-G

PC

2809S

C4D

7U10V

3KX

-GP

12


1 2R28100R2J-L-GP

DY R28100R2J-L-GP

DY

21

D2802CH551H-30PT-GP

2ND = 83.R5003.H8H3rd = 83.5R003.08F

83.R5003.C8F

D2802CH551H-30PT-GP

2ND = 83.R5003.H8H3rd = 83.5R003.08F

83.R5003.C8F

12

R281318K7R2D-GPR281318K7R2D-GP

12

C2806SC470P50V3JN-2GPDY

C2806SC470P50V3JN-2GPDY

12

R281210KR2J-L-GP

DY

R281210KR2J-L-GP

DY

WWW.MANUALS.CLAN.SU

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

COMBO_MIC_RINT_MIC1_R

ALC268_SENSE_A

AUDIO_PC_BEEPSPKR_SB_1KBC_BEEP_1AUDIO_BEEP

MIC1-R_PORT-B

MIC2-R_PORT-B

AU

D_C

BN

AU

DIO

_PC

_BE

EP

HP

_OU

T_R

_AU

D

AU

D_3V

D_R

EAPD

HP

_OU

T_L

_AU

D

MIC

2V

MIC1-L_PORT-B

MIC2-L_PORT-B

AC

97_DA

TIN

VR

EF

JDR

EF

LDO

_CA

P_A

UD

IO

AU

D_C

BP

AUD_MIC_L

CP

VE

E

AUD_MIC_R

AC

Z_B

ITC

LK_A

UD

IO_+

COMBO_MIC_JD#

MIC2V

MIC2V

ALC268_SENSE_B

LIN2-R_PORT-BLIN2-L_PORT-B

PD#

HD

A_C

OD

EC

_SD

OU

T

HD

A_C

OD

EC

_BIT

CLK

COMBO_MIC_JD#

COMBO_MIC_Q

INT_MIC_L_R

COMBO_MIC

EAPD

PD#

AUD_AGND

5V_S0

AUD_AGND

AUD_AGND

3D3V_S0

5VA_S0

AUD_AGND

5V_S0

3D3V_S0

AUD_AGND

AUD_AGND

AUD_AGND

AUD_AGND

AUD_AGND

3D3V_S0

1D5V_S0

5V_S0

5VA_S0AUD_AGND

AUD_AGND

5V_S5

5VA_S05V_S0

AUD_AGND

5V_S5

3D3V_S5

INT_MIC_L_R 49

AUD_HP1_JD# 58

HDA_CODEC_BITCLK21

AUD_SPK_L+_R58

KBC_BEEP 27HDA_SPKR 21

AUD_SPK_R+_R58

HDA_CODEC_RST# 21

HDA_CODEC_SYNC 21

AUD_SPK_R-_R58

HDA_CODEC_SDOUT21

HDA_SDIN021

AUD_SPK_L-_R58 COMBO_MIC 58

AMP_MUTE# 27

KBC_PWRBTN# 27,68,82

PM_SLP_S3# 19,27,36,37,47

AUD_HP1_JACK_R258AUD_HP1_JACK_L258

PM_SLP_S3#19,27,36,37,47

HDA_CODEC_RST# 21

Title


Date: Sheet of


Petra Uma -1

Audio Codec 271XCustom

29 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1


29 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1


29 103Tuesday, July 10, 2012

<Core Design>

CLOSE TO PIN18

CLOSE TO PIN35

CLOSE TO PIN34

CLOSE TO PIN19

CLOSE TO PIN39 and 46

ANALOG

DIGITAL(include thermal pad) Spilt by DGND

CLOSE TO PIN38

Due to layout concern,change to DGND

281

271

EN1

GND2

VIN3 VOUT 4

NC#5 5

U2902

G9090-475T12U-GP74.09090.F3F

DY

2nd = 74.70247.03F

U2902

G9090-475T12U-GP74.09090.F3F

DY

2nd = 74.70247.03F1

2

C2 904

SC

D1U

10V2K

X-L1-G

PC

2 904S

CD

1U10V

2KX

-L1-GP

1 2R291922K1R2F-L-GPR291922K1R2F-L-GP

12 3

4


12


1 2C2916SCD1U10V2KX-L1-GP


12

R290920KR2F-L-GPR290920KR2F-L-GP

12

FC

2901S

CD

1U10V

2KX

-L1-GP

DY

FC

2901S

CD

1U10V

2KX

-L1-GP

DY

1 2R29020R2J-L-GP

DY

R29020R2J-L-GP

DY

12

C2930SC10U6D3V3MX-L-GPC2930SC10U6D3V3MX-L-GP

1 2R292020KR2F-L-GP

R292020KR2F-L-GP

12

R29104K7R2J-L-GPDY

R29104K7R2J-L-GPDY

1 2C2925 SC1U16V3KX-5GPC2925 SC1U16V3KX-5GP

12

C2935SC1U10V2KX-1GP

DY

C2935SC1U10V2KX-1GP

DY

12

R29172K2R2J-2-GPR29172K2R2J-2-GP

1 2R2907 39K2R2F-L-GPR2907 39K2R2F-L-GP

12

C2926TVL-0402-01-AB1-GPC2926TVL-0402-01-AB1-GP

12 R292610KR2J-L-GP

R292610KR2J-L-GP

12

C2906

SC

10U10V

3MX

-GP

C2906

SC

10U10V

3MX

-GP

12

C2934SC10U25V5KX-GPC2934SC10U25V5KX-GP

1 2R291433R2J-L1-GP

R291433R2J-L1-GP

1 2R29080R2J-L-GP

DY

R29080R2J-L-GP

DY

12

R292722K1R2F-L-GPR292722K1R2F-L-GP

1 2C2917 SC2D2U10V3KX-L-GP

DY

C2917 SC2D2U10V3KX-L-GP

DY

1 2

G2903

GAP-CLOSE

G2903

GAP-CLOSE

1 2C2918 SC2D2U10V3KX-L-GP

DY

C2918 SC2D2U10V3KX-L-GP

DY

12 C2912SC2D2U10V3KX-L-GPC2912SC2D2U10V3KX-L-GP

12

C2907

SC

D1U

10V2K

X-L1-G

PC

2907S

CD

1U10V

2KX

-L1-GP

12

C2910

SC

D1U

10V2K

X-L1-G

PC

2910S

CD

1U10V

2KX

-L1-GP

12 R29030R2J-L-GP

DYR29030R2J-L-GP

DY

12

EC2901SCD1U16V2KX-3GPDY

EC2901SCD1U16V2KX-3GPDY

12

FC

2902S

CD

1U10V

2KX

-L1-GP

DY

FC

2902S

CD

1U10V

2KX

-L1-GP

DY

1

2

3

D2902BAW56-5-GP83.00056.Q112nd = 83.00056.K11

D2902BAW56-5-GP83.00056.Q112nd = 83.00056.K11

1 2R29040R0402-PADR29040R0402-PAD

12

C2922

SC

100P50V

2JN-L-G

PC

2922S

C100P

50V2JN

-L-GP

12

R29064K7R2J-L-GPR29064K7R2J-L-GP

G

D

S

Q2901BSS138-8-GP84.00138.H312nd = 84.05067.031

Q2901BSS138-8-GP84.00138.H312nd = 84.05067.031

1 2C2914

SC10U6D3V5KX-1GPC2914

SC10U6D3V5KX-1GP1

2

C2927SC1U10V3KX-L1-GP


1 2R29220R3J-4-GPR29220R3J-4-GP

12

C2909SC22P50V2JN-4GPDYC2909SC22P50V2JN-4GPDY

1234 5

678


1 2C2919 SC2D2U10V3KX-L-GPC2919 SC2D2U10V3KX-L-GP

1 2

G2901

GAP-CLOSE

G2901

GAP-CLOSE

2 1

3

D2903AZ2025-02S-GP83.02025.0A1

D2903AZ2025-02S-GP83.02025.0A1

AVDD238PVDD139SPK-OUT-L+40SPK-OUT-L-41PVSS142PVSS243SPK-OUT-R-44SPK-OUT-R+45PVDD246EAPD47SPDIFO48GND49

DV

DD

1

GP

IO0/

DM

IC-D

AT

A2

GP

IO1/

DM

IC-C

LK3

PD

#4

SD

AT

A-O

UT

5

BC

LK6

DV

SS

7

SD

AT

A-IN

8

DV

DD

-IO9

SY

NC

10

RE

SE

T#

11

PC

BE

EP

12SENSE_A 13

LINE1-R/PORT-C-R 24LINE1-L/PORT-C-L 23MIC1-R/PORT-B-R 22MIC1-L/PORT-B-L 21

MONO-OUT 20JDREF 19

SENSE_B 18MIC2-R/PORT-F-R 17MIC2-L/PORT-F-L 16

LINE2-R/PORT-E-R 15LINE2-L/PORT-E-L 14

AVSS237

CB

P36

CB

N35

CP

VE

E34

HP

OU

T-R

/PO

RT

-I-R

33

HP

OU

T-L

/PO

RT

-I-L

32

MIC

1-V

RE

FO

-L31

MIC

1-V

RE

FO

-R30

MIC

2-V

RE

FO

29

LDO

-CA

P28

VR

EF

27

AV

SS

126

AV

DD

125

U2901

ALC271X-VB6-CG-GP

71.00271.B03

U2901

ALC271X-VB6-CG-GP

71.00271.B03

1 2C2920 SC2D2U10V3KX-L-GPC2920 SC2D2U10V3KX-L-GP

123

4

RN2901SRN47K-2-GP-URN2901SRN47K-2-GP-U

1 2C2924 SC1U16V3KX-5GPC2924 SC1U16V3KX-5GP

12

C2901SC1000P50V3JN-GP-UC2901SC1000P50V3JN-GP-U

1 2R29050R0402-PADR29050R0402-PAD

1

2

3

D2901BAW56-5-GP83.00056.Q112nd = 83.00056.K11

D2901BAW56-5-GP83.00056.Q112nd = 83.00056.K11

2

1

3

D2906

AZ2025-02S-GP

83.02025.0A1

D2906

AZ2025-02S-GP

83.02025.0A1

2 1

3

D2905AZ2025-02S-GP83.02025.0A1

D2905AZ2025-02S-GP83.02025.0A1

1 2R29250R2J-L-GPR29250R2J-L-GP

12

C2911SC2D2U10V3KX-L-GPC2911SC2D2U10V3KX-L-GP

12

C2 903

SC

10U6D

3V3M

X-L-G

PC

2 903S

C10U

6D3V

3MX

-L-GP

1 2R291522R2J-2-GP

R291522R2J-2-GP

12C2921SC1U6D3V2KX-L-1-GPC2921SC1U6D3V2KX-L-1-GP

1 2R2923

0R0603-PAD

R2923

0R0603-PAD

WWW.MANUALS.CLAN.SU

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of


Petra Uma -1

Audio AMPA4


<Core Design>

Title


Date: Sheet of


Petra Uma -1

Audio AMPA4


<Core Design>

Title


Date: Sheet of


Petra Uma -1

Audio AMPA4


<Core Design>

(Blanking)

WWW.MANUALS.CLAN.SU

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A APCIE_TXN3

PCIE_RXP3SD_CD#

SP8

SD_WP

RSET

PC

IE_R

XP

3

VD

D33

VD

D33

CARD_3V3

VDD10

VDD33

VDD10

VDD33

ENSWREG

RS

ET

PCIE_CLK_LAN_REQ#

VDD10LAN_WAKE#_R

ISOLATEBPLT_RST#

VDD33

SDA

REGOUT

VDD33VDD33

SD_WP

SD

_CD

#

PC

IE_R

XP

3_C

PC

IE_R

XN

3_C

10M

/100

M/1

G_L

ED

#

VD

D10

LAN

_AC

T_L

ED

#

VD

D33

/18

VD

D10

EV

DD

10

SP

5

SP

10S

P9

SP

8S

P7

SP

6

XT

AL1

VD

D33

XT

AL2

PC

IE_T

XN

3P

CIE

_TX

P3

PC

IE_C

LK_L

AN

PC

IE_C

LK_L

AN

#

PC

IE_R

XN

3

SP9SP6

10M/100M/1G_LED#

SDA

XTAL2

XTAL1

ISOLATEB

SP10SP5

VDD33

ENSWREG

ENSWREG

SP7

REGOUT VDD10

EVDD10

SP9

SP8

SP7

SP10

SP5

SP6

VDD33/18

PCIE_RXN3

10M/100M/1G_LED#

LAN_ACT_LED#

PLT_RST#

PCIE_CLK_LAN_REQ#

PCIE_CLK_LAN

PCIE_CLK_LAN#

LAN_WAKE#

PCIE_TXP3

LAN_WAKE#_R

3D3V_S5

VDD33

CARD_3V3

VDD33 3D3V_S0

3D3V_SRC

VDD33

SD_DATA3 74

SD_DATA1 74

SD_DATA2 74

SD_WP 74

SD_CLK 74

SD_CMD 74

MDI0+59MDI0-59

MDI1+59MDI1-59MDI2+59MDI2-59

MDI3+59MDI3-59

SD_DATA0 74

SD_CD# 74

LAN_WAKE# 27

PCIE_CLK_LAN 20

PCIE_CLK_LAN# 20

PCIE_CLK_LAN_REQ# 20

PLT_RST# 5,18,27,36,65,71,97

LAN_ACT_LED# 59

10M/100M/1G_LED# 59

PCIE_TXP3 20

PCIE_TXN3 20

PCIE_RXP3 20

PCIE_RXN3 20

LAN_PWR_EN27

Title


Date: Sheet of


Husk/Petra -1

LAN(RTL8411)Custom

31 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Husk/Petra -1

LAN(RTL8411)Custom

31 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Husk/Petra -1

LAN(RTL8411)Custom

31 103Tuesday, July 10, 2012

<Core Design>

close the Pin 18~pin 23

LDO

SWR

the Caps close to VDD33 pin

the Caps close to pin33

LDO

SWR

-1_20120302A

12

R31101K54R2F-GPDY

R31101K54R2F-GPDY

12

C3115

SC

D1U

10V2K

X-L-G

PC

3115S

CD

1U10V

2KX

-L-GP

12 R31160R2J-L-GPR31160R2J-L-GP

12

C3116

SC

D1U

10V2K

X-L-G

PC

3116S

CD

1U10V

2KX

-L-GP

12C3125 SC12P50V2JN-3GPC3125 SC12P50V2JN-3GP

12

C3135

SC

4D7U

6D3V

3KX

-L-GP

DY

C3135

SC

4D7U

6D3V

3KX

-L-GP

DY

12

R310910KR2J-L-GP

DY

R310910KR2J-L-GP

DY

12

C3129

SC

5P50V

2CN

-2GP

DY

C3129

SC

5P50V

2CN

-2GP

DY

12

R31061MR2J-1-GPDYR31061MR2J-1-GPDY

12 R31030R2J-L-GPR31030R2J-L-GP

12

R31172K49R2F-GPR31172K49R2F-GP

12

C3101

SC

D1U

10V2K

X-L-G

PC

3101S

CD

1U10V

2KX

-L-GP

12

C3117

SC

D1U

10V2K

X-L-G

PC

3117S

CD

1U10V

2KX

-L-GP

12

C3123

SC

D1U

10V2K

X-L-G

PC

3123S

CD

1U10V

2KX

-L-GP

12

C3127

SC

1U6D

3V2K

X-L-1-G

PC

3127S

C1U

6D3V

2KX

-L-1-GP

12

C3118

SC

D1U

10V2K

X-L-G

PC

3118S

CD

1U10V

2KX

-L-GP

12

C3122

SC

D1U

10V2K

X-L-G

PC

3122S

CD

1U10V

2KX

-L-GP

12

C3130

SC

5P50V

2CN

-2GP

DY

C3130

SC

5P50V

2CN

-2GP

DY

12 R31040R2J-L-GPR31040R2J-L-GP

12

C3102

SC

D1U

10V2K

X-L-G

P

DY

C3102

SC

D1U

10V2K

X-L-G

P

DY

12

C3119

SC

D1U

10V2K

X-L-G

PC

3119S

CD

1U10V

2KX

-L-GP

12

R311910KR

2J-L-GP

LAN_IOACR311910K

R2J-L-G

P

LAN_IOAC

12 R31120R2J-L-GPR31120R2J-L-GP

OUT 1GND 2OC# 3EN/EN#4

IN5

U3102

SY6288CAAC-GP

74.06288.07FLAN_IOACU3102

SY6288CAAC-GP

74.06288.07FLAN_IOAC 12 R3105

0R2J-L-GPR31050R2J-L-GP

12

C3103

SC

D1U

10V2K

X-L-G

PC

3103S

CD

1U10V

2KX

-L-GP

1 2L3101

IND-4D7UH-192-GPDY

L3101

IND-4D7UH-192-GPDY

12

C3136SC

4D7U

6D3V

3KX

-L-GP

LAN_IOAC

C3136SC

4D7U

6D3V

3KX

-L-GP

LAN_IOAC

12

C3134

SC

4D7U

6D3V

3KX

-L-GP

DY

C3134

SC

4D7U

6D3V

3KX

-L-GP

DY

12

C3 110

SC

D1U

10V2K

X-L-G

PC

3 110S

CD

1U10V

2KX

-L-GP

12R3101

0R5J-5-GPNon_LAN_IOAC

R3101

0R5J-5-GPNon_LAN_IOAC

12

C3120

SC

D1U

10V2K

X-L-G

PC

3120S

CD

1U10V

2KX

-L-GP

12

C3131

SC

5P50V

2CN

-2GP

DY

C3131

SC

5P50V

2CN

-2GP

DY

MDIP01

MDIN02

AVDD103

MDIP14

MDIN15

MDIP26

MDIN27

AVDD108

MDIP39

MDIN310

AVDD3311

DVDD3312

CARD_3V313

SD_D7/XD_RDY14

SD_D6/MS_INS#/XD_RE#15

SD_D5/XD_CE#16

REGOUT 48

VDDREG 47

VDDREG 46

ENSWREG_H 45

SDA 44

LED3 43

SCL/LED_CR 42

DVDD10 41

LANWAKE# 40

DVDD33 39

ISOLATE# 38

PERST# 37

CLKREQ# 36

SD_WP/MS_D1/XD_WP# 35

MS_BS/XD_CLE 34

VDD33/18 33

SD

_D4/

XD

_WE

#17

SD

_D1/

MS

_CLK

/XD

_D6

18

SD

_D0/

MS

_D7/

XD

_D5

19

SD

_CLK

/MS

_D3/

XD

_D4

20

SD

_CM

D/M

S_D

6/X

D_D

321

SD

_D3/

MS

_D2/

XD

_D2

22

SD

_D2/

XD

_D7

23

GN

D24

HS

IP25

HS

IN26

RE

FC

LK_P

27

RE

FC

LK_N

28

EV

DD

1029

HS

OP

30

HS

ON

31

GN

D32

AV

DD

3364

AV

DD

3363

RS

ET

62

AV

DD

1061

CK

XT

AL2

60

CK

XT

AL1

59

AV

DD

3358

XD

_CD

#57

MS

_D0/

XD

_D1

56

MS

_D4/

XD

_D0

55

SD

_CD

#/M

S_D

5/X

D_A

LE54

VD

D33

/18

53

DV

DD

1052

LED

051

GP

O50

LED

149

GND65U3101

RTL8411AA-CG-GP71.08411.A03

U3101

RTL8411AA-CG-GP71.08411.A03

12 R31130R2J-L-GPR31130R2J-L-GP

12

C3113

SC

4D7U

6D3V

3KX

-L-GP

DY

C3113

SC

4D7U

6D3V

3KX

-L-GP

DY12

C3108

SC

D1U

10V2K

X-L-G

P

DY

C3108

SC

D1U

10V2K

X-L-G

P

DY

12 R31110R2J-L-GPR31110R2J-L-GP

12

X3101XTAL-25MHZ-102-GP82.30020.8512nd = 82.30020.791

X3101XTAL-25MHZ-102-GP82.30020.8512nd = 82.30020.791

12

C3124

SC

D1U

10V2K

X-L-G

PC

3124S

CD

1U10V

2KX

-L-GP

12 R31140R2J-L-GPR31140R2J-L-GP

12

C3109

SC

4D7U

6D3V

3KX

-L-GP

DY

C3109

SC

4D7U

6D3V

3KX

-L-GP

DY

12 R3120

0R2J-L-GP

R3120

0R2J-L-GP

12

C3132

SC

5P50V

2CN

-2GP

DY

C3132

SC

5P50V

2CN

-2GP

DY

12

R310815K4R2F-GPDYR310815K4R2F-GPDY

12 R31020R2J-L-GP

DYR31020R2J-L-GP

DY

12

C3105

SC

D1U

10V2K

X-L-G

PC

3105S

CD

1U10V

2KX

-L-GP

12

C3121

SC

D1U

10V2K

X-L-G

PC

3121S

CD

1U10V

2KX

-L-GP

12

C3 111

SC

4D7U

6D3V

3KX

-L-GP

DY

C3 111

SC

4D7U

6D3V

3KX

-L-GP

DY

12

C3128

SC

5P50V

2CN

-2GP

DY

C3128

SC

5P50V

2CN

-2GP

DY

12 R31150R2J-L-GPR31150R2J-L-GP

12C3126 SC15P50V2JN-2-GPC3126 SC15P50V2JN-2-GP

12

R31071KR2J-L2-GPR31071KR2J-L2-GP

12

C3104

SC

D1U

10V2K

X-L-G

P

DY

C3104

SC

D1U

10V2K

X-L-G

P

DY

12

C3133

SC

5P50V

2CN

-2GP

DY

C3133

SC

5P50V

2CN

-2GP

DY

12

C3107

SC

D1U

10V2K

X-L-G

PC

3107S

CD

1U10V

2KX

-L-GP

12

C3106

SC

D1U

10V2K

X-L-G

P

DY

C3106

SC

D1U

10V2K

X-L-G

P

DY

12 R31180R2J-L-GPR31180R2J-L-GP

12

C3114

SC

D1U

10V2K

X-L-G

P

DY

C3114

SC

D1U

10V2K

X-L-G

P

DY

WWW.MANUALS.CLAN.SU

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of


Petra Uma -1

RTS5159 (CARD READER)A4


<Core Design>

Title


Date: Sheet of


Petra Uma -1



<Core Design>

Title


Date: Sheet of


Petra Uma -1



<Core Design>

(Blanking)

WWW.MANUALS.CLAN.SU

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

Title


Date: Sheet of


Petra Uma -1

ReservedA4


<Core Design>

Title


Date: Sheet of


Petra Uma -1

ReservedA4


<Core Design>

Title


Date: Sheet of


Petra Uma -1

ReservedA4


<Core Design>

(Blanking)

WWW.MANUALS.CLAN.SU

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of


Petra Uma -1

ReservedA4


<Core Design>

Title


Date: Sheet of


Petra Uma -1

ReservedA4


<Core Design>

Title


Date: Sheet of


Petra Uma -1

ReservedA4


<Core Design>

(Blanking)

WWW.MANUALS.CLAN.SU

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of


Petra Uma -1

USB 3.0 ControllerA4


<Core Design>

Title


Date: Sheet of


Petra Uma -1



<Core Design>

Title


Date: Sheet of


Petra Uma -1



<Core Design>

(Blanking)

WWW.MANUALS.CLAN.SU

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

H_PWRGD_R

RU

N_E

NA

BLE

_R

3D3V_S5_EN5V_S5_EN

RUN_ENABLE

1D5V_S0 1D5V_S3

3D3V_S0 3D3V_SRC

5V_S0 5V_S5

1D05V_VTT

3D3V_S5

5V_S5

5V_S03D3V_S0

RUN_ENABLE

5V_S5

3D3V_SRC

3D3V_S5

3D3V_SRC3D3V_S5

IMVP_PWRGD28,42 SYS_PWROK 19

PLT_RST#5,18,27,31,65,71,97

H_THERMTRIP# 5,22

PURE_HW_SHUTDOWN# 27,28

S5_ENABLE 27,97

5V_S5_EN41

H_CPUPWRGD5,22,97

PM_SLP_S3#19,27,29,37,47

PS_S3CNTRL 37

PM_SLP_S3#19,27,29,37,47

PM_SLP_S3#19,27,29,37,47

Title


Date: Sheet of


Petra Uma -1

Power Plane EnableA3

36 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1


36 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1


36 103Tuesday, July 10, 2012

<Core Design>

Power Sequence

ANNIE Run Power

Option for non-IOAC

-1_20120221

EC change

EC change

12

C3611SCD01U50V2KX-L-GPC3611SCD01U50V2KX-L-GP

C

B

E

Q3601MMBT2222A-3-GP84.02222.V11

Q3601MMBT2222A-3-GP84.02222.V11

1 2R36260R0402-PAD

R36260R0402-PAD

OUT 1GND 2OC# 3EN/EN#4

IN5

U3611

SY6288CAAC-GP

74.06288.07FDYU3611

SY6288CAAC-GP

74.06288.07FDY

VCC 1

GND 2

HV 3DC14DC25EN6

U3610G5938TL1U-GP74.05938.09P

U3610G5938TL1U-GP74.05938.09P

1234 5

678S

SSG D

DDD

U3604AO4468-GP84.04468.037

2nd = 84.08882.037

SSSG D

DDD

U3604AO4468-GP84.04468.037

2nd = 84.08882.037

12

C3602

SC

D1U

10V2K

X-L1-G

PC

3602S

CD

1U10V

2KX

-L1-GP

12

C3615SC10U10V3MX-GPDY

C3615SC10U10V3MX-GPDY

12

C3612SCD01U50V2KX-L-GPDYC3612SCD01U50V2KX-L-GPDY

1 2C3607SCD1U25V3KX-L-GP

DYC3607SCD1U25V3KX-L-GP

DY

1234 5

678S

SSG D

DDD

U3607AO4468-GP84.04468.037

2nd = 84.08882.037

SSSG D

DDD

U3607AO4468-GP84.04468.037

2nd = 84.08882.037

12

R3602

200KR

2J-L1-GP

DY

R3602

200KR

2J-L1-GP

DY

1

2

3

D3603BAS16-6-GP

2ND = 83.00016.F1183.00016.K11

D3603BAS16-6-GP

2ND = 83.00016.F1183.00016.K11

12

R36322K2R2J-2-GPR36322K2R2J-2-GP

1

2

3

D3601BAS16-6-GP

2ND = 83.00016.F1183.00016.K11

D3601BAS16-6-GP

2ND = 83.00016.F1183.00016.K11

1 2R36221KR2J-L2-GP

R36221KR2J-L2-GP

1 2R36140R0402-PADR36140R0402-PAD

12 R36032KR2F-3-GPR36032KR2F-3-GP

12R3628

10KR2J-L-GPDY

R3628

10KR2J-L-GPDY

12

C3614SCD22U10V2KX-1GP DY

C3614SCD22U10V2KX-1GP DY

G S

D

Q36062N7002K-2-GP

84.2N702.J312ND = 84.2N702.031

Q36062N7002K-2-GP

84.2N702.J312ND = 84.2N702.031

1 2R36011KR2J-L2-GP

DYR3601

1KR2J-L2-GP

DY

1234 5

678S

SSG D

DDD

U3605AO4468-GP84.04468.037

2nd = 84.08882.037

SSSG D

DDD

U3605AO4468-GP84.04468.037

2nd = 84.08882.037

12

C3603SCD1U16V2KX-L-GP

DY

C3603SCD1U16V2KX-L-GP

DY

1 2R3608100KR2J-4-GP

R3608100KR2J-4-GP

1 2

R3629

0R5J-5-GP

R3629

0R5J-5-GP

12 R36164K7R2J-L-GP

R36164K7R2J-L-GP

WWW.MANUALS.CLAN.SU

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

0D75V_EN_1

VDDPWRGOOD_R

PS

_S3C

NT

RL_

D

DRAMRST_CNTRL_PCH

SM_DRAMRST#_D

3D3V_S5

1D5V_S03D3V_S5

0D75V_S0

1D5V_S3

DDR_VREF_S3

1D5V_S3

VDDPWRGOOD 5

PM_DRAM_PWRGD19

PS_S3CNTRL36

DDR3_DRAMRST# 14,15


SM_DRAMRST#5

+V_SM_VREF_CNT 9

0D75V_EN 46

1D05VTT_PWRGD 45,48

PM_SLP_S3#19,27,29,36,47


PM_SLP_S3# 19,27,29,36,47

DDR_WR_VREF01_D115 M_VREF_DQ_DIMM1_C 9


M_VREF_DQ_DIMM0_C 9


DDR_WR_VREF01_B414

Title


Date: Sheet of


Petra Uma -1

ADAPTERA3

37 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1

ADAPTERA3

37 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1

ADAPTERA3

37 103Tuesday, July 10, 2012

<Core Design>

Close to CPUS3 Power Reduction Circuit SM_DRAMPWROK

Close to DIMMS3 Power Reduction Circuit SM_DRAMPWROK

Close to CPUS3 Power Reduction Circuit SM_DRAMPWROK

S3 Power Reduction CircuitSM_DRAMRST#

Close to CPUS3 Power Reduction Circuit Processor VREF_DQ Implementation

12

R3702200R2F-L-GPR3702200R2F-L-GP

1 2R3719130R2F-1-GP

R3719130R2F-1-GP

G S

D

Q37012N7002K-2-GP

84.2N702.J312ND = 84.2N702.031

Q37012N7002K-2-GP

84.2N702.J312ND = 84.2N702.031

G

D S

Q3709AO3418-GP

84.03418.031IVB

2nd = 84.03404.C31

Q3709AO3418-GP

84.03418.031IVB

2nd = 84.03404.C31

1 2R37160R2J-L-GP

DY

R37160R2J-L-GP

DY

12

R37200R2J-L-GPDYR37200R2J-L-GPDY

12

R370322R2J-2-GPR370322R2J-2-GP

12

C3702SC100P50V2JN-L-GP

DY

C3702SC100P50V2JN-L-GP

DY

1 2R37180R0402-PAD

R37180R0402-PAD

12

R3721200R2F-L-GPDYR3721200R2F-L-GPDY

1 2R37070R2J-L-GP

DY

R37070R2J-L-GP

DY 1 2R37080R2J-L-GP

DYR37080R2J-L-GP

DY

IN B1

IN A2

GND3 OUT Y 4

VCC 5

U370174VHC1G09DFT2G-GP73.01G09.AAH2nd = 73.01G09.0AB

U370174VHC1G09DFT2G-GP73.01G09.AAH2nd = 73.01G09.0AB

12

R3705100KR2J-4-GPR3705100KR2J-4-GP

12


DY


DY

G

S

D

Q37082N7002K-2-GP84.2N702.J312ND = 84.2N702.031

Q37082N7002K-2-GP84.2N702.J312ND = 84.2N702.031

12


1 2R37090R2J-L-GPDY

R37090R2J-L-GPDY

12


DYC3701SCD1U10V2KX-L1-GP

DY

12C3703SCD047U16V2KX-1-GPC3703SCD047U16V2KX-1-GP

12

R37100R0402-PADR37100R0402-PAD

1 2R37140R2J-L-GP

DYR37140R2J-L-GP

DY1

2

R3713200R2F-L-GP

R3713200R2F-L-GP

G

D S

Q3710AO3418-GP

84.03418.031IVB

2nd = 84.03404.C31

Q3710AO3418-GP

84.03418.031IVB

2nd = 84.03404.C31

G

S

D

Q37032N7002K-2-GP84.2N702.J312ND = 84.2N702.031

Q37032N7002K-2-GP84.2N702.J312ND = 84.2N702.031

1 2R37010R0402-PAD

R37010R0402-PAD

WWW.MANUALS.CLAN.SU

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

PWR_AD+_2

PWR_ADJK_ENPWR_ADJK_EN

AD_JK

AD_JK AD+

AD_OFF27

Title


Date: Sheet of


Petra Uma -1

DCIN JACKA4

38 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1

DCIN JACKA4

38 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1

DCIN JACKA4

38 103Tuesday, July 10, 2012

<Core Design>

1Pin=3A

Adaptor in to generate DCBATOUTANNIE solution

12

PR

3807200K

R2F

-L-GP

PR

3807200K

R2F

-L-GP

12

PR3808100KR2J-4-GP

PR3808100KR2J-4-GP

21

3R1

R2PQ3801LTC024EUB-FS8-GP

2ND = 84.00124.H1K3rd = 84.05124.011

84.00024.A1K

R1

R2PQ3801LTC024EUB-FS8-GP

2ND = 84.00124.H1K3rd = 84.05124.011

84.00024.A1K

EB

C

R1

R2

PQ3802PDTA124EU-1-GP84.00124.K1K2nd = 84.00024.01K3rd = 84.05124.A11

R1

R2

PQ3802PDTA124EU-1-GP84.00124.K1K2nd = 84.00024.01K3rd = 84.05124.A11

1234 5

678S

SSG D

DDD

PU3802

QM3005S-GP

SSSG D

DDD

PU3802

QM3005S-GP

12

PC3802SC1U50V5ZY-1-GPPC3802SC1U50V5ZY-1-GP

AK

D3801P6SBMJ27APT-GP

2nd = 83.P6SMB.JAG83.P6SBM.DAG

3rd = 83.P6SMB.CAG

D3801P6SBMJ27APT-GP


3rd = 83.P6SMB.CAG

12 P

C3801

SC

D1U

50V3K

X-G

PP

C3801

SC

D1U

50V3K

X-G

P

1

2345

7

NP1

NP2

6DCIN1

ACES-CON5-27-GP

20.F2182.0052nd = 20.F2198.005

DCIN1

ACES-CON5-27-GP

20.F2182.0052nd = 20.F2198.005

12

PC3805SC1U50V5ZY-1-GPPC3805SC1U50V5ZY-1-GP

WWW.MANUALS.CLAN.SU

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

BAT_IN#_1BATA_SCL_1BATA_SDA_1

BI

BAT_IN#_1

BAT_IN#_1

BI

BATA_SDA_1

BATA_SCL_1 BT+

BT+

BT+

BAT_IN#27BAT_SCL27,40BAT_SDA27,40

Title


Date: Sheet of


Petra Uma -1

BATT CONNA4

39 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1

BATT CONNA4

39 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1

BATT CONNA4

39 103Tuesday, July 10, 2012

<Core Design>

BATTERY CONNECTOR

12

PC3901SCD1U50V3KX-GPPC3901SCD1U50V3KX-GP

12

R39020R0402-PAD

R39020R0402-PAD1TP3907TPAD14-OP-GP TP3907TPAD14-OP-GP



12

34

56

78

BAT2ACES-CONN8D-GP

20.81633.008

BAT2ACES-CONN8D-GP

20.81633.008




12

PC3902SC2200P50V2KX-2GPPC3902SC2200P50V2KX-2GP


1234 5

678

PN3901SRN33J-7-GPPN3901SRN33J-7-GP

KA

PD3901MMPZ5232BPT-GP-U

83.5R603.D3F2ND = 83.5R603.K3F3rd = 83.5R603.Q3F

PD3901MMPZ5232BPT-GP-U

83.5R603.D3F2ND = 83.5R603.K3F3rd = 83.5R603.Q3F

WWW.MANUALS.CLAN.SU

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

PWR_CHG_BAT_SCL

PWR_CHG_BAT_SDA

PWR_CHG_CSOP_1

PW

R_C

HG

_AC

P

PW

R_C

HG

_AC

N

PWR_CHG_BTST

PWR_CHG_BTST_R

PWR_CHG_ACDET

PWR_CHG_ACOK

AD+_G_2

PWR_CHG_IOUT

DC

_IN_D A

D+_G

_1

BATT_SENSE_G

PWR_CHG_VCC

PWR_CHG_LODRV

PWR_CHG_PHASE

PWR_CHG_HIDRV

PWR_CHG_CMPIN

PWR_CHG_IOUT

PWR_CHG_AD_OFF

PWR_CHG_ILIM

AC_IN#

PWR_CHG_ACOK

STOP_CHG

PWR_CHG_SRP

PWR_CHG_SRN

BT+_R

STOP_CHG

PWR_CHG_BAT_SCLPWR_CHG_BAT_SCL

PWR_CHG_BAT_SDAPWR_CHG_BAT_SDA

CHG_AGND

DCBATOUT

AD+

AD+_TO_SYS

CHG_AGND

CHG_AGND

CHG_AGNDCHG_AGND

BT+

AD+

CHG_AGND

CHG_AGND

CHG_AGND

CHG_AGND

CHG_AGND

3D3V_AUX_S5

PWR_CHG_REGN

PWR_CHG_REGN

3D3V_AUX_S5

3D3V_AUX_S5

3D3V_AUX_S5

DCBATOUT

AD+

BT+

3D3V_AUX_S5

AD_IA 27

AC_IN#27

CHG_ON#27

STOP_CHG#27

BAT_SDA27,39

BAT_SCL27,39

Title


Date: Sheet of


Petra Uma -1

CHARGER BQ24707ACustom

40 108Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1


40 108Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1


40 108Tuesday, July 10, 2012

<Core Design>

Charger Current=1.4~3.6A

SSID = Charger

R1

R2

120w

90w 100K

100K

60.4k

118k

AD+ total power R1 R2

65w

80w

100K

100K

12.4K

41.2k

A8( ANNIE/ASTRO)PR4007,PR4001

74.24727.073

PL4001 change to 7*7*3

MAG. 7*7*3

DCR: 37~40mOhm

Idc : 5.5 A , Isat : 10A

PR4032 , PR4033 DY

Wayler , 12-06

Delete PC4008

Wayler , 2011-1208

Delete PR4016

PR4015 change to 10 ohm

Wayler , 2011-1208

PU4003 change to 74.24727.073

Wayler , 2011-1208

EC change

ILIM10

VCC20

GN

D14

SCL9

SDA8

ACDET6

IOUT 7ACOK#5

AC

P2

AC

N1

BTST 17

REGN 16

HIDRV 18

PHASE 19

LODRV 15

CMPIN4

SRN 12

CMPOUT3

SRP 13

GN

D21

NC#1111

PU4003

BQ24727RGRR-GP

PU4003

BQ24727RGRR-GP

12

PG4002GAP-CLOSE-PWR-3-GPPG4002GAP-CLOSE-PWR-3-GP

1 2

PR4004

D01R3721F-GP-U

PR4004

D01R3721F-GP-U

G

SD

PQ40072N7002A-7-GP

PQ40072N7002A-7-GP

12PG4008 GAP-CLOSE-PWR-3-GPPG4008 GAP-CLOSE-PWR-3-GP

12

PR4006

316KR2F-L-GP

PR4006

316KR2F-L-GP

12

PR4030100KR2J-4-GPPR4030100KR2J-4-GP

12P

G4003

GA

P-C

LOS

E-P

WR

-3-GP

PG

4003G

AP

-CLO

SE

-PW

R-3-G

P12

PC

4019

SC

D1U

25V2K

X-G

P

DY

PC

4019

SC

D1U

25V2K

X-G

P

DY

12345 6 7 8

SSSGD D D D

PU4005FD

MC

8884-GP

-U

84.08884.A372nd = 84.00412.037

SSSGD D D D

PU4005FD

MC

8884-GP

-U

84.08884.A372nd = 84.00412.037

12

PR4033

10KR2F-L1-GPDYPR4033

10KR2F-L1-GPDY

1 2

PR4017

D01R3721F-GP-U

PR4017

D01R3721F-GP-U

12PG4010 GAP-CLOSE-PWR-3-GPPG4010 GAP-CLOSE-PWR-3-GP

1 2PR40130R0402-PADPR40130R0402-PAD

K APD4003

CH520S-30PT-GP

2nd = 83.1R003.I8F 83.R0203.08F

PD4003

CH520S-30PT-GP

2nd = 83.1R003.I8F 83.R0203.08F

G

SD

PQ40062N7002A-7-GP

PQ40062N7002A-7-GP

12

PR400712K4R2F-GPPR400712K4R2F-GP

12

PC4020

SC

10U25V

5KX

-GP

PC4020

SC

10U25V

5KX

-GP

12

PR4011

470KR2J-L1-GP

PR4011

470KR2J-L1-GP

1 2

PR402510R2F-L-GPPR402510R2F-L-GP

12

PC4025

SC

4D7U

25V5K

X-G

P

PC4025

SC

4D7U

25V5K

X-G

P

12345 6 7 8

SSSGD D D D

PU4004FD

MC

8884-GP

-U 84.08884.A372nd = 84.00412.037

SSSGD D D D

PU4004FD

MC

8884-GP

-U 84.08884.A372nd = 84.00412.037

1 2PC4009

SC1U16V3KX-2GP

PC4009

SC1U16V3KX-2GP

12

PR4032

10KR2F-L1-GP DYPR4032

10KR2F-L1-GP DY

1 2

PL4001IND-4D7UH-173-GP

68.4R71C.10K2nd = 68.4R710.20D


68.4R71C.10K2nd = 68.4R710.20D

12

PR4031

10KR2F-L1-GP

PR4031

10KR2F-L1-GP

12

PC4006

SC

D1U

25V2Z

Y-1G

P

PC4006

SC

D1U

25V2Z

Y-1G

P

12

PG4001GAP-CLOSE-PWR-3-GP


12

PC4010SCD01U50V2KX-L-GPPC4010SCD01U50V2KX-L-GP

12

PR4023

10KR2F-L1-GP

PR4023

10KR2F-L1-GP

12

PR401049K9R2F-L-GP

PR401049K9R2F-L-GP

12

PC

4011S

C220P

50V2JN

-3GP

PC

4011S

C220P

50V2JN

-3GP

12

PC4023

SC

D1U

50V3K

X-G

P

PC4023

SC

D1U

50V3K

X-G

P

12

PC

4002S

CD

1U50V

3KX

-GP

PC

4002S

CD

1U50V

3KX

-GP

12

PC

4017S

CD

047U25V

2KX

-GP

PC

4017S

CD

047U25V

2KX

-GP

AK

PD4002P6SBMJ27APT-GP


3rd = 83.P6SMB.CAG

PD4002P6SBMJ27APT-GP


3rd = 83.P6SMB.CAG

12

PR

40288K

45R2F

-2-GP

DY

PR

40288K

45R2F

-2-GP

DY

12

PR4022

10KR2F-L1-GP

PR4022

10KR2F-L1-GP

12

PC4022

SC

10U25V

5KX

-GP

PC4022

SC

10U25V

5KX

-GP

12P

G4004

GA

P-C

LOS

E-P

WR

-3-GP

PG

4004G

AP

-CLO

SE

-PW

R-3-G

P

12

PR4029100KR2J-4-GPPR4029100KR2J-4-GP

12


1 2

PR4015 10R5J-GPPR4015 10R5J-GP

1 2

PC4003SCD1U25V2KX-GP


1 2

PC4013SC3300P50V2KX-1GP

DYPC4013SC3300P50V2KX-1GP

DY

12

PC4001SCD47U25V3KX-1GP

PC4001SCD47U25V3KX-1GP

12345

678 S

SSGD

DDDPU4001

P1403EV8-GP

84.P1403.B37

SSSGD

DDDPU4001

P1403EV8-GP

84.P1403.B37

12

PR4026

100KR2J-4-GPDY

PR4026

100KR2J-4-GPDY

1 2PR40247D5R2F-GPPR40247D5R2F-GP

12

PR4020100KR2F-L2-GPPR4020100KR2F-L2-GP

1 2PR4008

0R3J-4-GP

PR4008

0R3J-4-GP

12


1234 5

678S

SSG D

DDD

PU4002P1403EV8-GP

84.P1403.B37

SSSG D

DDD

PU4002P1403EV8-GP

84.P1403.B37

12

PC4005

SC

4D7U

25V5K

X-G

P

DY

PC4005

SC

4D7U

25V5K

X-G

P

DY

12

PC

4016S

CD

1U25V

2KX

-GP

PC

4016S

CD

1U25V

2KX

-GP

12

PR4002

3D3MR2J-GP

PR4002

3D3MR2J-GP

12

PC4021

SC

10U25V

5KX

-GP

PC4021

SC

10U25V

5KX

-GP1

2PR4005

10KR2F-L1-GPDY

PR4005

10KR2F-L1-GPDY

G

SD

PQ40082N7002A-7-GP

PQ40082N7002A-7-GP

12



12


1

2

3 4

5

6

PQ4001

2N7002KDW-GP

84.2N702.A3F

2nd = 84.DM601.03F

PQ4001

2N7002KDW-GP

84.2N702.A3F

2nd = 84.DM601.03F

1 2PR4009

0R2J-L-GPDY

PR4009

0R2J-L-GPDY

12

PC

4012S

CD

1U25V

2KX

-GP

PC

4012S

CD

1U25V

2KX

-GP

WWW.MANUALS.CLAN.SU

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

PWR_3D3V_BOOT1

PWR_5V3D3V_ENC

PWR_5V_BOOT1_1

PWR_5V3D3V_TONSEL

PWR_5V3D3V_SKIPSEL

PWR_3D3V_FB2

PW

R_5

V3D

3V_V

RE

G3

PWR_3D3V_LGATE2

PWR_5V_FB1

PW

R_5

V3D

3V_V

RE

G5

PWR_5V_PHASE1

PWR_3D3V_BOOT2

PWR_5V_UGATE1

PWR_5V_ENTRIP1

PWR_5V_LGATE1

PWR_3D3V_UGATE2

PWR_5V_VOUT1

PWR_3D3V_PHASE2

PWR_5V_BOOT1

PWR_3D3V_VOUT2

PWR_5V_FB1_R

PWR_5V3D3V__EN0

PWR_3D3V_ENTRIP2

PWR_3D3V_FB2_R

DC

BA

TO

UT

_PD

1

PWR_5V3D3V__EN0_G5

PWR_5V_ENTRIP1

PWR_5V3D3V__EN0_G2

PWR_5V3D3V__EN0

PWR_3D3V_ENTRIP2

PWR_3D3V_EN

PWR_3D3V_ENTRIP2_R

PW

R_5

V_E

NT

RIP

1_R

PWR_5V_EN

PWR_5V_EN PWR_3D3V_EN

PWR_5V_DCBATOUT

5V_PWR

PWR_5V3D3V_VREF

3D3V_AUX_S5

PWR_5V3D3V_VREF

3D3V_PWR

PWR_3D3V_DCBATOUT

3D3V_AUX_S5

5V_AUX_S5

3D3V_S5

PWR_3D3V_DCBATOUT

PWR_5V_DCBATOUT

3D3V_PWR3D3V_SRC

5V_PWR 5V_S5

DCBATOUT_2

DCBATOUT_2

DCBATOUT_2

DCBATOUT_2

DCBATOUT_2

3D3V_AUX_S5

3V_5V_POK 19

5V_S5_EN36 3D3V_SRC_EN 27

Title


Date: Sheet of


Petra Uma -1

5V/3D3V(RT8223M)Custom

41 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1


41 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1


41 103Tuesday, July 10, 2012

<Core Design>

S

VREG3 or VREG5

375kHz

500kHz

PWM only

CH2CH1

VREF(2V)

OperatingMode

OOA Auto Skip Auto Skip

SKIPSEL GNDVREG3 or VREG5

TONSEL

GND

VREF

200kHz

300kHz

D

400kHz

S G

G

D

250kHz

S

G

D

D

SG

Vz=3.9V

Iomax=5AOCP>7.5A

Iomax=6AOCP>9A

PU4103 change to cost down version

SA_20111006

Close to VFB Pin (pin5)

Vout = 2 * ( 1 + R1/R2 )

= 2 * ( 1 + 6.8K / 10K)

= 3.36V

R2

R1

Close to VFB Pin (pin2)

Vout = 2 * ( 1 + R1/R2 )

= 2 * ( 1 +33K / 21K)

= 5.14V

R2

R1

5V OCP setting

3D3V OCP setting

PR4111 7.32K changee to 6.8K

Modify Description

Modify Description

Change power source

Change power source

Change power source

Wayler.2011.1209

-1_20120223

Option for non-IOAC

EC change

EC change

1 2PG4119

GAP-CLOSE-PWR

PG4119

GAP-CLOSE-PWR

1 2

PL4102IND-2D2UH-122-GP68.2R21B.10J2nd = 68.2R210.20B

PL4102IND-2D2UH-122-GP68.2R21B.10J2nd = 68.2R210.20B

1 2PR4130

0R2J-L-GP

PR4130

0R2J-L-GP

1 2PR41200R0402-PADPR41200R0402-PAD

1 2PG4120

GAP-CLOSE-PWR

PG4120

GAP-CLOSE-PWR

1

2

34

5

6

PQ4101

2N7002KDW-GP

84.2N702.A3F2nd = 84.DM601.03F3rd = 84.2N702.F3F

PQ4101

2N7002KDW-GP

84.2N702.A3F2nd = 84.DM601.03F3rd = 84.2N702.F3F

12345 6 7 8

SSSGD D D D

PU4104FDMC8884-GP-U

2nd = 84.08067.A3784.08884.A37

SSSGD D D D

PU4104FDMC8884-GP-U

2nd = 84.08067.A3784.08884.A37

KA

PD4105MMPZ5228BPT-GPPD4105MMPZ5228BPT-GP

1 2PG4112

GAP-CLOSE-PWR

PG4112

GAP-CLOSE-PWR

12

PG4124GA

P-C

LOS

E-P

WR

-3-GP

PG4124GA

P-C

LOS

E-P

WR

-3-GP

1 2 3 45678

S S S GDDDD PU4101

FDMC8884-GP-U84.08884.A372nd = 84.08067.A37

S S S GDDDD PU4101

FDMC8884-GP-U84.08884.A372nd = 84.08067.A37

12

PC4109SC18P50V2JN-1-GP

DY


DY

12


12

PR41116K8R2F-2-GP

PR41116K8R2F-2-GP

12

PC4108SCD33U6D3V2KX-1-GPDY

PC4108SCD33U6D3V2KX-1-GPDY

1 2PG4102

GAP-CLOSE-PWR

PG4102

GAP-CLOSE-PWR

12

PC4126SC

10U10V

3MX

-GP

PC4126SC

10U10V

3MX

-GP

12

PR4112

0R2J-L-GP

DYPR4112

0R2J-L-GP

DY

1 2PG4106

GAP-CLOSE-PWR

PG4106

GAP-CLOSE-PWR

12

PR4114

0R2J-L-GP

DY

PR4114

0R2J-L-GP

DY

1 2PG4103

GAP-CLOSE-PWR

PG4103

GAP-CLOSE-PWR

12

PC4129SC

D1U

25V3K

X-L-G

P

PC4129SC

D1U

25V3K

X-L-G

P

12


68.2R21B.10J2nd = 68.2R210.20B


68.2R21B.10J2nd = 68.2R210.20B

1 2PG4111

GAP-CLOSE-PWR

PG4111

GAP-CLOSE-PWR 12


1 2PG4107

GAP-CLOSE-PWR

PG4107

GAP-CLOSE-PWR1 2

PG4104

GAP-CLOSE-PWR

PG4104

GAP-CLOSE-PWR

12


12

PG4121GA

P-C

LOS

E-P

WR

-3-GP

PG4121GA

P-C

LOS

E-P

WR

-3-GP

1 2

PC4115SCD1U25V3KX-L-GP


12

PC4120SC

D1U

50V3K

X-G

P

PC4120SC

D1U

50V3K

X-G

P

12


DYPC4128SC18P50V2JN-1-GP

DY

12

PC4110

SC

4D7U

25V5K

X-G

P

PC4110

SC

4D7U

25V5K

X-G

P

1 2PR410888K7R2F-GPPR410888K7R2F-GP

12


DY


DY

12


12

PC4116SC

D1U

25V3K

X-L-G

PPC4116S

CD

1U25V

3KX

-L-GP

1 2PG4122

GAP-CLOSE-PWR

PG4122

GAP-CLOSE-PWR

1 2PG4108

GAP-CLOSE-PWR

PG4108

GAP-CLOSE-PWR

12

PR411533KR2F-2-GPPR411533KR2F-2-GP

1 2

PR41052D2R3-1-U-GPPR41052D2R3-1-U-GP

12

PC4114SC

4D7U

25V5K

X-G

P

PC4114SC

4D7U

25V5K

X-G

P

12

PT4102SE220U6D3VM-30-GP

77.52271.09L2ND = 77.52271.07L


77.52271.09L2ND = 77.52271.07L

12345 6 7 8

SSSGD D D D

PU4105FDMC8878-GP

2nd = 84.08065.B3784.08878.A30

SSSGD D D D

PU4105FDMC8878-GP

2nd = 84.08065.B3784.08878.A30

1 2PG4110

GAP-CLOSE-PWR

PG4110

GAP-CLOSE-PWR

12

PC

4122

SC

D22U

10V2K

X-1G

P

PC

4122

SC

D22U

10V2K

X-1G

P

12

PC4112

SC

4D7U

25V5K

X-G

P

DY

PC4112

SC

4D7U

25V5K

X-G

P

DY

1 2PG4114

GAP-CLOSE-PWR

PG4114

GAP-CLOSE-PWR

1 2PR410784K5R2F-GP

PR410784K5R2F-GP

12 PR41210R0402-PAD

PR41210R0402-PAD

1 2PG4101

GAP-CLOSE-PWR

PG4101

GAP-CLOSE-PWR

12PR4123

10KR2J-L-GPDY

PR4123

10KR2J-L-GPDY

1 2PG4115

GAP-CLOSE-PWR

PG4115

GAP-CLOSE-PWR

12 PR41180R0402-PAD

PR41180R0402-PAD

BOOT29

UGATE210

PHASE211

LGATE212

VOUT27

FB25

EN13

ENTRIP26

REF3

TONSEL4

VR

EG

38

VIN

16

BOOT1 22

UGATE1 21

PHASE1 20

LGATE1 19

VOUT1 24

FB1 2

PGOOD 23

ENTRIP1 1

PGND 15

VR

EG

517

GND 25

ENC 18SKIPSEL14

PU4103RT8223MZQW-GP-U

74.08223.B73

PU4103RT8223MZQW-GP-U

74.08223.B73

1 2PG4123

GAP-CLOSE-PWR

PG4123

GAP-CLOSE-PWR

1

2

34

5

6

PU4106

2N7002KDW-GP84.2N702.A3F2nd = 84.DM601.03F

PU4106

2N7002KDW-GP84.2N702.A3F2nd = 84.DM601.03F

1 2

PR41062D2R3-1-U-GPPR41062D2R3-1-U-GP

1 2PG4105

GAP-CLOSE-PWR

PG4105

GAP-CLOSE-PWR

12


77.52271.09L2ND = 77.52271.07L


77.52271.09L2ND = 77.52271.07L

1 2PR4122

10KR2J-L-GP

PR4122

10KR2J-L-GP

1 2PG4109

GAP-CLOSE-PWR

PG4109

GAP-CLOSE-PWR

1 2PG4116

GAP-CLOSE-PWR

PG4116

GAP-CLOSE-PWR

12

PR4110

100KR2J-4-GP

DY

PR4110

100KR2J-4-GP

DY

1 2PG4113

GAP-CLOSE-PWR

PG4113

GAP-CLOSE-PWR

12

PC4119SC

D1U

50V3K

X-G

P

PC4119SC

D1U

50V3K

X-G

P

12

PC4111SC

4D7U

25V5K

X-G

P

PC4111SC

4D7U

25V5K

X-G

P

1 2 3 45678

S S S GDDDD PU4102

FDMC8878-GP84.08878.A30

2nd = 84.08065.B37

S S S GDDDD PU4102

FDMC8878-GP84.08878.A30

2nd = 84.08065.B37

1 2



1 2PG4117

GAP-CLOSE-PWR

PG4117

GAP-CLOSE-PWR

12

PC4127SC18P50V2JN-1-GPDY

PC4127SC18P50V2JN-1-GPDY

1 2PR4109 820KR2F-GP

DYPR4109 820KR2F-GP

DY

12

PR4129750KR2F-GP

PR4129750KR2F-GP

1 2PG4118

GAP-CLOSE-PWR

PG4118

GAP-CLOSE-PWR

12

PR4125100KR2F-L1-GP

PR4125100KR2F-L1-GP

12


12

PC4125SC

4D7U

6D3V

5KX

-3GP

PC4125SC

4D7U

6D3V

5KX

-3GP

WWW.MANUALS.CLAN.SU

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

PWR_VCORE_GOODG

PWR_VCORE_LGATE1

PWR_VCORE_UGATE1

PWR_VCORE_PWM2G

PWR_VCORE_BOOT1

PWR_VCORE_BOOTG

PWR_VCORE_UGATEG

PWR_VCORE_COMP

PWR_VCORE_PHASEG

PWR_VCORE_LGATEG

PWR_VCORE_PHASE1

PW

R_V

CO

RE

_VD

D

PWR_VCORE_ISUMPG

PW

R_V

CO

RE

_VC

CP

PW

R_V

CO

RE

_VR

_ON

PWR_VCORE_COMP

PW

R_V

CO

RE

_FB

PW

R_V

CO

RE

_SD

A

PW

R_V

CO

RE

_SC

LK

PWR_VCORE_NTC

PWR_VCORE_ISEN2G

PWR_VCORE_ISEN2

PWR_VCORE_COMPG

PWR_VCORE_FBG_4

VSS_AXG_SENSE_R

PW

R_V

CO

RE

_FBG

PWR_VCORE_COMPGPWR_VCORE_ISUMNG

PWR_VCORE_ISUMN

VSSSENSE_R

PW

R_V

CO

RE

_VR

_HO

T#

PWR_VCORE_FB_4

PWR_VCORE_NTCG

PWR_VCORE_PWM3

PWR_VCORE_FB_3

PWR_VCORE_FB_2PWR_VCORE_FB_1

PWR_VCORE_FBG_3

PWR_VCORE_FBG_1 PWR_VCORE_FBG_2

PWR_VCORE_NTCG_1

PWR_VCORE_NTC_1

ISUMP_1

PWR_VCORE_ISEN2

PWR_VCORE_ISEN2G

3D3V_S0

5V_S5

1D05V_VTT

1D05V_VTT

5V_S5

5V_S5

PWR_VCORE_LGATE1 43

PWR_VCORE_UGATE1 43

PWR_VCORE_BOOT1 43

PWR_VCORE_BOOTG 44

PWR_VCORE_PHASEG44

PWR_VCORE_UGATEG 44PWR_VCORE_LGATEG 44

PWR_VCORE_PHASE143


H_CPU_SVIDDAT8

VR_SVID_ALERT#8

H_CPU_SVIDCLK8

H_PROCHOT#5,27

VSUM+43

VSUM-43

VCCSENSE8

VSSSENSE8

VCC_AXG_SENSE 9

VSS_AXG_SENSE 9

PWR_VCORE_ISUMPG44PWR_VCORE_ISUMNG44

IMVP_PWRGD 28,36

Title


Date: Sheet of


Petra Uma -1

ISL95836_CPU_CORE(1/3)Custom

42 102Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1


42 102Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1


42 102Tuesday, July 10, 2012

<Core Design>

SSID = CPU.Regulator

Close to VR

Place near choke of Phase1

NTC Place near high side MOSFET of Phase1

NTC place near high side MOSFET of Phase1

Setting IMax

Setting LoadLine

Setting OCP

Setting GFX LoadLine

SA:change power plane

SA:change to be 0603

PU4201 change to V1.7 (74.95836.B33)

PC4205 package change to 0402



PR4240 DY

Wayler 12.06

PC4206 DY

PR4218 change to 453 ohm

Wayler 12.06

-1_201202231

2


12

PC4214SC

1U10V

2KX

-1GP

PC4214SC

1U10V

2KX

-1GP

1 2PR4240 0R2J-L-GPDYPR4240 0R2J-L-GPDY

1 2 PC4226SCD1U10V2KX-L-GPPC4226SCD1U10V2KX-L-GP

1 2PC4209

SC33P50V2JN-3GP

PC4209

SC33P50V2JN-3GP


12


DY


DY

12

PC4215SC

1U10V

2KX

-1GP

PC4215SC

1U10V

2KX

-1GP

12



1 2PR4234 0R0402-PADPR4234 0R0402-PAD

12PR422627K4R2F-GPPR422627K4R2F-GP

1 2PR4243 0R0402-PADPR4243 0R0402-PAD

1 2

PC4212SC47P50V2JN-3GPPC4212SC47P50V2JN-3GP

1 2PR4232 0R0402-PADPR4232 0R0402-PAD

1 2PR4239 0R0402-PADPR4239 0R0402-PAD

12 PR42022KR2F-3-GPPR42022KR2F-3-GP


1 2PR4244 0R0402-PADPR4244 0R0402-PAD

1 2PC4201

SCD01U50V2KX-L-GP

PC4201

SCD01U50V2KX-L-GP

12PC4208

SC150P50V2KX-GP

PC4208

SC150P50V2KX-GP


12

PR420942K2R2F-L-GPPR420942K2R2F-L-GP

1 2PR42012KR2F-3-GPPR42012KR2F-3-GP

1 2PC4202

SCD01U50V2KX-L-GP

PC4202

SCD01U50V2KX-L-GP

12

PR4230130R2F-1-GPPR4230130R2F-1-GP

1 2PR4225NTC-470K-9-GPPR4225NTC-470K-9-GP

12

PR421411KR2F-L-GPPR421411KR2F-L-GP

1 2PR4204

1K91R2F-1-GP

PR4204

1K91R2F-1-GP

1 2PR4246 0R0402-PADPR4246 0R0402-PAD

12

PR42171K91R2F-1-GPPR42171K91R2F-1-GP

12

PR4215NTC-10K-27-GPPR4215NTC-10K-27-GP

12

PR422854D9R2F-L1-GPPR422854D9R2F-L1-GP

12

PC4213SC

D15U

10V2K

X-G

P

PC4213SC

D15U

10V2K

X-G

P

1 2PR4220 0R0402-PADPR4220 0R0402-PAD

12

PR42161K91R2F-1-GPPR42161K91R2F-1-GP

12

PR4227

75R3J-L-GP

PR4227

75R3J-L-GP

1 2PR4203

267KR2F-GP

PR4203

267KR2F-GP1 2

PC4207

SC150P50V2KX-GP

PC4207

SC150P50V2KX-GP

1 2

PC4205

SC680P50V2KX-2GP

PC4205

SC680P50V2KX-2GP

12

PR42120R0402-PADPR42120R0402-PAD

12PC4204

SC330P50V2KX-3GP

DYPC4204

SC330P50V2KX-3GP

DY

1 2PR4233 0R0402-PADPR4233 0R0402-PAD

1 2

PC4210

SC470P50V2KX-3GP

PC4210

SC470P50V2KX-3GP

1 2

PR4205 2K61R2F-1-GPPR4205 2K61R2F-1-GP

1 2PR4206267KR2F-GPPR4206267KR2F-GP

12

PR42111R2F-GPPR42111R2F-GP

1 2

PC4211 SC470P50V2KX-3GPPC4211 SC470P50V2KX-3GP

12

PC4224SC1U10V2KX-1GPPC4224SC1U10V2KX-1GP

1 2PR4245 0R0402-PADPR4245 0R0402-PAD

1 2PR4241 0R0402-PADPR4241 0R0402-PAD

1 2PR4231 0R0402-PADPR4231 0R0402-PAD

1 2PR4229499R2F-2-GPPR4229499R2F-2-GP

1 2PR4207499R2F-2-GPPR4207499R2F-2-GP

1 2

PR4218453R2F-1-GPPR4218453R2F-1-GP

1 2PC4203

SC330P50V2KX-3GPDY


DY

12

PR42132K61R2F-1-GPPR42132K61R2F-1-GP

ISUMPG1

ISEN1G2

ISEN2G3

NT

CG

4

SC

LK5

ALE

RT

#6

SD

A7

VR

_HO

T#

8

VR

_ON

9

NT

C10

ISEN3/FB211 ISEN212 ISEN113

ISUMP14

ISUMN15

RT

N16

FB

17

COMP 18

PGOOD 19

BO

OT

120

UGATE1 21

PHASE122

LGATE1 23

PWM3 24

VD

D25

VC

CP

26

LGATE2 27

PHASE228

UGATE2 29

BO

OT

230

BO

OT

1G31

UGATE1G 32

PHASE1G33

LGATE1G 34

PWM2G 35

PGOODG 36

COMPG 37

FB

G38

RT

NG

39

ISUMNG40

GN

D41

PU4201

ISL95836HRTZ-2-GP74.95836.B33

PU4201

ISL95836HRTZ-2-GP74.95836.B33

12

PR4210154KR2F-GPPR4210154KR2F-GP

1 2PR4222NTC-470K-9-GPPR4222NTC-470K-9-GP

1 2PR4208499R2F-2-GPPR4208499R2F-2-GP

12

PC4216

SC

D01U

50V2K

X-L-G

P

PC4216

SC

D01U

50V2K

X-L-G

P

WWW.MANUALS.CLAN.SU

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

PW

R_V

CC

CO

RE

_VS

UM

+_1

PWR_VCCCORE_BOOT1_1

PW

R_V

CC

CO

RE

_VS

UM

-_1

PWR_VCCCORE1_DCBATOUT

VCC_CORE PWR_VCCCORE1_DCBATOUTDCBATOUT

PWR_VCCCORE1_DCBATOUT DCBATOUT_2

PWR_VCORE_UGATE142PWR_VCORE_PHASE142

PWR_VCORE_LGATE142

PWR_VCORE_BOOT142

VSUM+ 42

VSUM- 42

Title


Date: Sheet of


Petra Uma -1

ISL95836_CPU_CORE(2/3)A3

43 102Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1


43 102Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1


43 102Tuesday, July 10, 2012

<Core Design>

Vcc_core

Iccmax=33A

Itdc=25A

OCP>40A

Add Gaps

PU4301

PU4302

BOM control

Mount

DY

2nd source

BOM control

Main source

84.03664.037 (FDMS3664S)

84.03664.037 (FDMS3664S)

EC change

12

PC4304SC

10U25V

5KX

-GP

DY

PC4304SC

10U25V

5KX

-GP

DY

1 2PG4315

GAP-CLOSE-PWR

PG4315

GAP-CLOSE-PWR

12

PT4308SE47U25VM-11-GP

DY


DY

1

234

567

8

910

PU4301

FDMS3600-02-RJK0215-COLAY-GP

1st = 84.03664.037

PU4301


1st = 84.03664.037

1 2PG4310

GAP-CLOSE-PWR

PG4310

GAP-CLOSE-PWR

1 2PG4309

GAP-CLOSE-PWR

PG4309

GAP-CLOSE-PWR

12

PC4302SC

10U25V

5KX

-GP

PC4302SC

10U25V

5KX

-GP

1

2

3

PT4302ST

470U2V

DM

-5-GP

-U1

PT4302ST

470U2V

DM

-5-GP

-U1

12

PC4303SC

10U25V

5KX

-GP

PC4303SC

10U25V

5KX

-GP

1

234

567

8

910

PU4302


DY

1st = 84.03664.037

PU4302


DY

1st = 84.03664.037

12

PT4307SE47U25VM-11-GPPT4307SE47U25VM-11-GP

1

2

3

PT4303ST

470U2V

DM

-5-GP

-U1

PT4303ST

470U2V

DM

-5-GP

-U1

12

PC4305SC10U25V5KX-GP

DY

PC4305SC10U25V5KX-GP

DY

1 2PG4311

GAP-CLOSE-PWR

PG4311

GAP-CLOSE-PWR

1 2PG4301

GAP-CLOSE-PWR

PG4301

GAP-CLOSE-PWR

1 2PG4316

GAP-CLOSE-PWR

PG4316

GAP-CLOSE-PWR

1 2PG4320

GAP-CLOSE-PWR

PG4320

GAP-CLOSE-PWR

12

PG4302GA

P-C

LOS

E-P

WR

-3-GP

PG4302GA

P-C

LOS

E-P

WR

-3-GP

1 2PG4312

GAP-CLOSE-PWR

PG4312

GAP-CLOSE-PWR

1 2PL4301

L-D36UH-1-GP

2nd = 68.R3610.20C68.R3610.20A

PL4301

L-D36UH-1-GP

2nd = 68.R3610.20C68.R3610.20A

1 2PR43071R2F-GPPR43071R2F-GP

1 2PG4304

GAP-CLOSE-PWR

PG4304

GAP-CLOSE-PWR

1 2PG4313

GAP-CLOSE-PWR

PG4313

GAP-CLOSE-PWR

12PR43113K65R2F-1-GPPR43113K65R2F-1-GP

12



1 2PG4307

GAP-CLOSE-PWR

PG4307

GAP-CLOSE-PWR

12


DY


DY

1 2PR43012D2R3-1-U-GPPR43012D2R3-1-U-GP

1 2PG4321

GAP-CLOSE-PWR

PG4321

GAP-CLOSE-PWR

12

PC4306SC

10U25V

5KX

-GP

PC4306SC

10U25V

5KX

-GP

1 2PG4308

GAP-CLOSE-PWR

PG4308

GAP-CLOSE-PWR

12

PG4303GA

P-C

LOS

E-P

WR

-3-GP

PG4303GA

P-C

LOS

E-P

WR

-3-GP

1 2PG4314

GAP-CLOSE-PWR

PG4314

GAP-CLOSE-PWR

WWW.MANUALS.CLAN.SU

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

VSUMG-

VSUMG+

PC4410_1

PW

R_

GF

XC

OR

E1

_IS

N_

R

PWR_GFXCORE_BOOT_1

PW

R_

GF

XC

OR

E1

_IS

P_

R

VSUMG+_1

VCC_GFXCORE

PWR_GFXCORE1_DCBATOUT

PWR_GFXCORE1_DCBATOUT

DCBATOUT_2

PWR_VCORE_PHASEG42

PWR_VCORE_UGATEG42

PWR_VCORE_LGATEG42

PWR_VCORE_BOOTG42

PWR_VCORE_ISUMNG 42

PWR_VCORE_ISUMPG 42

Title


Date: Sheet of


Petra Uma -1


44 102Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1


44 102Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1


44 102Tuesday, July 10, 2012

<Core Design>

BOM control

Mount

DY

BOM control

2nd source

PU4401

PU4402

Main source

84.03664.037 (FDMS3664S)

84.03664.037 (FDMS3664S)

Setting GFX OCP

Vcc_gfxcore

Iccmax=33 A

TDC = 21.5A

OCP>40A

1

2

3

PT4402ST

33

0U

2V

DM

-8-G

P-U

PT4402ST

33

0U

2V

DM

-8-G

P-U

1

2

3

PT4401ST

33

0U

2V

DM

-8-G

P-U

PT4401ST

33

0U

2V

DM

-8-G

P-U

12

PC4407

SC

D0

22

U1

6V

2K

X-3

GP

PC4407

SC

D0

22

U1

6V

2K

X-3

GP

12



1 2PR44061R2F-GPPR44061R2F-GP

12

PG4402GA

P-C

LO

SE

-PW

R-3

-GP

PG4402GA

P-C

LO

SE

-PW

R-3

-GP

1 2PG4408

GAP-CLOSE-PWR

PG4408

GAP-CLOSE-PWR

1

234

567

8

910

PU4402


DY

1st = 84.03664.037

PU4402


DY

1st = 84.03664.037

12

PC4403SC

10

U2

5V

5K

X-G

P

PC4403SC

10

U2

5V

5K

X-G

P

1 2PG4406

GAP-CLOSE-PWR

PG4406

GAP-CLOSE-PWR

12



12PR44083K65R2F-1-GPPR44083K65R2F-1-GP 1 2

PR4410 0R0402-PADPR4410 0R0402-PAD

12


1 2PG4404

GAP-CLOSE-PWR

PG4404

GAP-CLOSE-PWR

1 2PG4401

GAP-CLOSE-PWR

PG4401

GAP-CLOSE-PWR1 2

PR44012D2R3-1-U-GPPR44012D2R3-1-U-GP

1

234

567

8

910

PU4401


1st = 84.03664.037

PU4401


1st = 84.03664.037

12

PC4404SC10U25V5KX-GPPC4404SC10U25V5KX-GP

1 2PR4402549R2F-GP

DY

PR4402549R2F-GP

DY

1 2PL4401

L-D36UH-1-GP

2nd = 68.R3610.20C68.R3610.20APL4401

L-D36UH-1-GP

2nd = 68.R3610.20C68.R3610.20A

12

PC4402SC

10

U2

5V

5K

X-G

P

PC4402SC

10

U2

5V

5K

X-G

P

1 2PG4409

GAP-CLOSE-PWR

PG4409

GAP-CLOSE-PWR

1 2

PR4404464R2F-GPPR4404464R2F-GP

1 2PG4407

GAP-CLOSE-PWR

PG4407

GAP-CLOSE-PWR

12

PG4403GA

P-C

LO

SE

-PW

R-3

-GP

PG4403GA

P-C

LO

SE

-PW

R-3

-GP

12

PR44092K61R2F-1-GPPR44092K61R2F-1-GP

12

PR4405NTC-10K-27-GPPR4405NTC-10K-27-GP

12


DYPC4405SCD068U16V2KX-GP

DY

1 2PG4405

GAP-CLOSE-PWR

PG4405

GAP-CLOSE-PWR

12

PR440711KR2F-L-GPPR440711KR2F-L-GP

WWW.MANUALS.CLAN.SU

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

PWR_1D05V_VFB PWR_1D05V_PHASE

PWR_1D05V_BOOT_RPWR_1D05V_BOOTPWR_1D05V_UGATE

VTT_SENSE_L

VSS_SENSE_L

PWR_1D05V_LGATE

PWR_1D05V_EN

PWR_1D05V_CCM

PWR_1D05V_IMAX

PWR_1D05V_VFB

VTT_SENSE_L

VSS_SENSE_L

3D3V_S0

1D05V_PWR

PWR_DCBATOUT_1D05V

5V_S5

PWR_DCBATOUT_1D05V1D05V_PWR1D05V_VTT 1D05V_VTT

DCBATOUT_2

PWR_DCBATOUT_1D05VDCBATOUT

1D05VTT_PWRGD37,48

VCCIO_SENSE 8

VSSIO_SENSE 8

RUNPWROK46,47

Title


Date: Sheet of


Petra Uma -1

DC to DC_1D05V(TPS51218D)A3

45 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1


45 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1


45 103Tuesday, July 10, 2012

<Core Design>

Freq=360KHz

D

G S

Vout=0.704*(1+R1/R2)

TPS51218D for 1D05V

G

D

S

SD:暫暫暫暫暫暫暫暫暫暫暫暫暫暫暫暫7x7mm

Pana. 0.42uH 7*7*4DCR=1.5mohm

Iomax = 20.645ATDC = 14.45 AOCP > 26.83A

PR4504 change to 54K9 , OCP > 27A

2012-0130 , Wayler.

-1_20120221

1 2

PR4511

0R2J-L-GP

DYPR4511

0R2J-L-GP

DY

1 2PG4511

GAP-CLOSE-PWR

PG4511

GAP-CLOSE-PWR

12

PT4504SE330U2VDM-L-GP79.33719.L01

DY

PT4504SE330U2VDM-L-GP79.33719.L01

DY

12

PC4504

SC

4D7U

25V5K

X-G

P

PC4504

SC

4D7U

25V5K

X-G

P

1 2PG4515

GAP-CLOSE-PWR

PG4515

GAP-CLOSE-PWR

12

PR450820KR2F-L-GP

PR450820KR2F-L-GP

1 2PG4520

GAP-CLOSE-PWR

PG4520

GAP-CLOSE-PWR

1 2PG4502

GAP-CLOSE-PWR

PG4502

GAP-CLOSE-PWR

12

PR450910R2F-L-GP

PR450910R2F-L-GP

1 2PG4507

GAP-CLOSE-PWR

PG4507

GAP-CLOSE-PWR

12

PR4507

10KR2F-L1-GP

PR4507

10KR2F-L1-GP

123

4

5 6 7 8

SSS

GD D D D

PU4503FDMS0308AS-GP

84.00308.B302nd = 84.08058.037

SSS

GD D D D

PU4503FDMS0308AS-GP

84.00308.B302nd = 84.08058.037

1 2


12

PC4510SC1000P50V3JN-GP-UDY PC4510SC1000P50V3JN-GP-UDY

12

PC4511SC

D1U

25V3K

X-L-G

P

PC4511SC

D1U

25V3K

X-L-G

P

1 2PG4510

GAP-CLOSE-PWR

PG4510

GAP-CLOSE-PWR

1 2

PR45052D2R3-1-U-GPPR45052D2R3-1-U-GP

1 2PG4514

GAP-CLOSE-PWR

PG4514

GAP-CLOSE-PWR

1 2PG4518

GAP-CLOSE-PWR

PG4518

GAP-CLOSE-PWR

123

4

5 6 7 8

SSS

GD D D D

PU4502FDMS7698-GP

84.07698.0372nd = 84.08065.037

SSS

GD D D D

PU4502FDMS7698-GP

84.07698.0372nd = 84.08065.037

12


DY


DY

1 2PG4523

GAP-CLOSE-PWR

PG4523

GAP-CLOSE-PWR

1 2PG4501

GAP-CLOSE-PWR

PG4501

GAP-CLOSE-PWR

12

PR450610R2F-L-GP

PR450610R2F-L-GP

1 2PG4506

GAP-CLOSE-PWR

PG4506

GAP-CLOSE-PWR

1 2PG4509

GAP-CLOSE-PWR

PG4509

GAP-CLOSE-PWR

1 2PR45120R0402-PADPR45120R0402-PAD

1 2

PR4510

0R2J-L-GP

DYPR4510

0R2J-L-GP

DY

12

PC4506

SC

4D7U

25V5K

X-G

P

PC4506

SC

4D7U

25V5K

X-G

P

1 2PR4504

54K9R2F-L-GP

PR4504

54K9R2F-L-GP

1 2PG4513

GAP-CLOSE-PWR

PG4513

GAP-CLOSE-PWR

12

C4502SC1U10V2KX-1GP

C4502SC1U10V2KX-1GP

1 2PG4522

GAP-CLOSE-PWR

PG4522

GAP-CLOSE-PWR

12

PT4503SE330U2VDM-L-GP79.33719.L01

PT4503SE330U2VDM-L-GP79.33719.L01

12

PC4508

SC

18P50V

2JN-1-G

P

DYPC4508

SC

18P50V

2JN-1-G

P

DY

1 2PG4504

GAP-CLOSE-PWR

PG4504

GAP-CLOSE-PWR

12

PC4509

SC

D1U

50V3K

X-G

PDY

PC4509

SC

D1U

50V3K

X-G

PDY

12

PC4507SC

D01U

25V2K

X-3G

P

PC4507SC

D01U

25V2K

X-3G

P

12PR4516

10KR2J-L-GP

PR4516

10KR2J-L-GP

12


DRVL 6V5IN 7SW 8

DRVH 9VBST 10GND 11PGOOD1

TRIP2

EN3

VFB4

RF5

PU4501

TPS51218DSCR-GP-U2

74.51218.073

PU4501

TPS51218DSCR-GP-U2

74.51218.073

1 2PG4512

GAP-CLOSE-PWR

PG4512

GAP-CLOSE-PWR

1 2

PL4501

IND-D42UH-4-GP

PL4501

IND-D42UH-4-GP

1 2PG4516

GAP-CLOSE-PWR

PG4516

GAP-CLOSE-PWR

1 2PG4521

GAP-CLOSE-PWR

PG4521

GAP-CLOSE-PWR

1 2PG4503

GAP-CLOSE-PWR

PG4503

GAP-CLOSE-PWR

12

PC4505

SC

1KP

50V

2KX

-1G

P PC4505

SC

1KP

50V

2KX

-1G

P

1 2PG4508

GAP-CLOSE-PWR

PG4508

GAP-CLOSE-PWR

WWW.MANUALS.CLAN.SU

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

PWR_1D5V_TON

PWR_1D5V_VDDQ

PWR_0D75V_EN

PWR_1D5V_VTTIN

PWR_1D5V_VDDQ

PWR_1D5V_EN

PWR_1D5V_FB

PWR_1D5V_PHASE

PWR_1D5V_PHASE_LPWR_1D5V_BOOT

PWR_1D5V_LGATE

PWR_1D5V_UGATE

PWR_1D5V_EN

PWR_0D75V_EN

PW

R_

1D

5V

_V

TT

RE

F

PWR_1D5V_VDDP

PWR_1D5V_VCC5

PWR_1D5V_CS

PWR_DCBATOUT_1D5V

1D5V_S3

DDR_VREF_PWR

1D5V_S3

3D3V_S5

5V_S5

DDR_VREF_S3

1D5V_PWR

PWR_DCBATOUT_1D5V

DDR_VREF_PWR0D75V_S0

5V_S5

5V_S5

PWR_DCBATOUT_1D5VDCBATOUT_2

1D5V_S31D5V_PWR 1D5V_PWR

RUNPWROK45,47

PM_SLP_S4#19,27

0D75V_EN37

Title


Date: Sheet of


Petra Uma -1

RT8207Custom

46 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1

RT8207Custom

46 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1

RT8207Custom

46 103Tuesday, July 10, 2012

<Core Design>

Iomax=1AOCP>1.5A

Close to output cap pin1, notinside of the output cap

Close to pin23

G

S

D

G S

D

R1

R2 Vout=0.75*(1+R1/R2)

Close to PIN9

Close to pin23

+0.75VSIomax: 1.2A

SSID = PWR.Plane.Regulator_1p5v0p75v

20100728

RT8207L for 1D5V

SD:暫暫暫暫暫暫暫暫暫暫暫暫暫暫暫暫7x7mm

IccMAX = 18.38AIccTDC = 12.86AOCP > 23.89A

CYNTEC. 0.68uH 7*7*3DCR= 5 ~ 5.5 mohmIdc=15.5A, Isat=25A

EC change

1 2PG4609

GAP-CLOSE-PWR

PG4609

GAP-CLOSE-PWR

1 2PG4615

GAP-CLOSE-PWR

PG4615

GAP-CLOSE-PWR

1 2PR4610620KR2F-GP

PR4610620KR2F-GP

12

PT4602SE390U2D5VM-12-GP77.53971.01L2nd = 79.3971V.6AL

PT4602SE390U2D5VM-12-GP77.53971.01L2nd = 79.3971V.6AL

1 2PG4608

GAP-CLOSE-PWR

PG4608

GAP-CLOSE-PWR

12


12

PC4617

SC

4D

7U

25

V5

KX

-GP

DYPC4617

SC

4D

7U

25

V5

KX

-GP

DY

123

4

5 6 7 8

SSS

GD D D D

PU4602FDMS7698-GP

84.07698.0372nd = 84.08065.037

SSS

GD D D D

PU4602FDMS7698-GP

84.07698.0372nd = 84.08065.037

12

PR4602

10KR2F-L1-GP

PR4602

10KR2F-L1-GP

1 2PG4614

GAP-CLOSE-PWR

PG4614

GAP-CLOSE-PWR

12

PC4605SC

10

U6

D3

V5

MX

-L1

-GP

DY

PC4605SC

10

U6

D3

V5

MX

-L1

-GP

DY

VTT24

VT

TR

EF

5

FB 9

VTTSNS2

VD

DP

15

VLDOIN23

PHASE 20

UGATE 21

CS

16

S511

VTTGND1

PGOOD13

VDDQ 8

BOOT 22

LGATE 19

GN

D3

MODE4

PGND 18

DEM 6

S310

NC#17 17

VD

D14

TON12

NC#77

GN

D25

PU4601

RT8207LZQW-GP74.08207.D73

PU4601

RT8207LZQW-GP74.08207.D73

1 2PR4612 0R0402-PADPR4612 0R0402-PAD 1 2PR4605

0R0603-PADPR4605

0R0603-PAD

12PR4604

5D1R2F-GP

PR4604

5D1R2F-GP

1 2PG4622

GAP-CLOSE-PWR

PG4622

GAP-CLOSE-PWR

12

PC4613SC

1U

16

V3

KX

-5G

P

DYPC4613S

C1

U1

6V

3K

X-5

GP

DY

1 2PG4613

GAP-CLOSE-PWR

PG4613

GAP-CLOSE-PWR

12

PC4616

SC

4D

7U

25

V5

KX

-GP

PC4616

SC

4D

7U

25

V5

KX

-GP

12


DYPC4610SC18P50V2JN-1-GP

DY

1 2PG4621

GAP-CLOSE-PWR

PG4621

GAP-CLOSE-PWR

1 2PR4606

2D2R3-1-U-GP

PR4606

2D2R3-1-U-GP

12

PC4614

SC

4D

7U

25

V5

KX

-GP

PC4614

SC

4D

7U

25

V5

KX

-GP

1 2

PL4601

IND-D68UH-36-GP68.R681A.10A2nd = 68.R6810.20B

PL4601

IND-D68UH-36-GP68.R681A.10A2nd = 68.R6810.20B

1 2PG4612

GAP-CLOSE-PWR

PG4612

GAP-CLOSE-PWR

1 2PG4620

GAP-CLOSE-PWR

PG4620

GAP-CLOSE-PWR

1 2PG4601

GAP-CLOSE-PWR

PG4601

GAP-CLOSE-PWR

12

PC4604SC

10

U6

D3

V5

MX

-L1

-GP

PC4604SC

10

U6

D3

V5

MX

-L1

-GP

1 2PG4611

GAP-CLOSE-PWR

PG4611

GAP-CLOSE-PWR

1 2PG4606

GAP-CLOSE-PWR

PG4606

GAP-CLOSE-PWR

1 2PG4619

GAP-CLOSE-PWR

PG4619

GAP-CLOSE-PWR

12

PC4603SC10U6D3V5MX-L1-GP


12


12


12

PC4615

SC

D1

U2

5V

3K

X-L

-GP

PC4615

SC

D1

U2

5V

3K

X-L

-GP

123

4

5 6 7 8

SSS

GD D D D

PU4603FDMS0308AS-GP84.00308.B302nd = 84.08058.037SSS

GD D D D

PU4603FDMS0308AS-GP84.00308.B302nd = 84.08058.037

12

PC4612SCD1U10V2KX-L1-GP

DY

PC4612SCD1U10V2KX-L1-GP

DY

1 2PG4605

GAP-CLOSE-PWR

PG4605

GAP-CLOSE-PWR

1 2PG4618

GAP-CLOSE-PWR

PG4618

GAP-CLOSE-PWR

1 2PG4607

GAP-CLOSE-PWR

PG4607

GAP-CLOSE-PWR

1 2PG4603

GAP-CLOSE-PWR

PG4603

GAP-CLOSE-PWR

1 2PR46070R0402-PAD

PR46070R0402-PAD

12

PC4602

SC

1K

P5

0V

2K

X-1

GP

PC4602

SC

1K

P5

0V

2K

X-1

GP

1 2PG4617

GAP-CLOSE-PWR

PG4617

GAP-CLOSE-PWR

1 2



12


1 2PR46150R0402-PADPR46150R0402-PAD

1 2PG4602

GAP-CLOSE-PWR

PG4602

GAP-CLOSE-PWR

12

PR4603

8K

87

R2

F-2

-GP

PR4603

8K

87

R2

F-2

-GP

1 2PG4610

GAP-CLOSE-PWR

PG4610

GAP-CLOSE-PWR

12


1 2PG4616

GAP-CLOSE-PWR

PG4616

GAP-CLOSE-PWR

WWW.MANUALS.CLAN.SU

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

PWR_1D8V_EN

PWR_1D8V_ADJ

1D8V_LDO 1D8V_S0

3D3V_S0 5V_S5

RUNPWROK45,46PM_SLP_S3#19,27,29,36,37

Title


Date: Sheet of


Petra Uma -1

LDO_1D8V(RT9025)A4

47 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1

LDO_1D8V(RT9025)A4

47 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1

LDO_1D8V(RT9025)A4

47 103Tuesday, July 10, 2012

<Core Design>

SSID = PWR.Plane.Regulator_1p8v

Vo(cal.)=1.812V

RT9025 for 1D8V_S0

Iomax>2.22AOCP>3A

1 2PG4702

GAP-CLOSE-PWR

PG4702

GAP-CLOSE-PWR

12

PC4707SCD1U10V2KX-L1-GPPC4707SCD1U10V2KX-L1-GP

12

PC4705SC

10U6D

3V5M

X-L1-G

P

PC4705SC

10U6D

3V5M

X-L1-G

P

12

PC4704SC

100P50V

2JN-L-G

P

PC4704SC

100P50V

2JN-L-G

P

12

PC4706SC

10U6D

3V5M

X-L1-G

P

DY

PC4706SC

10U6D

3V5M

X-L1-G

P

DYPGOOD1EN2VIN 3VDD4

NC#5 5

VOUT 6

ADJ 7

GND 8

GND 9

PU4701

RT9025-25ZSP-GP

74.09025.B3D

2nd = 74.09661.07D

PU4701

RT9025-25ZSP-GP

74.09025.B3D

2nd = 74.09661.07D

1 2PG4701

GAP-CLOSE-PWR

PG4701

GAP-CLOSE-PWR

12

PR470420K5R2F-GP

PR470420K5R2F-GP

1 2PR47060R0402-PAD

PR47060R0402-PAD

12

PC4701SC

10U6D

3V5M

X-L1-G

P

PC4701SC

10U6D

3V5M

X-L1-G

P

12

PR470516K2R2F-GP

PR470516K2R2F-GP

12


WWW.MANUALS.CLAN.SU

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

PWR_VCCSA_VID0

PWR_VCCSA_VID1

D85V_PWRGD

PWR_G978_VIN

D85V_PWRGDPWR_VCCSA_EN

PWR_VCCSA_EN

PWR_VCCSA_VID1PWR_VCCSA_VID0

0D85V_PWR

3D3V_S0

0D85V_S00D85V_PWR

5V_S0

1D05V_VTT_CPU

0D85V_PWR

VCCSA_VID1 9

VCCSA_VID0 9

1D05VTT_PWRGD 37,45

ALL_POWER_OK 27,37,42

Title


Date: Sheet of


Petra Uma -1

VCCSA SY8037A3

48 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1

VCCSA SY8037A3

48 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1

VCCSA SY8037A3

48 103Tuesday, July 10, 2012

<Core Design>

Design Current =4 A

VID0 VCCSA

0.675V

0.725VL

L

VID1

H

0.8VL

H

L

H

H

0.9V

PWM SY8037 for VCCSA

LDO G978 for VCCSA

SA_20111223A

1 2PR4804 0R0402-PADPR4804 0R0402-PAD

1 2PR4805 0R0402-PADPR4805 0R0402-PAD

12

PC4809SC1U10V2KX-1GP

0D85V_LDO

PC4809SC1U10V2KX-1GP

0D85V_LDO

1 2PG4809

GAP-CLOSE-PWR

PG4809

GAP-CLOSE-PWR

1 2PR4803 10KR2J-L-GPPR4803 10KR2J-L-GP

1 2PR4808 0R0402-PADPR4808 0R0402-PAD

1 2PR4801 0R0402-PADPR4801 0R0402-PAD

1 2PG4812

GAP-CLOSE-PWR

PG4812

GAP-CLOSE-PWR

1 2PG4811

GAP-CLOSE-PWR

PG4811

GAP-CLOSE-PWR

1 2PG4806

GAP-CLOSE-PWR

PG4806

GAP-CLOSE-PWR

1 2PG4813

GAP-CLOSE-PWR

PG4813

GAP-CLOSE-PWR

1 2PR4812 1KR2F-L-GP

DYPR4812 1KR2F-L-GP

DY

12

PC

4804

SC

10U6D

3V5K

X-1G

P

PC

4804

SC

10U6D

3V5K

X-1G

P

12

PC

4805

SC

22U6D

3V5M

X-L3-G

P

DY

PC

4805

SC

22U6D

3V5M

X-L3-G

P

DY

1 2PG4807

GAP-CLOSE-PWR

PG4807

GAP-CLOSE-PWR

12


0D85V_LDO


0D85V_LDO

D01

D12

VO#33

VO#44

VIN 5VPP 6POK 7

VEN/MODE 8GND 9

PU4802

G978F11U-GP

74.00978.031

0D85V_LDO

PU4802

G978F11U-GP

74.00978.031

0D85V_LDO

1 2PG4804

GAP-CLOSE-PWR

PG4804

GAP-CLOSE-PWR

12

PR480710KR2J-L-GP

DY

PR480710KR2J-L-GP

DY

12

PC

4803

SC

10U6D

3V5K

X-1G

P

PC

4803

SC

10U6D

3V5K

X-1G

P

12

PC

4806

SC

D1U

25V3K

X-L-G

P

DY

PC

4806

SC

D1U

25V3K

X-L-G

P

DY

1 2PG4808

GAP-CLOSE-PWR

PG4808

GAP-CLOSE-PWR

12

PC4810SC1U6D3V2KX-L-1-GP

DY PC4810SC1U6D3V2KX-L-1-GP

DY

1 2PG4805

GAP-CLOSE-PWR

PG4805

GAP-CLOSE-PWR

1 2PG4810

GAP-CLOSE-PWR

PG4810

GAP-CLOSE-PWR

WWW.MANUALS.CLAN.SU

DBC_EN_C

DP_TXP1_CPU_C

LCD_BRIGHTNESSDP_TXN1_CPU_C

LCD_BRIGHTNESS

USB_CAMERAUSB_CAMERA#

DBC_EN_CBLON_OUT_C

DP_DDC_DATA_CPU_CDP_DDC_CLK_CPU_C

DP_TXP1_CPU_CDP_TXN1_CPU_C

DP_TXN1_CPU_C

DP_AUXP_CPU_C

DP_TXP1_CPU_C

DP_TXP0_CPU_C

DP_DDC_DATA_CPU_CDP_DDC_CLK_CPU_C EDP_DDC_CLK

EDP_DDC_DATA

EDP_DDC_CLK

EDP_DDC_DATA

AUD_GND

AUD_GND

INT_MIC_L_R

DP_AUXP_CPU_CDP_AUXN_CPU_C

DP_TXP0_CPU_CDP_TXN0_CPU_CEDP#_LVDS_R

DP_AUXN_CPU_C

DP_TXN0_CPU_C

BLON_OUT_C

DP_HPD0_C

DP_HPD0_C

EDP#_LVDS_BEDP#_LVDS_R

EDP#_LVDS_C

LCDVDD3D3V_S0

3D3V_S0

DCBATOUT_LCD

DCBATOUT

3D3V_CAMERA_S03D3V_S0

3D3V_S0

3D3V_CAMERA_S0

DCBATOUT_LCD

3D3V_S0

1D05V_VTT

LCDVDD

AUD_AGND

LCDVDD

3D3V_S03D3V_S0

LVDS_VDD_EN17

L_BKLT_CTRL 17

USB_PP3 18USB_PN3 18

LVDS_DDC_DATA_R 17LVDS_DDC_CLK_R 17

DP_TXP1_CPU 4DP_TXN1_CPU 4

DP_AUXN_CPU 4DP_AUXP_CPU 4

DP_TXN0_CPU 4DP_TXP0_CPU 4

DP_AUXN_CPU4DP_AUXP_CPU4

DP_HPD# 4

SML1_DATA 20,27,28

SML1_CLK 20,27,28

INT_MIC_L_R 29

LVDSA_CLK 17LVDSA_CLK# 17

LVDSA_DATA2# 17LVDSA_DATA2 17

LVDSA_DATA1 17LVDSA_DATA1# 17

LVDSA_DATA0 17LVDSA_DATA0# 17

BLON_OUT27

EDP#_LVDS 22

MODEL_ID_R 27

Title


Date: Sheet of


Petra Uma -1

LCD ConnectorA2

49 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1

LCD ConnectorA2

49 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1

LCD ConnectorA2

49 103Tuesday, July 10, 2012

<Core Design>

SSID = VIDEO

Layout 40 mil

CCD GND

EDP: pin35 NCLVDS: pin35 GND

-1_20120214 Change DUMMY from eDPto DY (For eDP_EDID)

-1_20120301

12

R4919100KR2J-4-GP

DY

R4919100KR2J-4-GP

DY

12

C4906

SC

4D7U

25V5K

X-G

PC

4906S

C4D

7U25V

5KX

-GP

1 2 C4915 SCD1U16V2KX-L-GPEDP C4915 SCD1U16V2KX-L-GPEDP

1 2R49070R0402-PADR49070R0402-PAD

12

R4918100KR2J-4-GP

DY

R4918100KR2J-4-GP

DY

12

C4905SCD1U50V3KX-GPC4905SCD1U50V3KX-GP

1 2R49031KR2J-L2-GP

R49031KR2J-L2-GP

12


12

EC

4904S

C5D

6P50V

2CN

-1GP

DY

EC

4 904S

C5D

6P50V

2CN

-1GP

DY

EN1

GND2

OUT3 NC#4 4

IN 5

U4901

SY6288C6AAC-GP74.06288.B7F2nd = 74.09724.09F

U4901

SY6288C6AAC-GP74.06288.B7F2nd = 74.09724.09F

12 R490410KR2J-L-GP

DYR490410KR2J-L-GP

DY

12

R4917100KR2J-4-GP

DY

R4917100KR2J-4-GP

DY


12

EC4906MLVG0402220NV05BP-GP-U

DYEC4906MLVG0402220NV05BP-GP-U

DY

12R4902 33R2J-L1-GPR4902 33R2J-L1-GP

12

EC

4905S

C5D

6P50V

2CN

-1GP

DY

EC

4 905S

C5D

6P50V

2CN

-1GP

DY

12

R490610KR2J-L-GPDY

R490610KR2J-L-GPDY

1 2R4908 0R0603-PADR4908 0R0603-PAD

12

C4907

SC

4D7U

6D3V

3KX

-L-GP

C4907

SC

4D7U

6D3V

3KX

-L-GP

1 2R49100R2J-L-GP

DY

R49100R2J-L-GP

DY

12 3

4

RN4907SRN0J-6-GP

DY

RN4907SRN0J-6-GP

DY

12

C4 908

SC

4D7U

6D3V

3KX

-L-GP

C4 908

SC

4D7U

6D3V

3KX

-L-GP

1 234

RNH491SRN2K2J-1-GPDYRNH491SRN2K2J-1-GPDY

12


12

C4910SC100P50V2JN-L-GPC4910SC100P50V2JN-L-GP

12

R4914

100KR

2J-4-GP

DY

R4 914

100KR

2J-4-GP

DY


1 2R4923150KR2J-L1-GPR4923150KR2J-L1-GP

C

B

E

Q4904MMBT3904-4-GP84.T3904.C112ND = 84.03904.P113rd = 84.03904.L06


12

EC

4 902S

C33P

50V2JN

-3GP

DY

EC

4 902S

C33P

50V2JN

-3GP

DY

G S

D

Q49022N7002K-2-GP

84.2N702.J312ND = 84.2N702.031

EDP

Q49022N7002K-2-GP

84.2N702.J312ND = 84.2N702.031

EDP


12

C4903SC10U6D3V3MX-L-GPC4903SC10U6D3V3MX-L-GP

1

2

3 4

5

6


DY


DY

12

R4922100KR2J-4-GPEDP

R4922100KR2J-4-GPEDP

12

C4 909

SC

56P50V

2JN-2G

P

DY

C4 909

SC

56P50V

2JN-2G

P

DY


12

F4901POLYSW-1D1A24V-GP-U

2nd = 69.50007.A4169.50007.A31

F4901POLYSW-1D1A24V-GP-U

2nd = 69.50007.A4169.50007.A31

1

2345678910111213141516171819202122232425262728293031323334353637383940

41

42

NP1

NP2

LCD1

PS-CON40-GP

20.F1816.0402nd = 20.F1860.040

LCD1

PS-CON40-GP

20.F1816.0402nd = 20.F1860.040

1 2R4909 0R0603-PADR4909 0R0603-PAD

12

C4904

SC

D1U

50V3K

X-G

PC

4904S

CD

1U50V

3KX

-GP

1 2

R4929

0R0402-PAD

R4929

0R0402-PAD

1 2

F4902FUSE-1D1A6V-4GP-U69.50007.6912ND = 69.50007.771

F4902FUSE-1D1A6V-4GP-U69.50007.6912ND = 69.50007.771

12

EC

4903S

CD

1U10V

2KX

-L1-GP

DY

EC

4903S

CD

1U10V

2KX

-L1-GP

DY

12 R

4 911100K

R2J-4-G

PR

4 911100K

R2J-4-G

P


12 3

4


12



12


1 2R4920 0R2J-L-GPEDPR4920 0R2J-L-GPEDP

12


12

R4916100KR2J-4-GP

DY

R4916100KR2J-4-GP

DY

WWW.MANUALS.CLAN.SU

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

CRT_R

CRT_G

CRT_B

CRT_DDCCLK_CONCRT_VSYNC_CON

CRT_DDCDATA_CONCRT_HSYNC_CON

CRT_DDCCLK_CON

CRT_DDCDATA_CON

CRT_B

CRT_G

CRT_R

CRT_DDCCLK_CON

CRT_DDCDATA_CON

CRT_HSYNC1_1CRT_VSYNC1_1

CRT_VSYNC_CONCRT_VSYNC1_1

CRT_HSYNC_CONCRT_HSYNC1_1

CRT_HSYNC_CON

CRT_VSYNC_CON

5V_HDMI5V_CRT_S0

3D3V_S0

3D3V_S0

5V_CRT_S0

5V_S0

5V_S0

5V_S0 5V_S0

CRT_RED17

CRT_GREEN17

CRT_BLUE17

CRT_DDC_DATA17

CRT_DDC_CLK17

CRT_HSYNC17CRT_VSYNC17

CRT_DDCDATA_CON 59

CRT_DDCCLK_CON 59

CRT_R 59

CRT_G 59

CRT_B 59

CRT_HSYNC_CON 59

CRT_VSYNC_CON 59

Title


Date: Sheet of


Petra Uma -1

CRT ConnectorA3

50 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1

CRT ConnectorA3

50 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1

CRT ConnectorA3

50 103Tuesday, July 10, 2012

<Core Design>

CRT DDCDATA & DDCCLK level shift

1 2

L5003BLM18BB220SN-GP68.00084.A11

L5003BLM18BB220SN-GP68.00084.A11 1

2

C5009

SC

18P50V

2JN-1-G

P

DY

C5009

SC

18P50V

2JN-1-G

P

DY

9 8

14 10

7

U5001CTC74VHCT125AFTQK2M-GP

2nd = 73.74125.L1373.74125.F0B

U5001CTC74VHCT125AFTQK2M-GP

2nd = 73.74125.L1373.74125.F0B

1

2

34

5

6



1 2 3 45678

RN5004SRN150F-1-GPRN5004SRN150F-1-GP

12 11

14 13

7

U5001DTC74VHCT125AFTQK2M-GP

2nd = 73.74125.L1373.74125.F0B

U5001DTC74VHCT125AFTQK2M-GP

2nd = 73.74125.L1373.74125.F0B

5 6

14 4

7

U5001BTC74VHCT125AFTQK2M-GP

2nd = 73.74125.L1373.74125.F0B

U5001BTC74VHCT125AFTQK2M-GP

2nd = 73.74125.L1373.74125.F0B

2 3

14 1

7

U5001ATC74VHCT125AFTQK2M-GP

2nd = 73.74125.L1373.74125.F0B

U5001ATC74VHCT125AFTQK2M-GP

2nd = 73.74125.L1373.74125.F0B

12

C5012

SC

D01U

16V2K

X-L1-G

PC

5012S

CD

01U16V

2KX

-L1-GP

12

C5010

SC

18P50V

2JN-1-G

P

DY

C5010

SC

18P50V

2JN-1-G

P

DY

123 4


12

C5001

SC

10P50V

2JN-4G

PC

5001S

C10P

50V2JN

-4GP

12

C5005

SC

10P50V

2JN-4G

PC

5005S

C10P

50V2JN

-4GP

12

C5006

SC

10P50V

2JN-4G

PC

5006S

C10P

50V2JN

-4GP

12

C5004

SC

10P50V

2JN-4G

PC

5004S

C10P

50V2JN

-4GP

1 2

L5001BLM18BB220SN-GP68.00084.A11

L5001BLM18BB220SN-GP68.00084.A11

12

C5011SC100P50V2JN-L-GPDYC5011SC100P50V2JN-L-GPDY

12

C5002

SC

10P50V

2JN-4G

PC

5002S

C10P

50V2JN

-4GP

1 2R500110R2J-2-GPR500110R2J-2-GP

1 2R500210R2J-2-GP

R500210R2J-2-GP

21 D5001

CH551H-30PT-GP

2ND = 83.R5003.H8H3rd = 83.5R003.08F

83.R5003.C8F

D5001CH551H-30PT-GP

2ND = 83.R5003.H8H3rd = 83.5R003.08F

83.R5003.C8F

123 4

RN5003SRN10KJ-L-GPRN5003SRN10KJ-L-GP

12

C5003

SC

10P50V

2JN-4G

PC

5003S

C10P

50V2JN

-4GP

1 2

L5002BLM18BB220SN-GP68.00084.A11

L5002BLM18BB220SN-GP68.00084.A11

12

C5008

SC

100P50V

2JN-L-G

P

DY

C5008

SC

100P50V

2JN-L-G

P

DY

WWW.MANUALS.CLAN.SU

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

HP

D_H

DM

I_C

ON

DDC_DATA_HDMIDDC_CLK_HDMI

HDMI_DATA2_R#

HDMI_DATA1_R#HDMI_DATA1_R

HDMI_CLK_RHDMI_CLK_R#

HDMI_DATA0_R

HDMI_DATA2_R

HDMI_CLK_R#

HDMI_DATA1_R#

HDMI_DATA2_R#

HDMI_DATA0_R#HDMI_CLK_R

HDMI_DATA1_R

HDMI_PLL_GND

HDMI_HPD_B

HDMI_DATA0_R#HDMI_DATA0_R

HDMI_DATA2_R

5V_S0_D1

5V_S0_D2

DDC_CLK_HDMIDDC_DATA_HDMI

HDMI_HPD_E

5V_HDMI

5V_S05V_HDMI

5V_S0

5V_S0

3D3V_S0

3D3V_S0HDMI_CLK_R#17HDMI_CLK_R17

HDMI_DATA0_R#17HDMI_DATA0_R17



PCH_HDMI_CLK17

PCH_HDMI_DATA17

HDMI_PCH_DET 17

Title


Date: Sheet of


Petra Uma -1

HDMI Level Shifter/ConnectorA3

51 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1


51 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1


51 103Tuesday, July 10, 2012

<Core Design>

SSID = VIDEO

Close to HDMI Connector

HDMI Level Shifter & CONNECTOR

-1_20120221

12


12345 6 7 8

RN5115SR

N680J-1-G

P

RN5115SR

N680J-1-G

P

1 2R5111150KR2J-L1-GPR5111150KR2J-L1-GP

1

2

3

D5103BAW56-5-GP83.00056.Q112nd = 83.00056.K11

D5103BAW56-5-GP83.00056.Q112nd = 83.00056.K11

C

B

E



20

21

1

2345678910111213141516171819

22

23

HDMI1

SKT-HDMI23-45-GP22.10296.631

HDMI1

SKT-HDMI23-45-GP22.10296.631

1

2

34

5

6



1 2R51290R0402-PAD

R51290R0402-PAD

12

F5101FUSE-1D1A6V-4GP-U69.50007.6912nd = 69.50007.771

F5101FUSE-1D1A6V-4GP-U69.50007.6912nd = 69.50007.771

1 2 3 45678

RN5114SR

N680J-1-G

P

RN5114SR

N680J-1-G

P

12

R5110200KR2J-L1-GP DY

R5110200KR2J-L1-GP DY

G

SD

Q5105

2N7002A-7-GP

Q5105

2N7002A-7-GP

1 234


WWW.MANUALS.CLAN.SU

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of


Petra Uma -1

eDPA4


<Core Design>

Title


Date: Sheet of


Petra Uma -1

eDPA4


<Core Design>

Title


Date: Sheet of


Petra Uma -1

eDPA4


<Core Design>

LED BACKLIGHT CONVERTER POWER

(Blanking)

WWW.MANUALS.CLAN.SU

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of


Petra Uma -1

S-VIDEOA4


<Core Design>

Title


Date: Sheet of


Petra Uma -1

S-VIDEOA4


<Core Design>

Title


Date: Sheet of


Petra Uma -1

S-VIDEOA4


<Core Design>

(Blanking)

WWW.MANUALS.CLAN.SU

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of


Petra Uma -1

ReservedA4


<Core Design>

Title


Date: Sheet of


Petra Uma -1

ReservedA4


<Core Design>

Title


Date: Sheet of


Petra Uma -1

ReservedA4


<Core Design>

(Blanking)

WWW.MANUALS.CLAN.SU

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of


Petra Uma -1

ITPA4


<Core Design>

Title


Date: Sheet of


Petra Uma -1

ITPA4


<Core Design>

Title


Date: Sheet of


Petra Uma -1

ITPA4


<Core Design>

ITP ConnectorCPU

TCK(PIN AC5)

FBO(PIN 11)

TCK(PIN 5)

ITP ConnectorH_CPURST# use pull-up Resistor closeITP connector 500 mil ( max ),others place near CPU side.

SSID = User.Interface

(Blanking)

WWW.MANUALS.CLAN.SU

SATA_ODD_PWRGTSATA_ODD_DA# SATA_ODD_DA#_C

SATA_ODD_PWRGT SATA_ODD_DA#

OD

D_P

WR

GT

#

SATA_ODD_DA#_CODD_PWR_5V

SATA_TXP4_CSATA_TXN4_C

SATA_RX4-_CSATA_RX4+_C

ODD_PWR_5V

SATA_TXN0_CSATA_TXP0_C

SATA_RXP0_CSATA_RXN0_C

SATA_TXP0_3CSATA_TXN0_3C

SATA_RXN0_3CSATA_RXP0_3C

3D3V_S0

3D3V_S0

5V_S0

5V_S0

5V_S0

5V_S0

SATA_ODD_PRSNT# 22SATA_ODD_DA# 18

SATA_TXP421SATA_TXN421

SATA_RXN421SATA_RXP421

SATA_ODD_PWRGT22

SATA_TXN021SATA_TXP021

SATA_RXP021SATA_RXN021

SATA_RXP021SATA_RXN021

SATA_TXN021SATA_TXP021

Title


Date: Sheet of


Petra Uma -1

HDD/ODDA3

56 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1

HDD/ODDA3

56 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1

HDD/ODDA3

56 103Tuesday, July 10, 2012

<Core Design>

SATA HDD ConnectorSSID = SATA

ODD Connector SATA Zero Power ODD

High Active 2A

-1_20120223

-1_20120301

-1_20120301

1 2 C5602SCD01U16V2KX-L1-GPNon cable

C5602SCD01U16V2KX-L1-GPNon cable

12

TC5601SC10U25V5KX-GPZPO

TC5601SC10U25V5KX-GPZPO

1 2C5603SCD01U16V2KX-L1-GP Non cableC5603SCD01U16V2KX-L1-GP Non cable

12


12

TC5602SC10U25V5KX-GPTC5602SC10U25V5KX-GP

1 2 C5616SCD01U16V2KX-L1-GPCable

C5616SCD01U16V2KX-L1-GPCable

23NP1

1

234567

89

10111213141516171819202122

NP224

HDD1

SKT-SATA22P-40-GP

Non-cable

22.10300.3512nd = 22.10300.0313rd = 22.10300.011

HDD1

SKT-SATA22P-40-GP

Non-cable

22.10300.3512nd = 22.10300.0313rd = 22.10300.011

1 2 C5608SCD01U16V2KX-L1-GP C5608SCD01U16V2KX-L1-GP

12 3

4

RN5601SRN10KJ-L-GP

ZPO

RN5601SRN10KJ-L-GP

ZPO



GND1

IN#22

IN#33

EN/EN#4 OCB 5OUT#6 6OUT#7 7OUT#8 8

U5601

SY6288CCAC-GP74.06288.079

ZPO

2nd = 74.02311.A79

U5601

SY6288CCAC-GP74.06288.079

ZPO

2nd = 74.02311.A79

1

23456789

1011121314151617181920

2122

2324

NP1

NP2

HDD2

FOX-CON20-1-GP-U

20.F1546.020

CableHDD2

FOX-CON20-1-GP-U

20.F1546.020

Cable

12 C5609SCD01U16V2KX-L1-GPNon cable


12

R560410KR2J-L-GP

DY

R560410KR2J-L-GP

DY


12 R56020R2J-L-GPDY

R56020R2J-L-GPDY

12


GND S1

A+S2A-S3 GND S4

B-S5

B+S6

GND S7

DP P1+5VP2

+5VP3MD P4

GND P5

GND P6

GND 14

GND 15

NP1NP1

NP2NP2

ODD1

SKT-SATA7P-6P-119-GP22.10300.H312nd = 22.10300.H61

ODD1

SKT-SATA7P-6P-119-GP22.10300.H312nd = 22.10300.H61

1 2 3456


ZPOQ56012N7002KDW-GP84.2N702.A3F2nd = 84.DM601.03F

ZPO




12

C5605

SC

10U25V

5KX

-GP

Non cable

C5605

SC

10U25V

5KX

-GP

Non cable

12R56030R5J-5-GP ODD

R56030R5J-5-GP ODD

12

C5604

SC

D1U

10V2K

X-L1-G

P

C5604

SC

D1U

10V2K

X-L1-G

P

1 2 C5614SCD01U16V2KX-L1-GP

Cable


Cable

12 C5610SCD01U16V2KX-L1-GPNon cable



12

C5613

SC

10U25V

5KX

-GP

C5613

SC

10U25V

5KX

-GP

WWW.MANUALS.CLAN.SU

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of


Petra Uma -1

E-SATA/USB CHARGERA4


<Core Design>

Title


Date: Sheet of


Petra Uma -1



<Core Design>

Title


Date: Sheet of


Petra Uma -1



<Core Design>

ESATA Power

(Blanking)

WWW.MANUALS.CLAN.SU

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

AUD_HP1_JACK_R1

AUD_HP1_JACK_L1 AUD_HP1_JACK_L2

AUD_HP1_JACK_R2

COMBO_MIC_R1

COMBO_MIC

AUD_AGND

AUD_AGND

AUD_SPK_L-_R 29

AUD_SPK_L+_R 29AUD_SPK_R-_R 29AUD_SPK_R+_R 29

AUD_HP1_JD# 29

AUD_HP1_JACK_R2 29

AUD_HP1_JACK_L2 29

COMBO_MIC 29

Title


Date: Sheet of


Petra Uma -1

Audio JackA4

58 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1

Audio JackA4

58 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1

Audio JackA4

58 103Tuesday, July 10, 2012

<Core Design>

SSID = AUDIO

SA:change to be DGND

12

EC

5805S

C680P

50V2K

X-2G

P

DY

EC

5805S

C680P

50V2K

X-2G

P

DY

432

15

6

SPK1

ACES-CON4-29-GP

20.F1639.0042nd = 20.F1804.0043rd = 20.F1352.004

SPK1

ACES-CON4-29-GP

20.F1639.0042nd = 20.F1804.0043rd = 20.F1352.004

1

2

3

45

6

LOUT1

AUDIO-JK235-GP-U22.10270.6612nd = 22.10270.941

LOUT1

AUDIO-JK235-GP-U22.10270.6612nd = 22.10270.941

12

EC

5807S

C680P

50V2K

X-2G

P

DY

EC

5807S

C680P

50V2K

X-2G

P

DY

12

EC

5804S

C680P

50V2K

X-2G

P

DY

EC

5804S

C680P

50V2K

X-2G

P

DY

12

EC

5806S

C680P

50V2K

X-2G

P

DY

EC

5806S

C680P

50V2K

X-2G

P

DY

12

EC5803MLVG0402101NV05-GPDY


12R5801

549R3F-GPR5801

549R3F-GP

1 2R58030R2J-L-GPR58030R2J-L-GP

12



1 2R58020R2J-L-GPR58020R2J-L-GP

12

EC5802MLVG0402101NV05-GP

DY


DY

WWW.MANUALS.CLAN.SU

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

CONN_PWRCONN_PWR2

10M/100M/1G_LED#

LAN_ACT_LED#

MD

I0-

MD

I0+

MD

I1-

MD

I1+

MD

I2-

MD

I2+

MD

I3-

MD

I3+

XRF_TDC1

XR

F_T

DC

1

MCT_R

RJ45_7

RJ45_8

MCT1

MCT2

MCT3

MCT4

RJ45_3

RJ45_6

RJ45_4

RJ45_5

RJ45_1

RJ45_2

CONN_PWRCONN_PWR2

RJ45_7

RJ45_3RJ45_2

RJ45_5RJ45_8

RJ45_4

RJ45_6

RJ45_1

MC

T1

MC

T2

MC

T3

MC

T4

MC

T3

MC

T4

MC

T2

MC

T1

3D3V_S5

5V_S5

5V_S5

5V_S55V_S5

5V_CRT_S0

MDI3+31

MDI3-31

MDI0+31

MDI0-31

MDI2+31

MDI2-31

MDI1-31

MDI1+31

MDI3+31

MDI3-31

MDI1+31

MDI1-31

MDI2+31

MDI2-31

MDI0+31

MDI0-31

10M/100M/1G_LED# 31LAN_ACT_LED# 31

CRT_R 50

CRT_B 50CRT_DDCCLK_CON 50CRT_VSYNC_CON 50CRT_DDCDATA_CON 50CRT_HSYNC_CON 50

CRT_G 50

Title


Date: Sheet of


Petra Uma -1

LAN CONNECTORCustom

59 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1

LAN CONNECTORCustom

59 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1

LAN CONNECTORCustom

59 103Tuesday, July 10, 2012

<Core Design>

SSID = LAN

-1_20120301

12

C5 901

SC

D1U

10V2K

X-L1-G

PC

5 901S

CD

1U10V

2KX

-L1-GP

1

2

3 4

5

6

U5902

TVLST2304AD0-GP

U5902

TVLST2304AD0-GP

12


12

GDT4B88069X

9231T203-G

P

DYGDT4B

88069X9231T

203-GP

DY

12

EC5904SC

6D8P

50V2C

N-G

P

EC5904SC

6D8P

50V2C

N-G

P

12

GDT2B88069X

9231T203-G

P

DYGDT2B

88069X9231T

203-GP

DY

12

C5916SC1KP50V2JN-2GP

DY

C5916SC1KP50V2JN-2GP

DY

12

C5906

SC

1KP

50V2K

X-1G

PC

5906S

C1K

P50V

2KX

-1GP

12

C5907

SC

1KP

50V2K

X-1G

PC

5907S

C1K

P50V

2KX

-1GP

1

2

3 4

5

6

U5901

TVLST2304AD0-GP

U5901

TVLST2304AD0-GP

12

EC5902SC100P50V2JN-L-GP

DY


DY

12

EC5909SC

6D8P

50V2C

N-G

P

EC5909SC

6D8P

50V2C

N-G

P

234567891011121314151617181920

1

21222324

25

26

27

28

FT1

SKT-IO24-GP-U22.10342.0112nd = 22.10342.021

FT1

SKT-IO24-GP-U22.10342.0112nd = 22.10342.021

12

GDT1B88069X

9231T203-G

P

DYGDT1B

88069X9231T

203-GP

DY

12


12


12

EC5910SC

6D8P

50V2C

N-G

P

EC5910SC

6D8P

50V2C

N-G

P

12 3

4


1

2

3 4

5

6

U5903

TVLST2304AD0-GP

U5903

TVLST2304AD0-GP

12

EC5908SC

6D8P

50V2C

N-G

P

EC5908SC

6D8P

50V2C

N-G

P

12

C5905SC1KP2KV6KX-GP

C5905SC1KP2KV6KX-GP

12

EC5906SC

6D8P

50V2C

N-G

P

EC5906SC

6D8P

50V2C

N-G

P1

2


DY


DY

12

EC5905SC

6D8P

50V2C

N-G

P

EC5905SC

6D8P

50V2C

N-G

P

12


12

GDT3B88069X

9231T203-G

P

DYGDT3B

88069X9231T

203-GP

DY

1

2

3 4

5

6

U5904

TVLST2304AD0-GP

U5904

TVLST2304AD0-GP

12

EC5903SC

6D8P

50V2C

N-G

P

EC5903SC

6D8P

50V2C

N-G

P

12

EC5907SC

6D8P

50V2C

N-G

P

EC5907SC

6D8P

50V2C

N-G

P

1

2

3

5

4

6

7

8

9

10

11

12 13

14

15

16

17

18

19

20

21

22

23

24

1:1

1:1

1:1

1:1

XF5901

XFORM-24P-63-GP68.89240.30D2nd = 68.IH601.301

1:1

1:1

1:1

1:1

XF5901

XFORM-24P-63-GP68.89240.30D2nd = 68.IH601.301

WWW.MANUALS.CLAN.SU

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

RTC_PWR

SPI_HOLD_0#

SPI_SOSPI_WP#

RTC_AUX_S5

+RTC_VCC

3D3V_S5

3D3V_S5

3D3V_S5

3D3V_AUX_S5

SPI_CLK_R 21,27SPI_SO_R21,27

SPI_SI_R 21,27

SPI_CS0#_R21,27

Title


Date: Sheet of


Petra Uma -1

Flash/RTCCustom

60 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1

Flash/RTCCustom

60 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1

Flash/RTCCustom

60 103Tuesday, July 10, 2012

<Core Design>

Width=20mils

SSID = RTC

SSID = Flash.ROM

12

C6001

SC

10U6D

3V5K

X-1G

P

DY

C6001

SC

10U6D

3V5K

X-1G

P

DY

12


DY


DY

PWR1

GND2

NP1NP1

NP2NP2

RTC1

BAT-330DG02PSS0301CE-GP-U162.70001.0512nd = 62.70001.061

RTC1

BAT-330DG02PSS0301CE-GP-U162.70001.0512nd = 62.70001.061

1 2R60021KR2J-L2-GP

R60021KR2J-L2-GP

1 2R6001 33R2J-L1-GPR6001 33R2J-L1-GP

1 2 3 45678


CS#1

SO/SIO12

WP#3

GND4

VCC 8

HOLD# 7

SCLK 6

SI/SIO0 5

U6001

MX25L6406EM2I-12G-GP

2nd = 72.25Q64.B0172.25640.D01

U6001

MX25L6406EM2I-12G-GP

2nd = 72.25Q64.B0172.25640.D01

2

1

3

Q6001CH715FPT-GP

2nd = 83.00040.E8183.R0304.B81

Q6001CH715FPT-GP

2nd = 83.00040.E8183.R0304.B81

12

EC6002SC4D7P50V2CN-1GP

DYEC6002SC4D7P50V2CN-1GP

DY

12

EC

6003S

C4D

7P50V

2CN

-1GP

DY

EC

6003S

C4D

7P50V

2CN

-1GP

DY

12

EC

6001S

C4D

7P50V

2CN

-1GP

DY

EC

6001S

C4D

7P50V

2CN

-1GP

DY

12

C6002

SC

D1U

10V2K

X-L1-G

PC

6002S

CD

1U10V

2KX

-L1-GP

WWW.MANUALS.CLAN.SU

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

US

B20

_V2

USBPP0_C

USBPP9_C

USBPN9_C

USBPN0_C

USB20_V2

5V_S5USB20_V2

USB20_V2

USB20_V2

USB_PWR_EN#27,62

USB_PN018

USB_PP018

USB_PN918

USB_PP918

Title


Date: Sheet of


Petra Uma -1

USB Power SWA3

61 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1

USB Power SWA3

61 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1

USB Power SWA3

61 103Tuesday, July 10, 2012

<Core Design>

SSID = USB

Low Active 2A

Close to AUSB2

1

2345

6

7

8AUSB2

SKT-USB8-3-GP-U22.10321.B812nd = 22.10321.C413rd = 22.10321.E01

AUSB2


12

TC6102SE220U6D3VM-30-GP

77.52271.09L


77.52271.09L

1 2

34

L6101FILTER-4P-6-GPL6101FILTER-4P-6-GP

12

C6103

SC

10U10V

5ZY

-1GP

DY

C6103

SC

10U10V

5ZY

-1GP

DY

1

2345

6

7

8AUSB3


AUSB3


12

C6104

SC

D1U

16V2K

X-L-G

PC

6104S

CD

1U16V

2KX

-L-GP

1 2

34

L6102

FILTER-4P-6-GP

L6102

FILTER-4P-6-GP

12



GND1

IN#22

IN#33


U6102

SY6288DCAC-GP74.06288.A792nd = 74.02301.079

U6102

SY6288DCAC-GP74.06288.A792nd = 74.02301.079

12

C6106

SC

10U10V

5ZY

-1GP

DY

C6106

SC

10U10V

5ZY

-1GP

DY

12

C6102

SC

D1U

16V2K

X-L-G

PC

6102S

CD

1U16V

2KX

-L-GP

WWW.MANUALS.CLAN.SU

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

USB30_TP0_CUSB30_TN0_C

US

B30

_VC

CA

USB_PN1_LUSB_PP1_L

5V_S5

USB30_VCCA

USB30_VCCA

USB_PWR_EN#27,61

USB30_TN2 18USB30_TP2 18

USB30_RP2 18USB30_RN2 18

USB_PN118

USB_PP118

Title


Date: Sheet of


Petra Uma -1

USB 3.0 PortA3

62 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1

USB 3.0 PortA3

62 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1

USB 3.0 PortA3

62 103Tuesday, July 10, 2012

<Core Design>

GND

USB 2.0 D+

StdA_SSRX-

4

USB 3.0 Connector Pin definition

5

2

3

1

StdA_SSTX-

GND

POWER

USB 2.0 D-

SuperSpeed RX

6

7

8

9

StdA_SSRX+

StdA_SSTX+

SuperSpeed TX

Low Active 2A

12


77.52271.09L


77.52271.09L12 C6206SCD1U16V2KX-L-GP C6206SCD1U16V2KX-L-GP

12

C6203

SC

10U10V

5ZY

-1GP

DY

C6203

SC

10U10V

5ZY

-1GP

DY

12 C6207SCD1U16V2KX-L-GP C6207SCD1U16V2KX-L-GP

12



VBUS 1

GND4CHASSIS#1111CHASSIS#1010

GND_DRAIN7

D-2

D+3

STDA_SSRX+ 6STDA_SSRX- 5

STDA_SSTX+ 9STDA_SSTX- 8

CHASSIS#13 13CHASSIS#12 12

AUSB1SKT-USB13-23-GP

22.10339.5212nd = 22.10339.1413rd = 22.10321.Z41

AUSB1SKT-USB13-23-GP

22.10339.5212nd = 22.10339.1413rd = 22.10321.Z41

12

C6201

SC

D1U

16V2K

X-L-G

PC

6201S

CD

1U16V

2KX

-L-GP

GND1

IN#22

IN#33


U6201

SY6288DCAC-GP74.06288.A792nd = 74.02301.079

U6201

SY6288DCAC-GP74.06288.A792nd = 74.02301.079

1 2

34

L6201FILTER-4P-6-GPL6201FILTER-4P-6-GP

WWW.MANUALS.CLAN.SU

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of


Petra Uma -1

BluetoothA4


<Core Design>

Title


Date: Sheet of


Petra Uma -1

BluetoothA4


<Core Design>

Title


Date: Sheet of


Petra Uma -1

BluetoothA4


<Core Design>

SSID = User.InterfaceBluetooth Module conn.

ANNIE Bluetooth Module

(Blanking)

WWW.MANUALS.CLAN.SU

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of


Petra Uma -1

RESERVEDA4


<Core Design>

Title


Date: Sheet of


Petra Uma -1

RESERVEDA4


<Core Design>

Title


Date: Sheet of


Petra Uma -1

RESERVEDA4


<Core Design>

(Blanking)

WWW.MANUALS.CLAN.SU

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

USB_PN11 USB_PP11 3D3V_IOAC+5V_MINI_DEBUG

PC

IE_C

LK_W

LAN

PC

IE_C

LK_W

LAN

#

WIFI_RF_EN

WLAN_RST#

WLAN_WAKE#_R

E51_RXD_R

E51_TXD_R

WLAN_RST#

+5V_MINI_DEBUG

+5V_MINI_DEBUG

DEBUG_DET#

DEBUG_DET#

+5V_MINI_DEBUG

AP_DET#

WLAN_RST#

WLAN_RST#

3D3V_IOAC1D5V_S0

3D3V_IOAC

1D5V_S0

5V_S5

3D3V_S0

3D3V_IOAC3D3V_SRC

CLK_PCIE_WLAN_REQ# 20

PCIE_CLK_WLAN# 20

PCIE_CLK_WLAN 20

E51_RXD 27

E51_TXD 27WIFI_RF_EN 27

PCIE_RXN4 20

PCIE_RXP4 20

PCIE_TXN4 20

PCIE_TXP4 20

USB_PN11 18

USB_PP11 18

BLUETOOTH_EN27

WLAN_WAKE# 27

WLAN_PWR_EN#27

AP_DET# 27

PLT_RST# 5,18,27,31,36,71,97

WLAN_PERST# 27

Title


Date: Sheet of


Petra Uma -1

MINICARD(WLAN)/ITP CONNA3

65 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1


65 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1


65 103Tuesday, July 10, 2012

<Core Design>

SSID = Wireless Mini Card Connector(802.11a/b/g/n)

-1_20120223

-1_20120301

12

EC

6507S

C68P

50V2JN

-1GP

DY

EC

6507S

C68P

50V2JN

-1GP

DY

12

C6505SC10U6D3V5KX-1GPC6505SC10U6D3V5KX-1GP

12

R6503100KR2J-4-GPR6503100KR2J-4-GP

1 2R65040R2J-L-GPR65040R2J-L-GP

1 2R6501 0R0402-PADR6501 0R0402-PAD 12

EC

6512S

C8P

250V2C

C-G

P

DY

EC

6512S

C8P

250V2C

C-G

P

DY

12

EC

6509S

C68P

50V2JN

-1GP

DY

EC

6509S

C68P

50V2JN

-1GP

DY

12

EC

6511S

C56P

50V2JN

-2GP

DY

EC

6511S

C56P

50V2JN

-2GP

DY

12

C6503

SC

10U6D

3V5K

X-1G

PC

6503S

C10U

6D3V

5KX

-1GP

12

EC

6513S

C8P

250V2C

C-G

P

DY

EC

6513S

C8P

250V2C

C-G

P

DY1 2R6502 0R0402-PADR6502 0R0402-PAD1

2

C6501SC1U10V2KX-1GP

IOAC

C6501SC1U10V2KX-1GP

IOAC

12

C6502

SC

D1U

16V2K

X-L-G

PC

6502S

CD

1U16V

2KX

-L-GP

12

C6508MLVG0402220NV05BP-GP-U

DY

C6508MLVG0402220NV05BP-GP-U

DY

12

345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152

53

54

NP1

NP2

WLAN1

SKT-MINI52P-110-GP62.10043.G012nd = 62.10043.C31

WLAN1

SKT-MINI52P-110-GP62.10043.G012nd = 62.10043.C31

12

C6504

SC

D1U

16V2K

X-L-G

PC

6504S

CD

1U16V

2KX

-L-GP

1 2R6505

0R2J-L-GPDY

R6505

0R2J-L-GPDY

G

S

D

Q6502

2N7002K-2-GP

84.2N702.J312nd = 84.2N702.031

Q6502

2N7002K-2-GP

84.2N702.J312nd = 84.2N702.031

12

EC

6503S

C68P

50V2JN

-1GP

DY

EC

6503S

C68P

50V2JN

-1GP

DY

SD

GG

D

Q6501DMP2130L-7-GP

84.02130.031

2nd = 84.03413.A31

G

D

Q6501DMP2130L-7-GP

84.02130.031

2nd = 84.03413.A31

GND1

IN#22

IN#33


U6501

SY6288DCAC-GP74.06288.A79

IOAC

2nd = 74.02301.079

U6501

SY6288DCAC-GP74.06288.A79

IOAC

2nd = 74.02301.079

1 2R6511

0R2J-L-GPIOAC

R6511

0R2J-L-GPIOAC

12

EC6510SC10P50V2JN-4GP

DYEC6510SC10P50V2JN-4GP

DY

1 2

R6512

0R2J-L-GP

non-IOACR6512

0R2J-L-GP

non-IOAC

WWW.MANUALS.CLAN.SU

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of


Petra Uma -1

WWAN ConnectorA4


<Core Design>

Title


Date: Sheet of


Petra Uma -1

WWAN ConnectorA4


<Core Design>

Title


Date: Sheet of


Petra Uma -1

WWAN ConnectorA4


<Core Design>

SSID = Wireless Mini Card Connector(WWAN)

(Blanking)

WWW.MANUALS.CLAN.SU

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of


Petra Uma -1

ReservedA4


<Core Design>

Title


Date: Sheet of


Petra Uma -1

ReservedA4


<Core Design>

Title


Date: Sheet of


Petra Uma -1

ReservedA4


<Core Design>

(Blanking)

WWW.MANUALS.CLAN.SU

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DC_BATFULL#_Q

FRONT_PWRLED#_R

DC_BATFULL#_R

STDBY_LED#_Q

STDBY_LED#_R

CHARGE_LED#_Q

CHARGE_LED#_R

FRONT_PWRLED#_Q

DC_BATFULL#_Q

CHARGE_LED#_Q

FRONT_PWRLED#_Q

STDBY_LED#_Q

KBC_PWRBTN#

5V_AUX_S5

5V_S5

PWRLED27

STDBY_LED27

DC_BATFULL27

CHARGE_LED27

FRONT_PWRLED#_Q 82

KBC_PWRBTN# 27,29,82

Title


Date: Sheet of


Petra Uma -1

LED Bard/Power ButtonCustom

68 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1


68 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1


68 103Tuesday, July 10, 2012

<Core Design>

Power button LED

Battery LED2(DC_BATFULL)

Battery LED1(CHARGE)

Power STDBY_LED

21

3R1

R2

Q6801

LTC043ZUB-FS8-GP

2nd = 84.00143.E1K84.00043.011

R1

R2

Q6801

LTC043ZUB-FS8-GP

2nd = 84.00143.E1K84.00043.011

1 2R6802 330R2F-GPR6802 330R2F-GP

1 2R6801 330R2F-GPR6801 330R2F-GP

21

3R1

R2

Q6802

LTC043ZUB-FS8-GP

2nd = 84.00143.E1K84.00043.011

R1

R2

Q6802

LTC043ZUB-FS8-GP

2nd = 84.00143.E1K84.00043.011

1 2R6803 330R2F-GPR6803 330R2F-GP

12

EC6801MLVG0402101NV05-GPEC6801MLVG0402101NV05-GP

21

3R1

R2

Q6808

LTC043ZUB-FS8-GP

2nd = 84.00143.E1K84.00043.011

R1

R2

Q6808

LTC043ZUB-FS8-GP

2nd = 84.00143.E1K84.00043.011

13

2

CHLED1

LED-BO-5-GP-U1

83.00326.A70CHLED1

LED-BO-5-GP-U1

83.00326.A70

13

2

PLED1

LED-BO-5-GP-U1

83.00326.A70PLED1

LED-BO-5-GP-U1

83.00326.A70

21

3R1

R2

Q6805

LTC043ZUB-FS8-GP

2nd = 84.00143.E1K84.00043.011

R1

R2

Q6805

LTC043ZUB-FS8-GP

2nd = 84.00143.E1K84.00043.011

1 2R6804 330R2F-GPR6804 330R2F-GP

WWW.MANUALS.CLAN.SU

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

TP_CLKTP_DATA

KR

OW

7

KR

OW

0

KR

OW

5

KR

OW

3

KR

OW

1

KR

OW

6

KR

OW

4

KR

OW

2

KC

OL9

KC

OL7

KC

OL5

KC

OL8

KC

OL4

KC

OL6

KC

OL1

1K

CO

L12

KC

OL3

KC

OL2

KC

OL1

0

KC

OL1

6

KC

OL1

4K

CO

L13

KC

OL1

5

KC

OL1

7

KC

OL1

KC

OL0

KB_LED_PWM_D

KB_BL_DET_R

KB_BL_PWM_R

3D3V_S0

3D3V_S0

5V_S0

KROW[0..7] 27

KCOL[0..17] 27

TPCLK27TPDATA27

PCH_SMBDATA14,15,20PCH_SMBCLK14,15,20TP_IN#18

KB_BL_DET 27

KB_BL_PWM27

Title


Date: Sheet of


Petra Uma -1

Key Board/Touch PadA3

69 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1


69 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1


69 103Tuesday, July 10, 2012

<Core Design>

SSID = KBC

TOUCH PADInternal KeyBoardConnector

上上上上上上上上上上上上

0.5 pitch

1.0 pitch

-1_20120302A

1

2345678

9

10

TPAD1ACES-CON8-37-GP

14

20.K0637.008


14

20.K0637.008

1

234

5

6

KB2

ACES-CON4-50-GP

20.K0722.004

KB2

ACES-CON4-50-GP

20.K0722.004

1 2R6901100KR2J-4-GPR6901100KR2J-4-GP

27 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 28

KB1ETY-CON26-7-GP

20.K0733.0262nd = 20.K0752.026KB1

ETY-CON26-7-GP20.K0733.026

2nd = 20.K0752.026

G

DS

Q6901AO3418-GP

84.03418.031

Q6901AO3418-GP

84.03418.031

12


DYC6902

SCD1U10V2KX-L1-GP

DY

12

EC

6902S

C56P

50V2JN

-2GP

EC

6902S

C56P

50V2JN

-2GP

1

2345678

9

10


15

20.K0667.0082nd = 20.K0665.008


15

20.K0667.0082nd = 20.K0665.008

12

R6902200KR2F-L-GPR6902200KR2F-L-GP

1 234


1 2

R6903

0R2J-L-GP

R6903

0R2J-L-GP

12 3

4


12

C6901SCD1U25V2KX-GPC6901SCD1U25V2KX-GP

WWW.MANUALS.CLAN.SU

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

LID_CLOSE#_1

3D3V_AUX_KBC

LID_CLOSE#27

Title


Date: Sheet of


Petra Uma -1

Hall SensorA4

70 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1

Hall SensorA4

70 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1

Hall SensorA4

70 103Tuesday, July 10, 2012

<Core Design>

1 2R7002100R2J-L-GP

R7002100R2J-L-GP

VDD1

VOUT2

GND 3

LID1APX9132HAI-TRG-GP

1st = 74.05712.0BB2nd = 74.01803.07B

LID1APX9132HAI-TRG-GP

1st = 74.05712.0BB2nd = 74.01803.07B

12



12

C7001SCD047U16V2KX-1-GP

DY C7001SCD047U16V2KX-1-GP

DY

WWW.MANUALS.CLAN.SU

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

3D3V_S0

PLT_RST#5,18,27,31,36,65,97

CLK_PCI_LPC18

LPC_FRAME#21,27

LPC_AD021,27LPC_AD121,27LPC_AD221,27LPC_AD321,27

Title


Date: Sheet of


Petra Uma -1

Dubug connectorA4

71 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1

Dubug connectorA4

71 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1

Dubug connectorA4

71 103Tuesday, July 10, 2012

<Core Design>

20.D0183.110

123456789

101112

DB1

MLX-CON10-7-GP

DY

DB1

MLX-CON10-7-GP

DY

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ReservedA4


<Core Design>

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ReservedA4


<Core Design>

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ReservedA4


<Core Design>

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ReservedA4


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ReservedA4


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SD_CLK

CARD_3V3

SD_CLK31SD_CMD31

SD_WP31SD_CD#31

SD_DATA0 31SD_DATA1 31SD_DATA2 31

SD_DATA3 31

Title


Date: Sheet of


Petra Uma -1

CARD Reader CONNA4

74 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1

CARD Reader CONNA4

74 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1

CARD Reader CONNA4

74 103Tuesday, July 10, 2012

<Core Design>

SSID = SDIO SD/MMC Card Reader

Layout 40 mil1

2

C7401SC4D7U6D3V3KX-L-GPC7401SC4D7U6D3V3KX-L-GP

CD/DAT3 1CMD2

VSS1 3

VDD4

CLK5

VSS2 6

DAT0 7

DAT1 8

DAT2 9

CARD_DETECT10WRITE_PROTECT11

1212

1313

NP1 NP1

NP2 NP2

CARD1

SDCARD-13P-2-GP

62.10051.C412nd = 62.10051.D71

CARD1

SDCARD-13P-2-GP

62.10051.C412nd = 62.10051.D71

12

EC7401SC33P50V2JN-3GPDYEC7401SC33P50V2JN-3GPDY

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Petra Uma -1

New CardA4


<Core Design>

Title


Date: Sheet of


Petra Uma -1

New CardA4


<Core Design>

Title


Date: Sheet of


Petra Uma -1

New CardA4


<Core Design>

SSID = ExpressCard

+1.5V_CARD Max. 650mA, Average 500mA.+3.3V_CARD Max. 1300mA, Average 1000mA+3.3V_CARDAUX Max. 275mA

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ReservedA4


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ReservedA4


<Core Design>

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ReservedA4


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ReservedA4


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Petra Uma -1

ReservedA4


<Core Design>

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ReservedA4


<Core Design>

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ReservedA4


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ReservedA4


<Core Design>

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ReservedA4


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Petra Uma -1

G- Sensor A4


<Core Design>

Title


Date: Sheet of


Petra Uma -1

G- Sensor A4


<Core Design>

Title


Date: Sheet of


Petra Uma -1

G- Sensor A4


<Core Design>

SSID = User.Interface

Free Fall Sensor

Note- no via, trace, under the sensor (keep out area around 2mm)- stay away from the screw hole or metal shield soldering joints- design PCB pad based on our sensor LGA pad size (add 0.1mm)- solder stencil opening to 90% of the PCB pad size- mount the sensor near the center of mass of the NB as possible as you can

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ReservedA4


<Core Design>

Title


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Petra Uma -1

ReservedA4


<Core Design>

Title


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Petra Uma -1

ReservedA4


<Core Design>

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ReservedA4


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ReservedA4


<Core Design>

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5V_S5

FRONT_PWRLED#_Q 68KBC_PWRBTN# 27,29,68

Title


Date: Sheet of


Petra Uma -1

IO Board ConnectorA4

82 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1


82 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1


82 103Tuesday, July 10, 2012

<Core Design>

1

23456

7

8

PWRCN1

ACES-CON6-52-GP

20.K0721.0062nd = 20.K0382.006

PWRCN1

ACES-CON6-52-GP

20.K0721.0062nd = 20.K0382.006

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Petra Uma -1

GPU_PCIE/STRAPPING(1/5)A4


<Core Design>

Title


Date: Sheet of


Petra Uma -1



<Core Design>

Title


Date: Sheet of


Petra Uma -1



<Core Design>

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C C

B B

A A

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A A

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Petra Uma -1

GPU_DPPWR/GND(5/5)A4


<Core Design>

Title


Date: Sheet of


Petra Uma -1



<Core Design>

Title


Date: Sheet of


Petra Uma -1



<Core Design>

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B B

A A

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A A

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A A

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Petra Uma -1

RT8208F_+VGA_COREA4


<Core Design>

Title


Date: Sheet of


Petra Uma -1

RT8208F_+VGA_COREA4


<Core Design>

Title


Date: Sheet of


Petra Uma -1

RT8208F_+VGA_COREA4


<Core Design>

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Petra Uma -1

DISCRETE VGA POWERA4


<Core Design>

Title


Date: Sheet of


Petra Uma -1



<Core Design>

Title


Date: Sheet of


Petra Uma -1



<Core Design>

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D D

C C

B B

A A

Title


Date: Sheet of


Petra Uma -1

LVDS_SwitchA4


<Core Design>

Title


Date: Sheet of


Petra Uma -1

LVDS_SwitchA4


<Core Design>

Title


Date: Sheet of


Petra Uma -1

LVDS_SwitchA4


<Core Design>

LVDS Channel A

Panel BL brightness/Power En/BL En

(Blanking)

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Petra Uma -1

CRT_SwitchA4


<Core Design>

Title


Date: Sheet of


Petra Uma -1

CRT_SwitchA4


<Core Design>

Title


Date: Sheet of


Petra Uma -1

CRT_SwitchA4


<Core Design>

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Petra Uma -1

TOUCH PANELA4


<Core Design>

Title


Date: Sheet of


Petra Uma -1

TOUCH PANELA4


<Core Design>

Title


Date: Sheet of


Petra Uma -1

TOUCH PANELA4


<Core Design>

SSID = SDIO

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B B

A A

5V_S5

3D3V_AUX_S5

3D3V_S5

3D3V_S0

1D05V_VTT

DCBATOUT DCBATOUT_2 PWR_VCCCORE1_DCBATOUT 3D3V_S0

1D5V_S3 5V_S0 5V_S5

AUD_AGND

AD_JK

BT+ DCBATOUT LCDVDD

PLT_RST#5,18,27,31,36,65,71

S5_ENABLE27,36

PM_PWRBTN#19,27

H_CPUPWRGD5,22,36

Title


Date: Sheet of


Petra Uma -1

UNUSED PARTS/EMI CapacitorsA3

97 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1


97 103Tuesday, July 10, 2012

<Core Design>

Title


Date: Sheet of


Petra Uma -1


97 103Tuesday, July 10, 2012

<Core Design>

Test Point放放放放放放放放Dimm Door打打打打打打打打打打打打打打打打打打打打打打打打

Check test pointCPU

-1_20120301-1_20120301

EC change

12

EC

9704S

CD

1U50V

3KX

-GP

DY

EC

9704S

CD

1U50V

3KX

-GP

DY

1 AFTP9AFTP9

1

H11HOLE335R115-GPH11HOLE335R115-GP

12

EC

9714S

CD

1U50V

3KX

-GP

DY

EC

9714S

CD

1U50V

3KX

-GP

DY

1

H1

HO

LE355X

355R111-S

1-GP

H1

HO

LE355X

355R111-S

1-GP

12

EC

9732S

CD

1U50V

3KX

-GP

DY

EC

9732S

CD

1U50V

3KX

-GP

DY

1H12HOLE335R115-GPH12HOLE335R115-GP

12

EC

9715S

CD

1U50V

3KX

-GP

DY

EC

9715S

CD

1U50V

3KX

-GP

DY

12

EC

9707S

CD

1U50V

3KX

-GP

EC

9707S

CD

1U50V

3KX

-GP

12

EC

9716S

CD

1U50V

3KX

-GP

DY

EC

9716S

CD

1U50V

3KX

-GP

DY

12

EC

9706S

CD

1U10V

2KX

-L1-GP

DY

EC

9706S

CD

1U10V

2KX

-L1-GP

DY

12

EC

9711S

CD

1U10V

2KX

-L1-GP

DY

EC

9711S

CD

1U10V

2KX

-L1-GP

DY

12

EC

9712S

CD

1U10V

2KX

-L1-GP

DY

EC

9712S

CD

1U10V

2KX

-L1-GP

DY

1

HS3ST

F237R

128H41-G

P

34.4

TU

18.0

012n

d =

34.

4TU

18.1

01

HS3ST

F237R

128H41-G

P

34.4

TU

18.0

012n

d =

34.

4TU

18.1

01

12

EC

9713S

CD

1U10V

2KX

-L1-GP

DY

EC

9713S

CD

1U10V

2KX

-L1-GP

DY

12

EC

9726S

CD

1U10V

2KX

-L1-GP

EC

9726S

CD

1U10V

2KX

-L1-GP

1

H3

HO

LE355X

355R111-S

1-GP

H3

HO

LE355X

355R111-S

1-GP

12

EC

9702S

CD

1U50V

3KX

-GP

DY

EC

9702S

CD

1U50V

3KX

-GP

DY

1 AFTP7AFTP7

12

EC

9721S

CD

1U50V

3KX

-GP

EC

9721S

CD

1U50V

3KX

-GP

12

EC

9722S

CD

1U50V

3KX

-GP

EC

9722S

CD

1U50V

3KX

-GP

1 AFTP13AFTP13

12

EC

9717S

CD

1U10V

2KX

-L1-GP

DY

EC

9717S

CD

1U10V

2KX

-L1-GP

DY

12

EC

9701S

CD

1U50V

3KX

-GP

EC

9701S

CD

1U50V

3KX

-GP

12

EC

9723S

CD

1U50V

3KX

-GP

DY

EC

9723S

CD

1U50V

3KX

-GP

DY

1


1

HS2ST

F237R

128H41-G

P

34.4

TU

18.0

012n

d =

34.

4TU

18.1

01

HS2ST

F237R

128H41-G

P

34.4

TU

18.0

012n

d =

34.

4TU

18.1

01

1 2


DYEC9728MLVG0402101NV05-GP

DY

12

EC

9718S

CD

1U10V

2KX

-L1-GP

DY

EC

9718S

CD

1U10V

2KX

-L1-GP

DY

1

H5

HO

LE355X

355R111-S

1-GP

H5

HO

LE355X

355R111-S

1-GP

1 AFTP8AFTP8

1 2


DY


DY

1 AFTP11AFTP11

12

EC

9708S

CD

1U10V

2KX

-L1-GP

DY

EC

9708S

CD

1U10V

2KX

-L1-GP

DY1


12

EC

9730S

CD

1U50V

3KX

-GP

DY

EC

9730S

CD

1U50V

3KX

-GP

DY

12

EC

9725S

CD

1U10V

2KX

-L1-GP

DY

EC

9725S

CD

1U10V

2KX

-L1-GP

DY

12

EC

9719S

CD

1U10V

2KX

-L1-GP

EC

9719S

CD

1U10V

2KX

-L1-GP

1

H2

HO

LE355X

355R111-S

1-GP

H2

HO

LE355X

355R111-S

1-GP

1 AFTP1AFTP1

1

H4

HO

LE355X

355R111-S

1-GP

H4

HO

LE355X

355R111-S

1-GP

12

EC

9705S

CD

1U10V

2KX

-L1-GP

DY

EC

9705S

CD

1U10V

2KX

-L1-GP

DY

1

HS1ST

F237R

128H41-G

P

34.4

TU

18.0

012n

d =

34.

4TU

18.1

01

HS1ST

F237R

128H41-G

P

34.4

TU

18.0

012n

d =

34.

4TU

18.1

01

1 AFTP12AFTP12

1 AFTP10AFTP10

12

EC

9731S

CD

1U50V

3KX

-GP

DY

EC

9731S

CD

1U50V

3KX

-GP

DY

12

EC

9720S

CD

1U10V

2KX

-L1-GP

DYE

C9720

SC

D1U

10V2K

X-L1-G

PDY

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3

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2

2

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1

D D

C C

B B

A A

Title


Date: Sheet of


Petra Uma -1

Change HistoryA3


<Core Design>

Title


Date: Sheet of


Petra Uma -1

Change HistoryA3


<Core Design>

Title


Date: Sheet of


Petra Uma -1

Change HistoryA3


<Core Design>

Power SequencePU4601

1D5V_S3PM_SLP_S4#

0D75V_EN

RUNPWROK

1D5V_S3

0D75V_S0

PU4501

1D05V_S0 1.05VTT_PWRGD

1D05V_VTT

U4801

0D85V_S0 0D85V_S0

ALL_POWER_OK

U?

EC S0_PWR_GOOD

U?

CPU_CORE

VCC_GFXCORE

VCC_CORE

ALL_POWER_OK

U?

PCH PM_DRAM_PWRGD

U?

AND GATE

ALL_POWER_OK

VDDPWRGOOD

U?

CPU

H_CPUPWRGD

H_CPU_SVIDCLK

H_CPU_SVIDCLK

IMVP_PWRGD

U?

AND GATE

S0_PWR_GOOD

SYS_PWROK

PLT_RST#

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4

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3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of


Petra Uma -1

Power SequenceA1


<Core Design>

Title


Date: Sheet of


Petra Uma -1

Power SequenceA1


<Core Design>

Title


Date: Sheet of


Petra Uma -1

Power SequenceA1


<Core Design>

+1.05V_VTT

T3

1.0V_RUN_VGA_EN(Discrete only)------Delay 4ms

T41

+1.05V_VTT

SUS_PWR_DN_ACKPCH to KBC GPI94

+KBC_PWR

+PWR_SRC

H_VTTPWRGD

S5_ENABLE

KBC GPIO43 to PCH

1.5CPU_1.05VTT_PWRGD

T39

PCH to KBC GPI94

TPS51125 to KBC GPIO46

IMVP_VR_ON

(DC mode)(AC mode)

KBC GPO53 to ISL62883

+5V_ALW

+VCC_CORE

T48

PM_DRAM_PWRGD

>30us

+3.3V_RUN_VGA_EN(Discrete only)-->DY reservedKBC GPI95

SUS_PWR_DN_ACK

-->Reserved for sequence

KBC GPIO66 to APL5930

(for S3 Reduction)

+1.5V_RUN_CPU T49 >100ns>1ms

KBC GPIO43 to PCH

CK_PWRGD

+3.3V_ALW

T44 >1ms

AC

ISL62883 to CLOCKGEN

T42

KBC_PWRBTN_EC# GPIO3

1.8V_VGA_RUN_EN(Discrete only)------Delay 5ms

43

T14

H_PWRGD

T50

PLT_RST#

IMVP_PWRGD

PLTRST_DELAY#

ISL62884 to KBC GPO14

T54

+1.8V_RUN_VGA(Discrete only)

H_CPURST#

KBC GPIO45

T45

KBC LRESET#

GFX_VR_EN(UMA only)


T4

T35

T36

T5

T37

T38

PM_PWROK

EC_ENABLE# (GPIO51) keep low

3V_5V_POK

( >99ms )

+1.8V_RUN

T25

T6

CPU to TPS51611

GFX_CORE_EN(Discrete only)------Delay 5ms

PM_PWRBTN#

T8T9

T26

PCH_SUSCLK_KBCPCH to KBC GPIO01

RUNPWROK

KBC GPIO71 to RT8208B

T11

KBC GPO16 to LAN

T12

PCH_SUSCLK_KBC

+V_DDR_REF(0.9V)

PCH to KBC GPIO00

+15V_ALW

+0.75V_DDR_VTT

+5V_RUN

+15V_ALW

TPS51125 to KBC GPIO46

+1.5V_RUN


+CPU_GFX_CORE(UMA only)

+3.3V_RUN

Intel-Power Up Sequence

KBC_PWRBTN_EC#

PM_SLP_S3#

T8

+3.3V_LAN

TPS51218 to KBC GPI34

PCH_RSMRST#(EC Delay 40ms)

+5V_ALW

S5_ENABLE

PM_SLP_S4#

+3.3V_ALW KBC GPIO36 control

+3.3V_RTC_LDO

T4

PM_PWRBTN#

KBC_PWRBTN_EC#

+VGA_CORE(Discrete only)

AC

KBC GPO84 to PCH

T13

UMA GFX CORE Power

CPU CORE Power<3ms

T13

T5

T15

T16

PCH_RTCRST#

+PWR_SRC

+RTC_VCC

T2

3V_5V_POK

T1

+1.5V_SUS

T3

PCH_RTCRST#

+RTC_VCCT1

T9

<200ms

T11

T12

>10ms

>10ms

>1ms

T21

+5V_ALW & +3.3V_ALW need meet 0.7V difference

+5V_RUN & +3.3V_RUN need meet 0.7V difference

H_PWRGD

T10

T6

+5VALW_PCH_VCC5REFSUS

PM_PWRBTN#

AC

T7 +5V_ALW & +3.3V_ALW need meet 0.7V difference

+5VALW_PCH_VCC5REFSUS

Press Power button

+5VS_PCH_VCC5REF

T7

PM_LAN_ENABLE

T22

T28

T29

T30

T19

T31

T32

T33

T34

T20

AC_PRESENT_EC


T23

T24

T17

T18

T27

KBC GPO84 to PCH

CLK_CPU_BCLKCLKIN_BCLK(from CK505) stable

>1ms

T47

+VCC_CORE

T53

T55

0.05ms< <650ms

3ms< <20ms

T461.5CPU_1.05VTT_PWRGD

>5ms

T52

H_VTTPWRGD>1ms

PM_PWROKT51 >1ms

>1ms

1.5CPU_1.05VTT_PWRGD(after delay 1ms GPI96-VDDPWRGOOD_EC output for s3 reduction)

PCH_RSMRST#

Press Power button

+3.3V_RTC_LDO

T2

red word: KBC GPIO

T40

KBC_PWRBTN_EC# GPIO3KBC GPIO36 control

3V_5V_POK

Delay 10ms

KBC GPIO47 to PCH

T10

+1.05V_VTT

1.0V_RUN_VGA_EN(Discrete only)

H_VTTPWRGD

>30us

+3.3V_RUN_VGA_EN(Discrete only)-->DY reservedKBC GPI95

-->Reserved for sequence

KBC GPIO66 to APL59301.8V_VGA_RUN_EN(Discrete only)

T14

DC



T35

T36

T37

T38

+1.8V_RUN

T25

GFX_CORE_EN(Discrete only) T26

RUNPWROK

KBC GPIO71 to RT8208B

KBC GPO16 to LAN

+V_DDR_REF(0.9V)

+0.75V_DDR_VTT

+5V_RUN

+1.5V_RUN


+3.3V_RUN

PM_SLP_S3#

+3.3V_LAN

TPS51218 to KBC GPI34

PM_SLP_S4#

+VGA_CORE(Discrete only)

T15

T16

+1.5V_SUS

>1ms

T21

+5V_RUN & +3.3V_RUN need meet 0.7V difference

H_PWRGD

+5VS_PCH_VCC5REF

PM_LAN_ENABLE

T22

T28

T29

T30

T19

T31

T32

T33

T34

T20


T23

T24

T17

T18

T27

1.5CPU_1.05VTT_PWRGD(after delay 1ms GPI96-VDDPWRGOOD_EC output for s3 reduction)

PCH_RSMRST#

T41

+1.05V_VTT

1.5CPU_1.05VTT_PWRGD

T39

IMVP_VR_ONKBC GPO53 to ISL62883

+VCC_CORE

T48

PM_DRAM_PWRGD (for S3 Reduction)

+1.5V_RUN_CPU T49 >100ns>1ms

CK_PWRGD

T44 >1ms

ISL62883 to CLOCKGEN

T42

43

H_PWRGD

T50

PLT_RST#

IMVP_PWRGD

PLTRST_DELAY#

ISL62884 to KBC GPO14

T54

H_CPURST#

KBC GPIO45

T45

KBC LRESET#

GFX_VR_EN(UMA only)

PM_PWROK

( >99ms )

CPU to TPS51611

+CPU_GFX_CORE(UMA only)UMA GFX CORE Power

CPU CORE Power<3ms

CLK_CPU_BCLKCLKIN_BCLK(from CK505) stable

>1ms

T47

+VCC_CORE

T53

T55

0.05ms< <650ms

3ms< <20ms

T461.5CPU_1.05VTT_PWRGD

>5ms

T52

H_VTTPWRGD>1ms

PM_PWROKT51 >1ms

>1ms

T40

Delay 10ms

KBC GPIO47 to PCH

red word: KBC GPIO

WWW.MANUALS.CLAN.SU

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of


Petra Uma -1

Power Block DiagramA3


<Core Design>

Title


Date: Sheet of


Petra Uma -1



<Core Design>

Title


Date: Sheet of


Petra Uma -1



<Core Design>

Charger

BQ24747+AD

Adapter

Battery

RT8223MZQW

5V_AUX_S5

Regulator LDO Switch

5V_S53D3V_AUX_S5

SY6288DCAC

USB30_VCCA

3D3V_SRC

ISL95836HRTZrev 1.7

VCC_CORE

TPS51218DSCR

DCBATOUT

VCC_GFXCORE

For UMA

RT8207LZQW

0D75V_S0DDR_VREF_S3

1D5V_S0

1D5V_S3

Power Shape

AO4468

P1403EV8

5V_S0

3D3V_DAC_S0

AME8818BEEV330Z

G978

0D85V_S0

USB3.0 Power USB Power

1D05V_VTT

1D5V_DDR_S0

SY6288DCAC

USB20_V2

AO4468

3D3V_S0

3D3V_CARD_S0SY6288C6AAC

LCDVDD

DMP2305U

+KBC_PWR

RT9025

1D8V_S0

AO4468

WLAN Power

SY6288DCAC

3D3V_IOAC

SY6288CAAC

3D3V_S5

WWW.MANUALS.CLAN.SU

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

Title


Date: Sheet of


Petra Uma -1

SMBUS Block DiagramA2


<Core Design>

Title


Date: Sheet of


Petra Uma -1



<Core Design>

Title


Date: Sheet of


Petra Uma -1



<Core Design>

SML0CLK

SML0DATA

SML0_CLK

SML0_DATA

BQ24747SCL

SDA

SRN0J-6-GP

UMA

UMA

DISCRT_DDC_DATA

CRT_DDC_CLK

‧

3D3V_S0

SRN2K2J-1-GP

LVDS_DDC_CLK_R

LVDS_DDC_DATA_R

LCD_SMBCLK

SRN0J-6-GP

SRN10KJ-5-GP

SRN4K7J-8-GP

SRN2K2J-1-GP

LCD_SMBDATA

TPDATA

TPCLK

5V_S0

‧

LCDVDD_eDP

‧

‧

‧

TouchPad Conn.

‧‧

TPDATA

TPCLKPSCLK1

PSDAT1

LCD CONN

PCH SMBus Block Diagram

PCH

SMBCLK

SMBDATA

GPIO74/SDA2

GPIO73/SCL2

KBC

CLK_SMB

eDPSCL

SDA

3D3V_S0

‧

SRN2K2J-1-GP

3D3V_S5

‧

‧‧

SRN2K2J-1-GP

3D3V_S0

2N7002SPT

‧

‧‧

DAT_SMB

SML1_CLK

SML1_DATA To KBC & eDPSML1DATA

SML1CLK

BAT_SCL

BAT_SDA

2N7002DW-1-GP

‧

PCH_SMBCLK

PCH_SMBDATA

‧

3D3V_S0

SRN2K2J-1-GP

TPDATA

TPCLK

FT1 ConnCRT_DDCCLK_CON

CRT_DDCDATA_CON

CRT_DDC_CLK

CRT_DDC_DATA5V_S0

‧

SRN10KJ-6-GP

MinicardWLANSMB_DATA

SMB_CLK

GPIO17/SCL1

GPIO22/SDA1

SML1_CLK

SML1_DATA

SMBus Address:A0

SMBus Address:A4

DIMM 1SCL

SDA

3D3V_AUX_KBC

‧

DIMM 2SCL

SDASMBus address:16

SMB_CLK

SMB_DATA

PCH_SMBCLK

PCH_SMBDATA

BATA_SCL_1

BATA_SDA_1

KBC SMBus Block Diagram

Battery Conn.

PCH_SMBDATA

PCH_SMBCLK

‧‧

‧

3D3V_S0

SRN2K2J-1-GP

SDVO_CTRLDATA

SDVO_CTRLCLK

5V_S0

‧

SRN1K5J-GP

PCH_HDMI_DATA

PCH_HDMI_CLK

SRN2K2J-8-GP

3D3V_S5

‧

Level Shift

DDC_CLK_HDMI

DDC_DATA_HDMI

SMBus address:XX

NPCE885P

SRN100J-3-GP

L_DDC_DATA

L_DDC_CLK

HDMI CONN

LVDS_DDC_CLK

LVDS_DDC_DATA

CLK

DATA

PCHSCL

SDA

‧‧

3D3V_S0

3D3V_S5

‧

SRN2K2J-1-GP

LCDVDD_eDP

2N7002DW-1-GP

‧

SMBus address:12

WWW.MANUALS.CLAN.SU

A

A

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

Title


Date: Sheet of


Petra Uma -1

Thermal/Audio Block DiagramCustom


<Core Design>

Title


Date: Sheet of


Petra Uma -1



<Core Design>

Title


Date: Sheet of


Petra Uma -1



<Core Design>

OTZ2N7002THERM_SYS_SHDN#

SD

G

IMVP_PWRGD

PURE_HW_SHUTDOWN#

VR

3V/5VENPGOD

T8

AMIC

Put under CPU(T8 HW shutdown)

P2800_DXP

P2800_DXN

MMBT3904-3-GP

Place near CPUPWM CORE

Audio Block Diagram

CodecALC271

CMBOLOUT

SPEAKER

PCHSMBUS

SML1_CLK

SML1_DATA

PAGE28

SPKR_PORT_D_L-

SPKR_PORT_D_R+

Thermal Block Diagram

ThermalNCT7718W

DXP

DXN

MMBT3904-3-GP

SC2200P50V2KX-2GP

AUD_HP1_JACK_R1

AUD_HP1_JACK_L1

COMBO_MIC

AUD_HP1_JD#

INT_MIC_L_R

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5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of


Petra Uma -1

USB chargerA4


<Core Design>

Title


Date: Sheet of


Petra Uma -1

USB chargerA4


<Core Design>

Title


Date: Sheet of


Petra Uma -1

USB chargerA4


<Core Design>

(Blanking)

WWW.MANUALS.CLAN.SU

Date post:	22-Aug-2020
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