911 Semiconduct 52. Semiconductor Manufacturing Automation Tae-Eog Lee We review automation requirements and tech- nologies for semiconductor manufacturing. We first discuss equipment integration architectures and control to meet automation requirements for modern fabs. We explain tool architectures and operational issues for modern integrated tools such as cluster tools, which combine several pro- cessing modules with wafer-handling robots. We then review recent progress in tool science for scheduling and control of integrated tools and discuss control software architecture, design, and development for integrated tools. Next, we discuss requirements and technologies in fab integration architectures and operation such as modern fab architectures and automated material-handling systems, communication architecture and net- working, fab control application integration, and fab control and management. 52.1 Historical Background ........................... 911 52.2 Semiconductor Manufacturing Systems and Automation Requirements .............. 912 52.2.1 Wafer Fabrication and Assembly Processes .............. 912 52.2.2 Automation Requirements for Modern Fabs ......................... 913 52.3 Equipment Integration Architecture and Control .......................................... 914 52.3.1 Tool Architectures and Operational Requirements .... 914 52.3.2 Tool Science: Scheduling and Control ............... 915 52.3.3 Control Software Architecture, Design, and Development ........... 919 52.4 Fab Integration Architectures and Operation ...................................... 921 52.4.1 Fab Architecture and Automated Material-Handling Systems ......... 921 52.4.2 Communication Architecture and Networking ......................... 922 52.4.3 Fab Control Application Integration ................................ 922 52.4.4 Fab Control and Management ....................... 924 52.4.5 Other Fab Automation Technologies ............................. 924 52.5 Conclusion ........................................... 925 References .................................................. 925 52.1 Historical Background The world semiconductor market has been growing fast and amounted to US$ 270 billion in 2007. The semiconductor manufacturing industry has kept mak- ing innovations in circuit design and manufacturing technology. Some key innovations include circuit width reductions from 1.0 μm in 1985 to 60 nm in 2005, 40 nm in 2007, and even down to 14nm by 2020, and wafer size increase from 200 mm to 300 mm wafers, and even to 450 mm or larger in the near future. Some fabs are producing 1 Gb random-access memory (RAM) by us- ing 50 nm technology, which reduces the cost by about 50% compared with 60 nm technology. Such technol- ogy innovations have led to higher circuit density, increased circuit speed, and remarkable price reduction, which also have created new demand and expanded the market. In 2007, 35 new wafer fabs began to ramp up world monthly fab capacity by two million 200 mm wafers, Part F 52
We review automation requirements and tech-nologies for semiconductor manufacturing. Wefirst discuss equipment integration architecturesand control to meet automation requirements formodern fabs. We explain tool architectures andoperational issues for modern integrated toolssuch as cluster tools, which combine several pro-cessing modules with wafer-handling robots. Wethen review recent progress in tool science forscheduling and control of integrated tools anddiscuss control software architecture, design, anddevelopment for integrated tools. Next, we discussrequirements and technologies in fab integrationarchitectures and operation such as modern fabarchitectures and automated material-handlingsystems, communication architecture and net-working, fab control application integration, andfab control and management.
The world semiconductor market has been growingfast and amounted to US$ 270 billion in 2007. Thesemiconductor manufacturing industry has kept mak-ing innovations in circuit design and manufacturingtechnology. Some key innovations include circuit widthreductions from 1.0 μm in 1985 to 60 nm in 2005, 40 nmin 2007, and even down to 14 nm by 2020, and wafersize increase from 200 mm to 300 mm wafers, and evento 450 mm or larger in the near future. Some fabs are
producing 1 Gb random-access memory (RAM) by us-ing 50 nm technology, which reduces the cost by about50% compared with 60 nm technology. Such technol-ogy innovations have led to higher circuit density,increased circuit speed, and remarkable price reduction,which also have created new demand and expanded themarket.
In 2007, 35 new wafer fabs began to ramp up worldmonthly fab capacity by two million 200 mm wafers,
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912 Part F Industrial Automation
that is, a 17% increase. A modern fab constructioncosts about US$ 2 billion. On the other hand, the semi-conductor manufacturing industry has suffered strongcompetition due to excessive capacity. Therefore, theindustry has tried to reduce costs, improve quality, andshorten the manufacturing cycle time. Automation hasbeen the key for such manufacturing improvement andbusiness success. Consequently, there have been manyaggressive technology innovations and standardizationsfor fab automation. We therefore need to review those
efforts, the state of art, and the future challenges for fabautomation.
In this chapter, we briefly introduce semiconductormanufacturing systems and automation requirements,architecture and control for processing equipment andmaterial-handling systems, communication architectureand networking, and software architecture for processcontrol, equipment control, and fab-wide control. Weexplain academic research works as well as industrialtechnologies and practices.
The semiconductor manufacturing process consists ofwafer fabrication and assembly. In the wafer fabrica-tion process, multiple circuit layers (up to 30 or more)are laid out on a wafer surface through the repetitionof identical sequences of process steps. Most fabrica-tion process steps are chemical processes that oxidizea wafer surface, coat photosensitive chemicals onto thesurface, expose it to a circuit image from a light source,develop and etch the circuit pattern, deposit other chem-icals onto it, diffuse and implant additional chemicalson the etched pattern, and so on. Once a circuit layeris formed, the wafer reenters the fabrication line toform the next circuit layer. The total number of processsteps may amount to 480 or more. A wafer has severalhundreds of formed circuit devices. For strict qualitycontrol, the formed circuits are measured by metrol-ogy equipment frequently after some key process steps.Based on the metrology results, some devices in a wafermay be repaired, reworked or scrapped. Wafter yieldmay be rather low, especially during the ramp-up stagefor the initial 3–6 months. Wafers are transported andloaded into processing tools using a carrier called a cas-sette or pod that loads 25 wafers. A typical fab produces40 000 wafers each month. The fabrication cycle time isseveral weeks or even a few months, depending on thefab management performance. About 20 000–100 000wafers may be in progress at any given time.
Once a wafer completes the fabrication processes,devices on a wafer undergo intensive circuit tests calledelectronic die sorting (EDS). Depending on the testresults, the devices are classified into different finalproducts with specifications on clock speed, number of
effective transistors, and so on. A device that fails tosatisfy the specification of a high-grade product is clas-sified into a lower-grade product. Such a sorting processis also called binning. Some devices may be defective.Due to the yield problem and binning, it is difficult topredict the number of final products of each grade ortype.
Wafers that complete EDS are sent to an assemblyor packaging plant. The fabrication processes leadingto EDS and the assembly processes after EDS arecalled front-end and back-end processes, respectively.In the back-end processes, a wafer is sliced into indi-vidual devices. The sliced devices undergo packagingprocesses that include tape mounting, wire bonding,molding, and laser marking. The packaged devices takefinal tests, where additional binning is carried out. Theback-end processes have been regarded as relatively lowtechnology with low value added and tend to be sub-contracted. However, multichip packages (MCP) thatcombine several chips together into a single packageare becoming increasingly popular due to growing de-mand from the mobile-device industry. MCP or otheradvanced packaging technologies such as wafer-scalepackaging and flip chips increase the value and impor-tance of the back-end processes. Hence, a number ofback-end processes still involve manual material han-dling while the front-end processes have become highlyautomated. Figure 52.1 summarizes the overall semi-conductor manufacturing processes.
A process step is performed by a number of similaror identical wafer processing tools. Due to strict qualityrequirements, some wafer lots should be processed onlywith a restricted set of tools. Different types of waferlots flow concurrently through the fab. Therefore, thefab can be viewed as a hybrid flow shop. Reentrant job
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Semiconductor Manufacturing Automation 52.2 Semiconductor Manufacturing Systems and Automation Requirements 913
Dieattach
Wirebonding
Oxidation
Wafer
Deposition
Developing
Lithography
Coating
Etch
Backlap
Saw Cure Mold
256mb mobile Dram
1Gb N and flsh
256mb mobile Dram
1Gb N and flsh
PlasmaTape
mount
Final test
Assembly
EDS(Electronic die sorting)
Fabrication
Assembly
MCP
Back-end
Front-end
Diffusion/implant
Fig. 52.1 Overall manufacturing processes
flows for processing multiple circuit layers and randomyield make planning and scheduling complicated. A fabconsists of several hundreds of processing and inspec-tion tools. The tools are grouped into bays, where eachbay consists of 10–20 processing tools. Each bay hasa stocker, where wafer cassettes are waiting for process-ing or moving to the next bay.
52.2.2 Automation Requirementsfor Modern Fabs
There are several drivers for fab automation. Thematerial-handling tasks in a fab are very large; for in-stance, a fab that processes 40 000 wafers a monthrequires 200 operators per shift just for movingwafer cassettes [52.1]. Therefore, automated material-handling systems (AMHSs) are used to reduce suchhigh human operator requirements. Other drivers formaterial-handling automation include prevention of hu-man’s handling errors such as wafer dropping, andbetter tool utilization and reduced manufacturing cycletime by fast and reliable material transfer [52.1]. Thekey technological innovations in the front-end processesduring the past decades are the continuing reduction ofcircuit features for higher density and functionality, andwafer size increase to 300 mm for higher throughput.These have led to significant fab automation. Extremecircuit shrinkage requires strict quality control andhigher-class clean rooms to reduce increased risk of
particle contamination. As human operators are a sig-nificant source of particle generation, the number ofoperators needs to be reduced. Wafer size increase leadsto significantly heavier weight of a wafer cassette be-yond human operator’s adequate workload. Therefore,in recent 300 mm fabs, wafer-handling operations havebeen mostly automated. Control applications for equip-ment and AMHSs from many different vendors shouldbe easily integrated. Design, scheduling, and control offully automated fabs are highly complicated and requirenew concepts and ideas (Fig. 52.2).
Traditionally, wafers in a cassette have been pro-cessed in batch mode for most chemical processes suchas etching, deposition, etc. However, as the wafer sizeincreases and quality requirements become stricter dueto circuit shrinkage, it becomes difficult to control gas orchemical diffusion on all wafer surfaces within a largeprocessing chamber to be uniform enough for strictquality requirements. Therefore, single-wafer process-ing (SWP) technology that processes wafers one by onehas been extensively introduced for most processes. Inorder to reduce excessive moving tasks between SWPchambers, several SWP chambers are integrated withina closed environment together with a wafer-handlingrobot. Such a system is called cluster tools. An inte-grated system of SWP chambers with multiple handlingrobots is often called a track equipment or track sys-tem. It can be considered as a combination of multiplecluster tools. Cluster tools or track equipment have been
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Manufacturing executionsystems
Traditional clean room Minienvironment clean room
FMCS and HVAC Life safety
Air Handling
CVD/PVD
Etch
Dice
Engineeringsystems
Chemical distribution system
Package
ChaseWarehouse and
material handlingsystems
Shipping
• Printed circuit boards
Electronic assembly
Final testDevice attach/bond
Test Wafer probe
Oxidation
Class 100 area
Stocker
The open controllerand PLC and SLCcontrollers
Operator interface
Industrial control (Push buttons, pilot lights, terminal blocks, relays, contactors, switches)
Networks (Ethernet, DeviceNet, Remote I/O, Data Highway Plus, ControlNet)
Reliance electric & Allen Bradley drives and motors and Rockwell Automation drive systems
Power monitoring software, RSView32; Programming Packages (RSQuality, RSTrend, RSRecipe)
increasingly used for most processes. Due to the internalcomplexity and restrictions, they pose scheduling andcontrol challenges. First, their operations should be op-timized to maximize throughput. Second, wafer delayswithin a processing chamber after processing should becontrolled because residual gases and heat affect waferquality significantly. Third, the tool controller should bereliable and easily adaptable for different tool config-urations and changing wafer flow patterns or recipes.Scheduling and control, and tool application integrationare not trivial.
Another important issue for fab automation isstandardization for reducing integration effort and per-formance risk. Semiconductor Equipment and MaterialInternational (SEMI), an international organization, hasdeveloped extensive standards on architectural and in-terface standards of material-handling hardware, com-munication, and control software for fab automation.The standards themselves are based on state-of-the-artautomation technologies; however, they should be con-tinuously improved for higher operational goals andchanging automation requirements.
52.3 Equipment Integration Architecture and Control
In a cluster tool, there is no intermediate buffer betweenthe process modules (PMs). A wafer, once unloadedfrom a loadlock, can return to the loadlock only af-ter it completes all required process steps and is oftencooled down at a cooler module, if any. This is becausea hot wafer returned to the wafer cassette at the load-lock may damage other wafers there and a hot wafer inprogress should not be excessively cooled down beforeprocessing at the next PM. A wafer loaded into a PMimmediately starts processing since the PM’s chamberalready has gases and heat. There are different clustertool architectures, as illustrated in Fig. 52.3. Most toolshave radial configurations of chambers, where robotmove times between chambers are minimized. Linear
configurations are also considered to add or removechambers flexibly. The robot has a single arm or dualarms. The dual arms keep opposite positions. Dual-armed tools are known to have higher throughput thansingle-armed tools [52.2]. There are also tools with in-termediate vacuuming buffers between chambers andloadlocks [52.3] in order to save vacuuming and vent-ing times at the chambers. Some new cluster tools usemultiple wafer slots in a chamber in order to improvethroughput above that of SWP tools by processing sev-eral wafers together [52.4]. However, those new toolarchitectures tend to increase scheduling complexitysignificantly.
Track equipment or systems are also widely usedfor integrating several process steps. Photolithographyprocesses use track systems that supply steppers withwafers coated with photosensitive chemicals and de-
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Semiconductor Manufacturing Automation 52.3 Equipment Integration Architecture and Control 915
velop the circuit patterns on the wafers that are formedby exposures to circuit pattern picture images at thesteppers. Process modules for coating and develop-ing, and accompanying baking and cooling modulesare combined into a track tool with several robots, asillustrated in Fig. 52.4. Each process step has five toten parallel modules [52.5, 6]. An automated wet sta-tion also has a series of chemical and rinsing baths forcleaning wafer surfaces, which are combined by severalrobots moving on a rail [52.7]. Recently, EDS processesfor testing devices on wafers are automated to forma kind of track system. A number of testing tools forwafer burn-in (WBI) test, hot pretest, cold pretest, laserrepair, and posttest are configured in series–parallel byseveral robots moving on a rail. EDS systems and wetstations can process several different wafers concur-rently while most cluster tools or track tools for coatingand developing repeatedly process identical wafers.
Wafers mostly go through a sequence of processsteps in series. For some processes, wafers visit someprocess steps again; for instance, unlike conventionalchemical vapor deposition, atomic-layer deposition pro-cess controls the deposition thickness by repeatingextremely thin deposition multiple times. Therefore,a wafer reenters the chambers many times. In track sys-tems, wafer reentrance can be achieved, depending onthe chamber configuration and process recipe. In someprocesses, a chamber should be cleaned after a specifiednumber of wafers have been processed or when sensorswithin the chamber detect significant contamination. Ifa wafer remains in a chamber after processing, this canlead to quality problems. This idle time, called waferdelay, must be bounded, reduced or regulated. Processtimes or tasks times are rather constant, but can be sub-ject to random variation, mostly within a few percent.There can be exceptional delay, even if only rare, due to
10 coaters
10 cool plates
Loadlocks 10developers
Interface tosteppers
Robot
Robot
Opticaledge beadremovers
5 bakers
Robot
Robot
5 hot plates5 hot plates
Moduleelectronics
Buffer
5 bakers
Robot
Buffer CPx
Buffer
Moduleelectronics
Fig. 52.4 A track system
abnormal process conditions. A wafer alignment task,which correctly locates a wafer unloaded from a load-lock onto a robot arm by using a laser pointing system,sometimes fails and needs to be retried. Integrated toolsmostly limit intermediate buffers. Therefore, blockingand waiting are common and even deadlocks can occur.Reentrance, wafer delays, cleaning cycles, and uncer-tainty all increase scheduling complexity significantly.Tool productivity by intelligent scheduling and controlis critical for maximizing fab productivity and even af-fects wafer quality significantly.
52.3.2 Tool Science: Scheduling and Control
Scheduling StrategiesThere can be alternative scheduling strategies for clus-ter tools. First, a dispatching rule determines the nextrobot task depending on the tool state. It can be con-sidered dynamic and real time. However, it is hard tooptimize the rule. We are only able to compare per-
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916 Part F Industrial Automation
formances of heuristically designed dispatching rulesby computer simulation. Second, a schedule can bedetermined in advance. This method can optimize per-formance if a proper scheduling model can be defined.When there is a significant change in the tool situ-ation, rescheduling is done. Cyclic scheduling makeseach robot and each processing chamber repeat identi-cal work cycles [52.7, 8]. Once the robot task sequenceis determined, all work cycles are determined. Mostacademic works on cluster tool scheduling considercyclic scheduling. Cyclic scheduling has merits suchas reduced scheduling complexity, predictable behav-ior, improved throughput, steady or periodical timingpatterns, and regulated or bounded task delays orwafer delays and work in progress [52.7–10]. In cyclicscheduling, the timings of tasks can be controlled in realtime while the sequence or work cycle is predetermined.
A cluster tool that repeats identical work cycles canbe formally modeled and analyzed by a timed eventgraph (TEG), a class of Petri nets [52.12]. Transitions,places, arcs, and tokens usually represent activities orevents, conditions or activities, precedence relationsbetween transitions and places, and entities or condi-tions, respectively. They are represented graphically byrectangles, circles, arrows, and dots, respectively. Fig-ure 52.5 is an example of a TEG model for cluster tools.Once a TEG model is made, the tool cycle time, theoptimal robot task sequence, the wafer delays, and theoptimal timing schedules can be systematically identi-
P15
P1 P2 P3
T1 T2
P4
T3
P5
T4
P6
T5
P7
T6
P13P14 P12
T12T13T14
P11
T11
P10
P17
P16 P18
T10
P9 P8
T9 T8
T7
Unloading com
pleterobot m
ove
Unloading
from L
L
Unloading
Loading
Chamber 1 available
Fig. 52.5 A timed event graph model for a dual-armed cluster tool [52.11]
fied [52.7, 9, 10]; for instance, the tool cycle time is themaximum of the circuit ratios in the TEG model, wherethe circuit ratio of a circuit is the ratio of the sum of thetotal times in the circuit to the number of the tokens inthe circuit. For instance, the cycle time of a dual-armedcluster tool can be derived from the ratio as
max
[max
i=1,...,n
pi +2u +2l +3v
mi,
(n +1)(u + l +2v)
],
where pi , mi , u, l, v, and n are the process time of pro-cess step i, the number of parallel chambers for processstep i, the unloading time, the loading time, the movetime between the chambers, and the number of processsteps, respectively [52.13].
Schedule QualityFor a cluster tool with a given cyclic sequence, therecan be different classes of schedules, each of whichcorresponds to a firing schedule of the TEG model.A periodic schedule repeats an identical timing patternfor each d work cycles. When d = 1, the schedule iscalled steady. In a steady schedule, task delays suchas wafer delays are all constant. In a d-periodic sched-ule, the wafer delays have d different values, whilethe average is the same as that of a steady sched-ule. The period d is determined from the TEG model.A schedule that starts each task as soon as the pre-
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Semiconductor Manufacturing Automation 52.3 Equipment Integration Architecture and Control 917
Robot
PM1
PM2
PM3
PM4
PM5
v r
τ1
τ2
τ1
τ1
τ2
u v s v s v r u v
τ1
τ2
s v s v r u v
τ1
τ2
s v s v r u v
τ1
τ1
τ2
τ2
s v s v r u v s
a) Waver delay
Periodicity = 1
r r + 1 r + 2 r + 3
Robot
PM1
PM2
PM3
PM4
PM5
v
τ1
τ2
τ1 τ1
τ1
τ2
s v s v r u v s v s
τ1
τ2
v r u v s v
τ1
τ2
s v r v r
τ1
τ1
τ2 τ2
τ2
s v s v r u v s v s v
b)
Periodicity = 3
r r + 1 r + 2 r + 3
Robot
PM1
PM2
PM3
PM4
PM5
u v
τ1
τ2
τ1
τ1
τ2
s v s v r u v s v
τ1
τ2
s v r u v vs
τ1
τ2
s v r u v
τ1
τ1
τ2
τ2
s v s v ur v s
c)
r r + 1 r + 2 r + 3
Fig. 52.6a–c Examples of schedules. (a) Steady schedule: a SESS, (b) 3-periodic schedule, (c) irregular schedule
ceding ones complete is called earliest. An earliestschedule can be generated by the earliest firing rule ofthe TEG model that fires each transition as soon as itis enabled. In other words, an earliest starting sched-ule need not be generated and stored in advance. TheTEG model with the earliest firing rule can be used asa real-time scheduler or controller for the tool. There-fore, an earliest schedule can be implemented by anevent-based control, which initiates a task when an ap-propriate event, for instance, a task completion, occurs.Therefore, an earliest starting schedule based on suchevent-based control has merits. First, potential logicalerrors due to message sequence changes can be pre-vented. When a tool is controlled by a predeterminedtiming schedule, communication or computing delaysmay cause a change in a message sequence and a criti-cal logical error; for instance, a robot may try to unloada wafer at a chamber before processing at the cham-ber has been completed and hence when the wafer slotis still closed. Second, the earliest schedule minimizesthe average tool cycle time, which is the same as the
maximum circuit ratio of the TEG model. Therefore,the most desirable schedule is a steady and earlieststarting schedule (SESS). For a cluster tool with cyclicoperation, there always exists a SESS. Figure 52.6a isan example of SESS for the TEG model. A SESS canbe computed in advance using the max-plus algebraor a kind of longest-path algorithm [52.9] and imple-mented by an event-based controller based on the TEGmodel [52.10, 13].
Controlling Wafer DelaysWhen a tool has a strict constraint on the maximumwafer delay, as in low-pressure chemical vapor deposi-tion, coating processes or chemical cleaning processes,it is important to know whether there exists a feasi-ble schedule that satisfies the constraint. There havebeen works on the schedulability of a cluster tool,that is, the existence of a feasible SESS [52.11, 14].Lee and Park [52.14] propose a necessary and suffi-cient condition for schedulability, that is, the existenceof a feasible SESS, based on circuits in an extended
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918 Part F Industrial Automation
version of TEG called negative event graph, whichmodels the time-window constraints on wafer delaysby negative places and tokens. In fact, schedulabilitycan also be verified by the existence of a feasible so-lution in an associated linear program. However, thenecessary sufficient condition identifies why the timeconstraints are violated, and often gives a closed-formschedulability condition based on the scheduling pa-rameters such as the process times, the robot task times,and the number of parallel chambers for each processstep.
Most schedulability analyses assume deterministicprocess and task times. When a cluster tool is oper-ated by a SESS, the wafer delays are kept constant.However, in reality, there can be sporadic random dis-ruptions such as wafer alignment failures and retrialsor exceptional process times. In this case, the sched-ule is disturbed to a non-SESS, in which the waferdelays fluctuate and may exceed the specified limits.However, there are regulating methods that quickly re-store a disrupted schedule. Kim and Lee [52.15] proposea schedule stability condition for which a disrupted ear-liest firing schedule of a TEG or a cluster tool convergesto the original SESS regardless of the disruptions, anda simple way of enforcing such stability by adding anappropriate delay to some selected tasks. Therefore, wecan regulate wafer delays to be constant. Such a sta-bility control method has been proven to be effectiveeven when there are persistent time variations of a fewpercent [52.15]. Even when the process times or therobot task times vary significantly, but only if they arewithin a bounded range, schedulability against waferdelay constraints can be verified by an efficient algo-rithm on an associated graph [52.15]. When the initialtimings are not appropriately controlled or a SESS isdisrupted, the earliest schedule converges to a periodicschedule whose period is determined from the TEG.Therefore, the wafer delays can be much larger than theconstant value for a SESS. For a given wafer delay con-straint, even if the schedulability condition is satisfied,that is, a feasible SESS exists, a periodic schedule mayhave wafer delays that exceed the limit. Therefore, weare concerned with whether such a periodic schedulewith fluctuating wafer delays can satisfy the wafer de-lay constraint. Lee et al. [52.10] proposed a systematicmethod for identifying exact values of task delays ofa TEG or wafer delays of a cluster tool for each typeof schedule: steady or periodic, earliest or not. Fromthe method, the schedulability of periodic schedules,which occurs when timings are not well controlled, canbe verified.
Workload Balancing for ToolsIn a traditional flow line or shop, the workload of a pro-cess step is the sum of the process times of all jobsfor the step. The bottleneck is the process step with themaximum workload. Imbalance in the workloads of theprocess steps causes waiting of jobs or work in progressbefore the bottleneck. However, in automated manufac-turing systems such as cluster tools, the workload isnot easy to define because the material-handling systeminterferes with the job processing cycle. To generalizethe workload definition, we can define the generalizedworkload for a resource as the circuit ratio for the cir-cuit in the TEG that corresponds to the work cycle ofthe resource [52.10, 16]; for instance, the workload fora chamber at process step i with mi parallel chambers ina single-armed tool is (pi +2l +2u +3v)/mi , becauseeach work cycle of a chamber requires a wafer process-ing (pi ), two loading tasks (2l), two unloading tasks(2u), and three robot moves (3v). A robot has work-load (n +1)(u + l +2v), the sum of all robot task times.Therefore, the overall tool cycle time is determined bythe bottleneck resource as
max
[max
k=1,2,...,n
pk +2l +2u +3v
mk,
(n +1)(u + l +2v)
].
Imbalance between the workloads or circuit ratioscauses task delays such as wafer delays. In a single-armed tool, the workload imbalance between processstep i’s cycle and the whole tool cycle is
max
[max
k=1,2,...,n
pk +2l +2u +3v
mk,
(n +1)(u + l +2v)
]− (pi +2l +2u +3v)
mi.
Notice that each chamber at process step i has cycletime (pi +2l +2u +3v), while the overall cycle timeat the process step is (pi +2l +2u +3v)/mi . Therefore,the delay in each cycle of a chamber at process step iis mi times as long as the workload imbalance at theprocess step. Consequently, the average wafer delay ata chamber at process step i is [52.10]
mi max
[max
k=1,2,...,n
pk +2l +2u +3v
mk,
(n +1)(u + l +2v)
]−(pi +2l +2u +3v) .
We note from the well-known queueing formula, Lit-tle’s law, that the average delay is proportional to the
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Semiconductor Manufacturing Automation 52.3 Equipment Integration Architecture and Control 919
average work in progress. In a cluster tool, wafer de-lays are more important than the number of waitingwafers because of extreme limitation on the wafer wait-ing space. Wafer delays can be reduced or eliminatedby balancing the circuit ratios. Such generalized work-load balancing can be done by adding parallel chambersto a bottleneck process step, accommodating the pro-cess times within technologically feasible ranges orintentionally delaying some robot tasks [52.10,16]. Leeet al. [52.10, 16] proposed a linear programming modelthat optimizes such workload balancing decisions un-der given restrictions. Workload balancing is essentialfor cluster tool engineering.
Additional WorksCluster tools with cleaning cycles, multi-slots, and reen-trance present more challenging scheduling problems.There are some works on using cyclic scheduling forthese problems [52.4, 17, 18]. For a tool controlled bya dispatching rule, we cannot optimize the rule andidentify or control wafer delays. Wafer delays are un-expected and can be excessively long. Nonetheless,dispatching rules are inevitable when the schedulingproblem is too complex or involves uncontrollable sig-nificant uncertainty. Reentrance, cleaning cycles, andmulti-slots contribute significantly to scheduling com-plexity. In general, process times and robot task timesin cluster tools and track equipment are relativelywell regulated and have variations within a few per-cent, because most processes are designed to terminatewithin a specified time. However, modern adaptiveprocess control that adapts process control parame-ters based on real-time sensor information may causesignificant time variation. Cleaning based on cham-ber conditions may occur randomly and hence increaseuncertainty significantly. There are some works ondispatching rules for cluster tools with cleaning andmulti-slots [52.19].
52.3.3 Control Software Architecture,Design, and Development
In a cluster tool, each processing module or chamberis controlled by a process module controller (PMC).The robot, loadlocks, and slot valves at the chamberare controlled by a transport module controller (TMC).A module controller receives data from the sensors ina chamber, and issues control commands to the ac-tuators such as gas valves, pumps, and heaters. Themodule controllers use bus-type control networks calledfieldbuses such as process field bus–decentralized pe-
ripherals (PROFIBUS-DP) and control area networks(CANs) for communication and control with sensorsand actuators. The module controllers are also coor-dinated by a system controller, called the cluster toolcontroller (CTC). A CTC has a module manager anda real-time scheduler. A module manager receives es-sential event messages from the PMCs, manages thestates of the process modules, and sends the PMCsdetailed control commands to perform a schedulingcommand from the scheduler. Communication betweenthe PMCs, TMC, and the CTC usually uses transmis-sion control protocol/Internet protocol (TCP/IP) basedon Ethernet because they are well-known and accepteduniversal standards.
A real-time scheduler monitors the key events fromeach PMC and the TMC through the module man-ager. The events include starts and completions ofwafer processing or robot tasks, which are essential forscheduling. Then, the scheduler determines the states ofthe modules and scheduling decisions as specified bythe scheduling logic or rules, and issues the schedul-ing commands to the module manager. Since the waferflow pattern can change, the scheduling logic should beeasily changed without much programming work. Themodules are often configured by a tool vendor to fulfilla specific cluster tool order. For large liquid-crystal dis-play (LCD) fabrication, the modules are often integratedat a fab to assemble a large-scale cluster tool. Therefore,the scheduler should implement the scheduling logicin a modular way for flexibility when changing logic.To do this, the scheduling logic can be implementedby an extended finite state machine (EFSM) [52.13].An EFSM models state change of each module andembeds a short programming code for the schedulinglogic or procedure. The scheduling logic also includesprocedures for handling exceptions such as wafer align-ment failures, processing chamber failures, robot armfailures, etc. Figure 52.7 illustrates a typical architec-ture for communication and control in a cluster tool.A track system has a similar communication and controlarchitecture.
A SEMI standard, cluster tool module commu-nication (CTMC), specifies a model of distributedapplication objects for module controllers and a CTC,and a messaging standard between the objects [52.20].Lee et al. [52.21] also propose an object-oriented ap-plication integration framework based on a high-levelfieldbus communication protocol and service standard,PROFIBUS-field message specification (FMS), whichdefines a messaging standard between manufacturingequipment based on their object models. They sug-
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Job editReceipe editAlarm manipulationIO value setting
MC level task decompositionMC coordinationModule manager
CTC
Unload
Ready
Prepare
Ready PlacePick
Load ClosedOpen
Ready
Disabled
Pump-up
Pump-down
Ready
Disabled
Loadlock
Robot arm
Slot valve
Chuck
Fig. 52.7 A cluster tool controller architecture [52.22]
gest that some object models in CTMC, which weredefined based on a traditional object model for material-handling systems, need to be modified to handle therobot tasks in a cluster tool.
Each time a new cluster tool is developed, thescheduling logic and a CTC application should be in-tegrated and extensively tested. However, tool testingand verification involve difficulties. First, a real tool isexpensive and hence cannot be tied up for extensive test-ing. Second, testing with a real tool can be hazardousdue to mechanical or space restrictions. Third, since thedynamics of a real cluster tool is slow, it takes signifi-cant time to test the system. Finally, it is often difficultto recognize subtle logical errors by observing opera-tional behavior of a real tool. Therefore, the CTC andscheduler need to be tested in a virtual environmentsuch as a virtual cluster tool (VCT), in which the pro-cess modules and the transport modules are replaced bytheir emulators [52.22]. The emulators receive controlcommands from the scheduler through the module man-
ager and/or the module controllers, and create messagesfor events such as process completions or robot taskcompletions at appropriate times. The process times canbe accelerated for initial rough-cut testing. Tool engi-neers examine the sequence of the events generated atthe CTC or module controllers, and detect an anomaly.Such verification takes several days or weeks and is te-dious. Some errors are hard to recognize and are oftenmissed. Joo and Lee [52.22] propose the use of eventsequence finite state machines for automatic error detec-tion, which is basically identical to a finite state machineexcept that, when an event other than allowed ones ata state occurs, an error is assumed. They detected sev-eral unexpected logical errors, including logical errorscaused by message sequence changes due to communi-cation delay. Most tool simulators, such as ToolSim byBrooks Automation, focus on performance evaluationof a configured tool rather than high-fidelity model-ing and verification of tool operation and messagingbetween a CTC and module controllers.
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Semiconductor Manufacturing Automation 52.4 Fab Integration Architectures and Operation 921
52.4 Fab Integration Architectures and Operation
52.4.1 Fab Architecture and AutomatedMaterial-Handling Systems
In modern 300 mm fabs, wafer cassette-handling tasksfor interbay moves as well as intrabay ones are au-tomated. In order to save the footprint and securehuman operator access for equipment maintenance orexception handling, overhead transport (OHT) systemsare mostly used. Traditional automated guided vehicle(AGV) or rail-guided vehicle (RGV) systems have beenreplaced by OHTs. In order to reduce particle contam-ination risk, tasks of loading and unloading wafer attools are automated by using a new wafer carrier, thefront open unified pod (FOUP), and a standard me-chanical interface (SMIF). Processing tools are oftenenclosed in a minienvironment with extreme cleanness.Design and operation of the architecture and AMHSsof such fully automated fabs should be optimized tomaximize throughput and reduce the cycle time whileminimizing capital investment. An AMHS itself canbe a bottleneck due to a limited number of vehiclesand congestion on transport rails. Transport routes arenot so flexible and should be considered as a limitedresource. Therefore, in some 300 mm fabs, even crit-ical metrology steps are skipped in order to reduceexcessive vehicle traffic and the cycle time. Schedul-ing and dispatching systems are not yet well designedto handle such fully automated fabs. Control softwaresuch as manufacturing execution systems (MESs), ma-terial control systems (MCSs), equipment controllers,and schedulers as well as the AMHS architecture are
Stocker
EmptyOHT
LoadedOHT
Equipment
Interbayloop
Intrabayloop
Fig. 52.8 An overhead transport system
not yet as intelligent and flexible as human operators,who make adaptive and intelligent decisions dependingon the situation. There still remain many challenges tosmart and efficient fully automated fabs. Figure 52.8 il-lustrates a typical OHT system layout, which consistsof intrabay and interbay loops. There are works on opti-mal design of OHT networks, optimal number of OHTs,and performance analysis [52.23, 24].
Automated material-handling systems mostly havelimited handling capacity and flexibility due to re-stricted paths and limited number of vehicles. There-fore, stockers or waiting places have been mandatorysolutions for such problems. Stocking wafer cassettesat a bay involves significant delay due to prior wait-ing cassettes and handling operations. Therefore, insome 300 mm fabs, a desire to minimize the deliv-ery cycle time led to attempts to combine several baysinto a larger cell by eliminating bay-stockers in or-der to enforce direct delivery. However, this may causesignificant OHT congestion and blocking, and hencethroughput degradation. Nonetheless, direct deliveryis one of the key technological challenges for next-generation 450 mm fabs [52.25]. To achieve the goal ofdirect delivery, we need quite different architectures offabs and material-transfer systems. A solution might beto mimic a transfer line or a conveyor system, wherewafer cassettes go through a significant number of pro-cess tools without intermediate stocking. Such a systemis called an inline system. One of the most serious disad-vantages of inline systems is lack of flexibility. In futurefabs, lot sizes will continue to shrink. Therefore, con-
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flicting goals of flexibility and direct delivery shouldbe resolved. LCD fabs, for which material transfer hasbeen fully automated from the early stage due to manualhandling difficulties, tend to introduce inline systemsfor more process steps as the panel size increases con-tinually. A future 450 mm fab may also resemble anLCD line [52.25]. Stocker racks may be extensively lo-cated in parallel to the inline system [52.25]. Severalalternatives for future fab and material-handling systemarchitectures are now being discussed [52.26].
Traditionally, AMHSs have been scheduled andcontrolled separately from job scheduling. That is,wafer processing jobs are scheduled disregarding thelimited capacity of the AMHS, and then material-transfer tasks, which are requested from the jobschedule executor such as a real-time dispatcher, areseparately planned and controlled by a material controlsystem (MCS), that is, the AMHS controller. However,such decoupling is not so effective for modern inte-grated systems where job scheduling is significantlyrestricted by the AMHS, and vice versa. Interaction be-tween job schedules and material transfer control shouldbe considered, or they should be simultaneously sched-uled as in cluster tools. MCSs have been engineeredby AMHS vendors and are managed by automationengineers in fabs. However, job scheduling has beendone by production management or control staffs. Inthe future, the two staff groups should better collabo-rate to tightly couple job scheduling and AMHS control.As fab technologies evolve, material-handling require-ments become more challenging. SEMI has updateda roadmap for AMHSs for future fabs [52.27].
Open object interface framework(CORBA/DCOM/OPC-based application object interface)
Fig. 52.9 Communication architecture for fab automation
52.4.2 Communication Architectureand Networking
SEMI communication standards have been widely usedin fabs to reduce system integration efforts [52.28].While old tools are connected only by RS-232 ports,modern tools have Ethernet connections. The semicon-ductor equipment communication standard I (SECS-I)and high-speed message standard (HSMS) define datastandards on RS-232-based serial communication andTCP/IP communication over Ethernet connection, re-spectively. SECS-II defines messaging standards. Thegeneric equipment model (GEM) and virtual factoryequipment interfaces (VFEI) are object-based appli-cation interface standards for equipments and factorycontrol applications, respectively. The overall com-munication architecture is summarized in Fig. 52.9.AMHSs use fieldbus or control networks, either openor proprietary.
As advanced process control (APC) technology forreal-time process sensing and real-time adaptive con-trol becomes widespread, there is increasing demandon high-speed real-time communication technology, be-yond the current communication architecture, in orderto process massive process sensing data in real time.
52.4.3 Fab Control Application Integration
The most critical application for factory integrationis a manufacturing execution system (MES). Its ba-sic functions are to monitor equipment, send recipes,and keep track of wafers or other auxiliary materialssuch as photomasks. Quality monitoring and schedulingfunctions tend to be performed by separate appli-cations from specialized vendors. MES applicationsshould be easily and reliably integrated with equip-ment control applications. Traditionally, MESs usedmiddleware based on message queueing to reliablyprocess massive event messages from many equip-ments. No messages should be lost and the responsetime should be controlled. Therefore, such messagesfrom many different tools are queued and the mes-sage queues are served by reasonable queueing orservice policies for load balancing and response timecontrol. Such message-based communication and inte-gration require significant application work to integrateMES applications with equipment control applica-tions. An application designer should understand alllow-level messages and their required sequence forlogical interaction between the MES and equipmentcontrollers. Debugging, verification, and modification
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Semiconductor Manufacturing Automation 52.4 Fab Integration Architectures and Operation 923
are not easy. An alternative approach is object-based application integration. Each equipment and anMES application have a model of constituent ob-jects, which specify the functions and informationalstates. Then, interactions between an MES and equip-ment are implemented by method calls or servicerequests between their corresponding objects. The com-mon object request broker architecture (CORBA) isa middleware solution for facilitating application inte-gration and interaction between such distributed objectsand managing objects and services. MES applicationdesigners can conveniently make use of the high-level services of the objects in equipment controlapplications as well as common MES application ob-jects. Detailed messaging sequences are handled bythe methods of the objects that provide the relevantservices. SEMI proposed an object-based MES appli-cation design standard, called the computer-integratedmanufacturing (CIM) framework. SEMI also devel-oped a standard object model for control applicationsof process equipment, called the object-based equip-ment model (OBEM). There have been concerns aboutwhether CORBA can work reliably and fast enoughfor modern fab environments that generate massiveamounts of real-time data. However, MES vendorshave successfully implemented CORBA-based MESsolutions, for example, IBM’s SiView and AIM Sys-
Application components/objects
CORBA
OBEMOBEM
MES
Basic components/objects. . .
OBEM(Objectbasedequipmentmodel)
Machinemodule
MachineportMachine
Equipmentcontrol
applications
Equipmentresource
Equipmentresource
Partlocation
Materiallocation
Processcapability
OBEM/CORBA
Intermediatecomponents
Physical equipmentUse
r in
terf
ace
EquipmentresourceClock Carrier part
Fig. 52.10 Object-based interaction for MES and equipment control applications
Recently, the service-oriented architecture (SOA)has been increasingly popular for business and enter-prise applications [52.29]. Business processes tend tochange frequently to cope with business requirementchanges, and to be distributed over the Internet. There-fore, more flexibly composable services are defined andcalled as needed to form a new business process. Ob-jects are considered to have too small granularity tobe used for business processes [52.29]. Further, dis-tributed objects technology such as CORBA and thedistributed component object model (DCOM) are noteasy standards to work with, because it is difficult tointegrate object applications that were developed bydifferent people at different places on different plat-forms at different times. Furthermore, CORBA andDCOM are not widely understood by software en-gineers and control and automation engineers. Webservices have been open standards for easily integratingapplications distributed on the Internet by using extensi-ble markup language (XML)-based open standards suchas simple object access protocol (SOAP), web servicesdescription languages (WSDLs), and universal descrip-tion, discovery, and integration (UDDI), and standardweb protocols such as XML, hypertext transfer proto-col (HTTP), and transmission control protocol/Internet
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protocol (TCP/IP). Therefore, SOA based on web ser-vices can provide open standards for easily integratingdistributed factory applications with proper granular-ity. Therefore, some fabs or vendors for MESs orfab management applications are also now consideringSOA-based design. However, it should be studied morewhether SOA really makes sense for factory applica-tions in terms of reliability and real-time performance.
52.4.4 Fab Control and Management
Fab operation is highly complicated due to the com-plex process steps and the massive number of lots inprogress. One of the most crucial fab control applica-tions is a real-time dispatcher that keeps track of thelots and equipment states, and determines which lotswill be processed at which tools. It uses dispatchingor scheduling rules that are proven to be effective forfab operation. The rules may be developed and testedfor each fab through extensive simulation in advance.The essential function of a dispatcher is to process mas-sive amounts of job and equipment data reliably andquickly, and compute a dispatch list quickly. A dis-patcher sends a scheduling command to the MCS andthe process equipment directly in an automated fab,whereas in a manual fab human operators perform thejob of loading tasks as specified in the dispatch list.
Fig. 52.11 A fab control system architecture (EEES – engineeringequity extension service, SPC – statistical process control)
An alternative scheduling approach to the dispatch-ing rules is to have a separate scheduler that determinesan appropriate work-in-progress level for each processstep by using a dynamic lot flow model and then de-termines an optimal schedule for each process stepseparately under the restriction of the ready times andthe due dates that are imposed by the schedule of otherprocess steps. Frequent rescheduling is needed to copewith changes in fabs. Even in this case, the dispatcherretains the basic functions except for the schedulingfunction, and may change the schedule from the sched-uler by local rules depending on the fab state. Thisapproach has potential for further improving fab per-formance. However, there should be more experimentalstudies on which approach is more effective for differentfab management environments.
A production planning system or supply-chain plan-ning system determines daily production requirementsfor key process stages to meet order due dates or de-mand forecasts while minimizing inventory level. Thesystem also considers binning due to random yieldsand capacity constraints. Other important fab controlapplications include yield management systems and ad-vanced planning and scheduling (APS) systems. Anoverall fab control application architecture is summa-rized in Fig. 52.11.
In spite of extensive literature on fab scheduling,control, and management, there still remain many is-sues, including how the dispatching and schedulingsystems, and scheduling rules should be developedto fulfill complex scheduling requirements for fullyautomated 300 mm fabs or future 450 mm fabs, inwhich AMHSs will be more strongly coupled with jobscheduling for direct delivery, and lot definition and jobflows will change significantly.
52.4.5 Other Fab Automation Technologies
Fab automation aims at an autonomous factory that re-liably and intelligently produces high-quality wafers.As quality requirements have become stricter andthe cost of attaining this quality has increased, fabshave developed quality-sensitive automation technolo-gies. Advanced process control (APC) technologyincludes fault detection and classification (FDC) andrun-to-run (R2R) control [52.30]. FDC makes useof statistical methods such as multivariate analysis,or intelligent computing or data-mining technologiessuch as neural networks or rules, in order to de-tect early any anomaly in process control that willcause significant quality problems, classify the prob-
lems, and report them to the quality engineers. R2Rcontrol intelligently adapts process control parametersbased on in situ measurements from process sensors.The response models between the measurement andcontrol parameters are dynamic, nonlinear, multiple-input multiple-output (MIMO), and uncertain [52.30].Therefore, advanced stochastic or statistical functionalmodels and algorithms, or neural networks are used.An equipment engineering system (EES) is for toolvendors to remotely monitor process control of toolsat fabs and tune process parameters. It is intendedto reduce the initial ramp-up period and cost. Tool
vendors cannot keep high-class engineers at customersites for long periods, for instance, even more than6 months. Another automation technology for qual-ity is e-Diagnostics, which enables tool vendors inremote locations to detect an anomaly in tools inproduction at fabs quickly. It can prevent or reduceproduction of defective wafers and reduce the leadtime to dispatch tool engineers to customer sites.Tool vendors and SEMI have developed EES and e-Diagnostics technologies and standards, including datastandards, security control, remote control or manipula-tion, etc. [52.31].
52.5 Conclusion
Semiconductor manufacturing fabs have extensivelydeveloped and implemented state-of-the-art industrialautomation technologies. We have briefly reviewedthem in this Chapter. There remain many challengesfor the future, such as for 450 mm fabs. Futurefabs for manufacturing nanodevices may require quite
new concepts of equipment and material handling,and hence new automation technologies. Concepts,technologies, and practices of semiconductor manufac-turing automation can give insights into automationof other manufacturing industries or service sys-tems.
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