5542g_129716449-Aspire-5542-5542G-schematic

7/22/2019 5542g_129716449-Aspire-5542-5542G-schematic

http://slidepdf.com/reader/full/5542g129716449-aspire-5542-5542g-schematic 1/61

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title

Size Document Number Rev

Date: Sheet

of

Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, Taiwan, R.O.C.

JV50-TR SB

BLOCK DIAGRAM

A3

1 61Tuesday, June 16, 2009

<Core Design>

Title


Date: Sheet

of


JV50-TR SB

BLOCK DIAGRAM

A3


<Core Design>

Title


Date: Sheet

of


JV50-TR SB

BLOCK DIAGRAM

A3


<Core Design>

0~1.55V 18A

VCC_CORE_S0_1

VDDNB

0~1.55V 18A

DDR2667/800 MHz

DDR2 667/800MHz

667/800MHz

ODD SATA

HDD SATA

SATA

Mini USB

Blue Tooth

Camera

USB

4 Port

USB

KBC WPC773 Winbond

INT.KB

TouchPad

MXICMX25L1605

BIOS

DEBUGCONN.

LPC

LPC BUS

Mini CardPCIex1

WLAN

BCM5784LAN Giga LAN TXFM RJ45

New card PWR SW W83L351YG

CRT

LCD

CLK GEN.ICS9LPRS480BKLFT 71.09480.A03RTM880N-796-VB-GRT 71.00880.A03

G792

Codec

ALC888S

INT MIC

MIC In

MDC Card

AZALIA

MODEM

Line Out(SPDIF)

RJ11

667/800 MHz

3

16,17

16,17 19

20

35

23

22

24

31

25

26 27 27

34 28

33

28

30

30

30

36

38 36

37 37

MAX9789OP AMP

INT.SPKR

29

30

Project code: 91.4FN01.001PCB P/N : 48.4FN01.001REVISION : 09230- -1

TOP

VCC

S

S

GND

BOTTOM

PCB STACKUP

DCBATOUT

SYSTEM DC/DC

5V_S5

INPUTS

SYSTEM DC/DCRT8205A

5V_S5(6A)

46

OUTPUTS

RT9025

1D1V_M92

49

3D3V_S5(6A)

1D2V_S0(4A)

47

DCBATOUT1D1V_S0(7.5A)

INPUTS OUTPUTSTPS51124

RT9161

3D3V_S0 2D5V_S0(200mA)

50

45

VCC_CORE_S0_0

0~1.55V 18A

OUTPUTS

CPU DC/DCINPUTS

DCBATOUT

CHARGER

OUTPUTSINPUTS

CHG_PWR

DCBATOUTUP+5V5V 100mA

18V 6.0A

MAX8731

ISL6265AHR

MS/MS Pro/xD/MMC/SD

5 in 1

CardReaderRealtekRTS5159 32 32

A-Link

AMD Caspian CPU

S1G3 (35W)

638-Pin uFCPGA638

AMD RS880M

CPU I/F

INTEGRATED GRAHPICS

LVDS, CRT I/F

AMD SB710

USB 2.0/1.1 ports

(10/100/1000Mb) ETHERNET

ATA 66/100

High Definition Audio

ACPI 1.1

LPC I/F

South Bridge

PCI/PCI BRIDGE

O U T

I N

16X16

North Bridge

4X4

11,12,13,14,15

8,9,10

4,5,6,7

SYSTEM DC/DCTPS51125

DCBATOUT 1D8V_S3(11A)

INPUTS OUTPUTS 48

49

G957 49

49G9161

3D3V_S0

3D3V_S5

1D5V_S0(1A)

1D2V_S5(400mA)

Daughter BoardLED Board

Daughter BoardUSB Board

M92XT

HDMI 21

Mini Card

Finger

Printer 31

Line In

30

53,54,55,56,57,58,59

08649 08651

Daughter Board

Mini sensor Board

08696

Daughter Board

Finger Printer Board08650

16X

DY

DY

DDR3 VRAM

58, 59

33

http://laptop-motherboard-schematic.blogspot.com/



5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet of


JV50-TR A

USB/PCIE Routin

g

A3


<Core Design>

Title


Date: Sheet of


JV50-TR A

USB/PCIE Routin

g

A3


<Core Design>

Title


Date: Sheet of


JV50-TR A

USB/PCIE Routin

g

A3


<Core Design>


























5 4 3 2 1



5 4 3 2 1

D D

C C

B B

A A

3D3V_S0 3D3V_S5

ACZ_RST#_R 12RTC_CLK 11,35

PCLK_FWH 11,37CLK_PCI_LOM 11

PCLK_KBC 11,36

SB_GPO16 12

SB_GPO17 12

CLK_PCI4 11

P CI _A D2 4 1 1P CI _A D2 5 1 1

P CI _A D2 6 1 1P CI _A D2 7 1 1P CI _A D2 8 1 1P CI _A D2 9 1 1P CI _A D3 0 1 1

P CI _A D2 3 1 1

PCI_CLK3 11PCI_CLK2 11

Title


Date: Sheet of


ATi-SB710_STRAPPING_(5/5)

A3

15 61Tuesday, June 16, 2009JV50-TR SB

<Core Design>

Title


Date: Sheet of



A3


<Core Design>

Title


Date: Sheet of



A3


<Core Design>

REQUIRED SYSTEM STRAPS

PCLK_FWH

ENABLE PCI

ROM BOOT

EXT. RTC

(PD on X1,apply32KHz toRTC_CLK)DEFAULT

SB_GPO17 , SB_GPO16

H, H = Reserved

ROM TYPE:

H, L = SPI ROM

L, H = LPC ROM DEFAULT

L, L = FWH ROM

DISABLE PCI

ROM BOOTPULLLOW

PULL

HIGH

INTERNAL

RTC

DEFAULT

RTCCLKPCLK_KBC

CLKGEN

ENABLED

DEFAULT

CLKGENDISABLED

AZ_RST#

IMC

ENABLED

IMCDISABLED

DEFAULT

PCI_CLK2

WatchDOG

(NB_PWRGD)

ENABLED

WatchDog(NB_PWRGD)

DISABLEDDEFAULT

IGNOREDEBUG

STRAPS

USE

DEBUG

STRAPS

CLK_PCI_LOM

CLK_PCI4

RESERVED

PCI_CLK3

(Use External)

(Use Internal)

NOTE: SB700 HAS INTERNAL 15K PULL UP RESISTOR FOR RTCCLK

REQUIRED STRAPS

Reserved

PCI_AD30

PCI_AD29

DEBUG STRAPS

PCI_AD25 PCI_AD23

Note: SB700 has 15K internal PU FOR PCI_AD[30:23]

BYPASS

ACPI

BCLK

USE DEFAULT

PCIE STRAPS

USE EEPROM

PCIE STRAPS

PCI_AD24

BYPASS IDE

PLL

USE PCI

PLL

USE

SHORT

RESET

USE

LONG

RESET

USE IDE

PLL

USE ACPI

BCLK

PCI_AD26PCI_AD27

BYPASS

PCI PLL

PULL

HIGH

PCI_AD28

PULLLOW

(DEFAULT) (DEFAULT)(DEFAULT)(DEFAULT)(DEFAULT)(DEFAULT)

Reserved

Reserved

DEFAULT

R171

2 K 2 R 2 F - GP

DY

R171

2 K 2 R 2 F - GP

DY

1

2

R159

1 0 K R 2 J - 3 - GP

DY

R159

1 0 K R 2 J - 3 - GP

DY

1

2

R135

1 0 K R 2 J - 3 - GP

DY

R135

1 0 K R 2 J - 3 - GP

DY

1

2

R140

1 0 K R 2 J - 3 - GP

DY

R140

1 0 K R 2 J - 3 - GP

DY

1

2

TP133TPAD14-GP TP133TPAD14-GP

TP195TPAD14-GP

TP195TPAD14-GP

RN52SRN2K2J-1-GP

RN52SRN2K2J-1-GP

1 2

3 4

TP129TPAD14-GP

TP129TPAD14-GP

RN50SRN10KJ-5-GPRN50SRN10KJ-5-GP

1 2

3 4

R1662K2R2F-GPDYR1662K2R2F-GPDY

1

2



R160

1 0 K R 2 J - 3 - GP

DY

R160

1 0 K R 2 J - 3 - GP

DY

1

2

R136

1 0 K R 2 J - 3 - GP

DY

R136

1 0 K R 2 J - 3 - GP

DY

1

2

RN46SRN10KJ-5-GP

RN46SRN10KJ-5-GP

1 2

3 4

R145

1 0 K R 2 J - 3 - GP

DY

R145

1 0 K R 2 J - 3 - GP

DY

1

2

R153

1 0 K R 2 J - 3 - GP

DY

R153

1 0 K R 2 J - 3 - GP

DY

1

2


R155

1 0 K R 2 J - 3 - GP

DY

R155

1 0 K R 2 J - 3 - GP

DY

1

2

R430

1 0 K R 2 J - 3 - GP

DY

R430

1 0 K R 2 J - 3 - GP

DY

1

2

R429

1 0 K R 2 J - 3 - GP

R429

1 0 K R 2 J - 3 - GP

1

2


R142

1 0 K R 2 J - 3 - GP

DY

R142

1 0 K R 2 J - 3 - GP

DY

1

2


R139

1 0 K R 2 J - 3 - GP

DY

R139

1 0 K R 2 J - 3 - GP

DY

1

2














5 4 3 2 1



5 4 3 2 1

D D

C C

B B

A A

S A T A_

R X N 0

S A T A_

T X P 0

S A T A_

T X N 0

S A T A_

R X P 0

5V_S0

3D3V_S03D3V_S03D3V_S0 3D3V_S0

SATA_RXP0 13

SATA_TXP0 13

SATA_RXN0 13

SATA_TXN0 13

Title


Date: Sheet of


JV50-TR SB

HDD


<Core Design>

Title


Date: Sheet of


JV50-TR SB

HDD


<Core Design>

Title


Date: Sheet of


JV50-TR SB

HDD


<Core Design>

SATA Connector

MP

MP

D19

BAV99PT-GP-U

83.00099.K11

DY

D19

BAV99PT-GP-U

83.00099.K11

DY

1 2

3

D24

BAV99PT-GP-U

83.00099.K11

DY

D24

BAV99PT-GP-U

83.00099.K11

DY

1 2

3

D22

BAV99PT-GP-U

83.00099.K11

DY

D22

BAV99PT-GP-U

83.00099.K11

DY

1 2

3

C685

S C D1 U1 6 V 2 Z Y -2 GP

DY C685

S C D1 U1 6 V 2 Z Y -2 GP

DY

1

2

SATA1

SKT-SATA22P-27-GP

62.10065.471

2ND = 62.10065.5513RD = 62.10065.661

SATA1

SKT-SATA22P-27-GP

62.10065.471

2ND = 62.10065.5513RD = 62.10065.661

NP1

NP2

23

24

1

2345678

9101112131415

16171819202122

TC22

S C 1 0 U1 0 V 5 Z Y -1 GP

TC22

S C 1 0 U1 0 V 5 Z Y -1 GP

1

2

D21

BAV99PT-GP-U

83.00099.K11

DYD21

BAV99PT-GP-U

83.00099.K11

DY

1 2

3

D23

SS24-GP

83.2R004.08G

2ND = 83.2R004.J8M3RD = 83.2R004.H8M

D23

SS24-GP

83.2R004.08G

2ND = 83.2R004.J8M3RD = 83.2R004.H8M

A

K


5 4 3 2 1



5 4 3 2 1

D D

C C

B B

A A

S A T A_

R X N 1

S A T A_

T X N 1

S A T A_

R X P 1

S A T A_

T X P 1

ODD_MD

ODD_DP

3D3V_S03D3V_S03D3V_S0 3D3V_S0

5V_S0

SATA_TXN113SATA_TXP113

SATA_RXP113SATA_RXN113

Title


Date: Sheet of


JV50-TR SB

ODD


<Core Design>

Title


Date: Sheet of


JV50-TR SB

ODD


<Core Design>

Title


Date: Sheet of


JV50-TR SB

ODD


<Core Design>

SATA ODD Connector

MPMP

-1

D8

BAV99PT-GP-U

83.00099.K11

DY D8

BAV99PT-GP-U

83.00099.K11

DY

1 2

3

TP152TPAD14-GPTP152TPAD14-GP

1

D7

BAV99PT-GP-U

83.00099.K11

DYD7

BAV99PT-GP-U

83.00099.K11

DY

1 2

3

R16510KR2J-3-GP

DYR16510KR2J-3-GP

DY

1 2

D5BAV99PT-GP-U

83.00099.K11

DY D5BAV99PT-GP-U

83.00099.K11

DY

1 2

3

TC9 S

C 1 0 U1 0 V 5 Z Y -1 GP

TC9 S

C 1 0 U1 0 V 5 Z Y -1 GP

1

2

C430 S

C D1 U1 6 V 2 Z Y -2 GP

C430 S

C D1 U1 6 V 2 Z Y -2 GP

1

2

ODD1

SKT-SATA7P+6P-59-GP

62.10065.751

2ND = 62.10065.851

3RD = 62.10065.B01

ODD1

SKT-SATA7P+6P-59-GP

62.10065.751

2ND = 62.10065.851

3RD = 62.10065.B01

S1

S2S3S4S5S6S7

P1P2P3P4P5

13

14

P6D4

SSM24PT-GP

DY

83.2R004.H8MD4

SSM24PT-GP

DY

83.2R004.H8M

K

A

D6

BAV99PT-GP-U

83.00099.K11

DY D6

BAV99PT-GP-U

83.00099.K11

DY

1 2

3


5 4 3 2 1



5 4 3 2 1

D D

C C

B B

A A

USB_5+USB_5-

3D3V_BT_S0

3D3V_BT_S0

USB_5-USB_5+

3D3V_BT_S0

3D3V_S03D3V_BT_S0

BLUETOOTH_EN 36

USBPN5 12USBPP5 12

Title


Date: Sheet of


BLUETOOTH


JV50-TR SB

Title


Date: Sheet of


BLUETOOTH


JV50-TR SB

Title


Date: Sheet of


BLUETOOTH


JV50-TR SB

BLUETOOTH MODULE

EC21 put nearBLUE1 / allUSB put onechoke nearconnector by

EMI request

1.5A / High Active Voltage 2V

TP236 AFTE14P-GP TP236 AFTE14P-GP1

EC98SCD1U16V2ZY-2GP

DYEC98SCD1U16V2ZY-2GP

DY 1

2

R5270R0402-PADR5270R0402-PAD

12

BT1 ACES-CON4-1-GP-U2

20.D0197.1042ND = 20.F0984.004

BT1 ACES-CON4-1-GP-U2

20.D0197.1042ND = 20.F0984.004

432

1

5

6

C920SC4D7U10V5ZY-3GP

DY

C920SC4D7U10V5ZY-3GP

DY1 2

R5280R0402-PADR5280R0402-PAD

12TP237 AFTE14P-GP TP237 AFTE14P-GP1

TP235 AFTE14P-GP TP235 AFTE14P-GP1

U68

G5240B1T1U-GP

74.05240.A7F2ND = 74.09711.A7F

U68

G5240B1T1U-GP

74.05240.A7F2ND = 74.09711.A7F

OUT1

GND2

NC#33

EN 4

IN 5


5 4 3 2 1

5V_USB1_S0

USB1

USB1USB1

6



5 4 3 2 1

D D

C C

B B

A A

USBPN0 USBPP0

USBPN2 USBPP2

USB_OC#4

USBPN1

USBPP1

USB_PWR_EN#

USB_0+USB_0-

USB_2+USB_2-

5V_USB1_S05V_USB1_S0

5V_S5

5V_S5

5V_USB1_S0

5V_USB1_S0

5V_USB1_S0

USB_OC#0 12

USB_OC#412

USB_PWR_EN#36

USBPN312USBPP312

USBPN112

USBPP112

USBPN012USBPP012

USBPN212USBPP212

Title


Date: Sheet of


USB


JV50-TR SB

Title


Date: Sheet of


USB


JV50-TR SB

Title


Date: Sheet of


USB


JV50-TR SB

100 mil USB2

1.U75 as close to the USB2 as possible

2.U76 as close to the USB1 as possible

2008/11/06

-1

-1

R1330R0402-PADR1330R0402-PAD

12

EC79 S C D1 U1 6 V 2 Z Y -2 GP

DYEC79 S

C D1 U1 6 V 2 Z Y -2 GP

DY

1

2

TC24 S E 2 2 0 U 6 D 3 V M-7 GP

DYTC24 S

E 2 2 0 U 6 D 3 V M-7 GP

DY

1

2

R1560R0402-PADR1560R0402-PAD

12

EC84SCD1U16V2ZY-2GP

DY

EC84SCD1U16V2ZY-2GP

DY

1

2

R1570R0402-PADR1570R0402-PAD

12

SKT-1394-4P-27-GP-U

22.10218.T512ND = 22.10321.1113RD = 22.10218.W514TH = 22.10218.P01

SKT-1394-4P-27-GP-U

22.10218.T512ND = 22.10321.1113RD = 22.10218.W514TH = 22.10218.P01

5

1

234

6

USB3

SKT-1394-4P-27-GP-U

22.10218.T512ND = 22.10321.1113RD = 22.10218.W514TH = 22.10218.P01

USB3

SKT-1394-4P-27-GP-U

22.10218.T512ND = 22.10321.1113RD = 22.10218.W514TH = 22.10218.P01

5

1

234

6

U17

AOZ8001J-GP-U1

83.08000.AAE

DY

U17

AOZ8001J-GP-U1

83.08000.AAE

DY

1

2 3

4

C836SC4D7U6D3V3MX-2GPC836SC4D7U6D3V3MX-2GP

1

2

EC85

S C D1 U1 6 V 2 Z Y -2 GP

DYEC85

S C D1 U1 6 V 2 Z Y -2 GP

DY

1

2

TP173 AFTE14P-GPTP173 AFTE14P-GP1


U54

RT9715DGF-GP

74.09715.079

2ND = 74.00547.A79

U54

RT9715DGF-GP

74.09715.079

2ND = 74.00547.A79

GND1

VIN2

VIN3

EN#4 FLG# 5VOUT 6VOUT 7VOUT 8

USBCN1

ACES-CON15-8-GP -U1

20.F1290.015

2ND = 20.F1035.0153RD = 21.D0214.115

USBCN1

ACES-CON15-8-GP -U1

20.F1290.015

2ND = 20.F1035.0153RD = 21.D0214.115

432

1

56789

1011

12131415

16

17

U14

AOZ8001J-GP-U1

83.08000.AAE

DY

U14

AOZ8001J-GP-U1

83.08000.AAE

DY

1

2 3

4

EC83

S C 1 0 0 0 P 5 0 V 3 J N - G P - U

DY EC83

S C 1 0 0 0 P 5 0 V 3 J N - G P - U

DY 1

2

C837

S C 1 U1 0 V 3 Z Y - 6 GP

C837

S C 1 U1 0 V 3 Z Y - 6 GP

1

2

TC29 S E 2 2 0 U 6 D 3 V M-7 GP

79.22710.6AL2ND = 77.92271.021

TC29 S E 2 2 0 U 6 D 3 V M-7 GP

79.22710.6AL2ND = 77.92271.021

1

2


R1340R0402-PADR1340R0402-PAD

12




A B C D E

1.route on bottom as differential pairs.

LAN Connector



A B C D E

4 4

3 3

2 2

1 1

CONN_PWR2CONN_PWR

10M/100M/1G_LED#

LAN_ACT_LED#

MCT4

M C T _R

MCT3MCT2MCT1

RJ45_1

RJ45_8

RJ45_6

RJ45_3RJ45_2

RJ45_7

RJ45_5RJ45_4

CONN_PWR

XRF_TDC RJ45_6

RJ45_2

RJ45_3

RJ45_1

MCT1

MCT2

RJ45_4

RJ45_5

RJ45_7

RJ45_8

MCT4

MCT3

CONN_PWR2

3D3V_LAN_S5

2D5V_1D2V_LAN

10M/100M/1G_LED#26

MDI1-26

MDI1+26

MDI0-26

MDI0+26

MDI3+26

MDI3-26

MDI2+26

MDI2-26

LAN_ACT_LED#26

Title


Date: Sheet of


SB

LAN CONN A3

27 61Tuesday, June 16, 2009JV50-TR

Title


Date: Sheet of


SB

LAN CONN A3


Title


Date: Sheet of


SB

LAN CONN A3


DOC_TIP,DOC_RING,TIP,RING:W/S : 10/100 @ Surface layers 10/20 @ Inner layers

LAN Connector

2.Tx+/Tx- are pairs. Rx+/Rx- are pairs.

3.No vias, No 90 degree bends.4.pairs must be equal lengths.5.6mil trace width,12mil separation.6.36mil between pairs and any other trace.7.Must not cross ground moat,except

RJ-45 moat.

GIGA Lan TransformerA2(+) A1(-)::GREEN

A2(+) A3(-):ORANGE

B1(+) B2(-):YELLOW

1ST 68.HD081.30B

1ST 68.HD081.30B

C31 S C D1 U1 6 V 2 Z Y -2 G

P

C31 S C D1 U1 6 V 2 Z Y -2 G

P

1

2

EC11

S C 1 0 0 P 5 0 V 2 J N- 3 GP

DY

EC11

S C 1 0 0 P 5 0 V 2 J N- 3 GP

DY 1

2

C11SC1KP50V2KX-1GP

DYC11SC1KP50V2KX-1GP

DY

RJ45

RJ45-125-GP-U1

22.10277.0212ND = 22.10277.231

RJ45

RJ45-125-GP-U1

22.10277.0212ND = 22.10277.231

A1 A2 A3

1

2345678

B1

B2

9

10

R150R2J-2-GP

DY

R150R2J-2-GP

DY

1 2

C570

SC1KP2KV8KX-GP

C570

SC1KP2KV8KX-GP 1

2

RN5

SRN470J-3-GP

RN5

SRN470J-3-GP

1234 5

678

XF2

XFORM-271-GP

2ND = 68.68160.30B

XF2

XFORM-271-GP

2ND = 68.68160.30B

1

2

3 10

9

11

7

8

6

12

4

5

EC60

S C 1 0 0 P 5 0 V 2 J N- 3 GP

DY

EC60

S C 1 0 0 P 5 0 V 2 J N- 3 GP

DY 1

2

C558SC1KP50V2KX-1GP

DYC558SC1KP50V2KX-1GP

DY

C16

S C D1 U1 6 V 2 Z Y

-2 GP

C16

S C D1 U1 6 V 2 Z Y

-2 GP

1

2

RN77

SRN75J-1-GP

RN77

SRN75J-1-GP

1 2 3 4

5 6 7 8

C39 S C D1 U1 6 V 2 Z Y -2 G

P

C39 S C D1 U1 6 V 2 Z Y -2 G

P

1

2

XF1

XFORM-271-GP

2ND = 68.68160.30B

XF1

XFORM-271-GP

2ND = 68.68160.30B

1

2

3 10

9

11

7

8

6

12

4

5

C14

S C D1 U1 6 V 2 Z Y

-2 GP

C14

S C D1 U1 6 V 2 Z Y

-2 GP

1

2














5 4 3 2 1

NEWCARD Connector



5 4 3 2 1

D D

C C

B B

A A

PCIE_WAKE#_NEW

NEW_PIN16

CPUTSB#

CPPE#

USBPP9_1USBPN9_1

CONN_TP2CONN_TP1

RXP5

TPS2231_PERST#

RXN5

SMB_DATA_NEWSMB_CLK_NEW

TPS2231_PERST#CPUTSB#CPPE#

PLT_RST1#_NEWCARDPLT_RST1#_NEWCARD

3D3V_NEW_S0

3D3V_NEW_LAN_S5

1D5V_NEW_S0

3 D3 V_ NE W_ S0 1 D5 V_ NE W _S03D3V_S0 3D3V_NEW_LAN_S5

3D3V_NEW_LAN_S5

3D3V_S5

1D5V_NEW_S01D5V_S0

3D3V_NEW_S03D3V_S0

3D3V_S0

3D3V_NEW_S0

1D5V_NEW_S01D5V_S0

3D3V_S5

CLK_PCIE_NEW3CLK_PCIE_NEW#3

PCIE_TXP58PCIE_TXN58

PCIE_WAKE#12,26

SMB_DATA12,26,33SMB_CLK12,26,33

CPPE#12

PCIE_RXP58PCIE_RXN58

USBPN912

USBPP912

PM_SLP_S3#12,35,36,42,44,49,60,61

PM_SLP_S5#12,36,48

PLT_RST1#_B11,32,33,37,53

Title


Date: Sheet of


NEW CARD


JV50-TR SB

Title


Date: Sheet of


NEW CARD


JV50-TR SB

Title


Date: Sheet of


NEW CARD


JV50-TR SB

Place them Near to ConnectorPlace them Near to Chip

TP167TP167

R226 0R2J-2-GPDY

R226 0R2J-2-GPDY1 2

C512SCD1U16V2ZY-2GP

DY

C512SCD1U16V2ZY-2GP

DY

1

2

TP161TP161

C533SC100P50V2JN-3GP

DYC533

SC100P50V2JN-3GP

DY12

C510SC1U10V3ZY-6GP

DY

C510SC1U10V3ZY-6GP

DY

1

2

NEW1

CARDBUS26P-20GP-U

62.10081.131

DY

NEW1

CARDBUS26P-20GP-U

62.10081.131

DYNP1

1

23456789

1011121314151617181920212223242526

NP2

RN64

SRN33J-5-GP-U

DYRN64

SRN33J-5-GP-U

DY12 3

4

C 53 2 S CD 1U 16 V2 KX -3 GPDY

C 53 2 S CD 1U 16 V2 KX -3 GPDY

1 2

C503

S C D1 U1 6 V 2 Z Y -2 GP

DY

C503

S C D1 U1 6 V 2 Z Y -2 GP

DY

1

2

NEW2

CARDBUS2P-21-GP-U

21.H0182.001

DYNEW2

CARDBUS2P-21-GP-U

21.H0182.001

DY

1 2

C 53 1 S CD 1U 16 V2 KX -3 GP

DYC 53 1 S CD 1U 16 V2 KX -3 GP

DY1 2

C518

S C D1 U1 6 V 2 Z Y -2 GP

DY

C518

S C D1 U1 6 V 2 Z Y -2 GP

DY

1

2

R210 0R2J-2-GPDY

R210 0R2J-2-GPDY

1 2

R242

0R2J-2-GP

DY R242

0R2J-2-GP

DY12

TP162TP162

C520SC1U10V3ZY-6GP

DY

C520SC1U10V3ZY-6GP

DY

1

2

RN71

SRN100KJ-6-GP

DY

RN71

SRN100KJ-6-GP

DY12 3

4

R207 0R2J-2-GP

DYR207 0R2J-2-GP

DY1 2

C543SCD1U16V2ZY-2GP

DY

C543SCD1U16V2ZY-2GP

DY

1

2

U26

W83L351YG-GP

74.83351.073

DY

U26

W83L351YG-GP

74.83351.073

DY

G N D

7

G N D

2 1

NC#44

NC#55

NC#13 13

NC#14 14

N C # 1 6

1 6

1_5VIN 12

1_5VOUT 11

3_3VIN2

3_3VOUT3

STBY#1

S Y S

R S T #

6

P E R

S T #

8

C P U

S B #

9

C P P

E #

1 0

R C L K E N

1 8

O C #

1 9

S H D N #

2 0

A U X I N

1 7

AUXOUT 15






5 4 3 2 1

3D3V AUX S5



5 4 3 2 1

D D

C C

B B

A A

BIOS_DOSPI_WP#

SPI_HOLD#

LPC_LAD[0..3]

SPI_HOLD#

BIOS_DIO

BIOS_VCC

BIOS_CLK

3D3V_AUX_S5

3D3V_S0

3D3V_AUX_S5

SPIDI36SPICS#36

SPI_WP#36

PCLK_FWH11,15

LPC_LAD011,36LPC_LAD111,36LPC_LAD211,36LPC_LAD311,36

LPC_LFRAME#11,36

PLT_RST1#_B11,32,33,34,53

LPC_LAD[0..3]11,36

SPIDO 36SPICLK 36

Title


Date: Sheet of


JV50-TR SB

BIOS

A337 61Tuesday, June 16, 2009

<Core Design>

Title


Date: Sheet of


JV50-TR SB

BIOS


<Core Design>

Title


Date: Sheet of


JV50-TR SB

BIOS


<Core Design>

16M Bits

SPI FLASH ROM

GOLDEN FINGER FOR DEBUG BOARD

SB

-1

RN94

SRN10KJ-6-GP

RN94

SRN10KJ-6-GP

1 2 3 4

5 6 7 8

EC76 S C 4 D7 P 5 0 V 2 C N-1 GP

DYEC76 S

C 4 D7 P 5 0 V 2 C N-1 GP

DY

1

2

EC78 S C 4 D7 P 5 0 V 2 C N-1 GP

DYEC78 S

C 4 D7 P 5 0 V 2 C N-1 GP

DY

1

2

R106

0R0603-PAD

R106

0R0603-PAD

1

2

EC75 S C 4 D7 P 5 0 V 2 C N-1 GP

DYEC75 S

C 4 D7 P 5 0 V 2 C N-1 GP

DY

1

2

E R3 0 R0 40 2- PA DE R3 0 R0 40 2- PA D1 2

ER433R2J-2-GP

ER433R2J-2-GP1 2

EC34SCD1U16V2ZY-2GP

DY

EC34SCD1U16V2ZY-2GP

DY

1

2

E R2 0 R0 40 2- PA DE R2 0 R0 40 2- PA D1 2

U9

MX25L1605DM2I-12G-GP

72.25165.A01

2ND = 72.25X16.A01

U9

MX25L1605DM2I-12G-GP

72.25165.A01

2ND = 72.25X16.A01

CS#1

SO/SIO12

WP#/ACC3

GND4

VCC 8

HOLD# 7

SCLK 6

SI/SIO0 5

DB1

MLX-CON10-7-GP

20.D0183.110

DY

DB1

MLX-CON10-7-GP

20.D0183.110

DY

123456789

101112

EC77

S C 4 D7 P 5 0 V 2 C N-1 GP

DYEC77

S C 4 D7 P 5 0 V 2 C N-1 GP

DY

1

2


5 4 3 2 1

5V S0

TOUCH PADTP62AFTE14P-GP TP62AFTE14P-GP 1



5 4 3 2 1

D D

C C

B B

A A

TP_RIGHT

TP_DATATP_CLKTP_LEFT

5V_S0

3D3V_FP_S0

TP_LEFT

USBPN6_1USBPP6_1

TP_RIGHT

TP_RIGHT

TP_LEFT

3D3V_FP_S0

USBPN6_1USBPP6_1

FP_DETECT#FP_ID

TP_CLKTP_DATA

TPCLKTPDATA

3D3V_S0

5V_S05V_S0

USBPP612USBPN612

FP_DETECT#36

FP_ID12

TPDATA36TPCLK36

Title


Date: Sheet of


JV50-TR SB

Touch P AD/Finger printer

A3


<Core Design>

Title


Date: Sheet of


JV50-TR SB


A3


<Core Design>

Title


Date: Sheet of


JV50-TR SB


A3


<Core Design>

Finger printer

-1

FPCN1

PTWO-CON12-3-GP-U

20.K0370.0122ND = 20.K0315.012

FPCN1

PTWO-CON12-3-GP-U

20.K0370.0122ND = 20.K0315.012

432

1

56789

101112

13

14

RN85

SRN33J-5-GP-U

RN85

SRN33J-5-GP-U

12 3

4

TP126 AFTE14P-GP TP126 AFTE14P-GP 1

EC23 S C 1 0 0 P 5 0 V 2 J N- 3 GP

DY

EC23 S C 1 0 0 P 5 0 V 2 J N- 3 GP

DY 1

2

R427

0R0603-PAD

R427

0R0603-PAD

1

2

RN83

SRN10KJ-5-GP

RN83

SRN10KJ-5-GP

1 2

3 4

R149 0R0402-PADR149 0R0402-PAD1 2


TP62 AFTE14P GP TP62 AFTE14P GP 1

EC73 S C 1 0 0 P 5 0 V 2 J N- 3 GP

DY

EC73 S C 1 0 0 P 5 0 V 2 J N- 3 GP

DY 1

2

TPCN1

PTWO-CON12-3-GP-U

20.K0370.0122ND = 20.K0315.012

TPCN1

PTWO-CON12-3-GP-U

20.K0370.0122ND = 20.K0315.012

432

1

56789

101112

13

14

EC22 S C 1 0 0 P 5 0 V 2 J N- 3 GP

DY

EC22 S C 1 0 0 P 5 0 V 2 J N- 3 GP

DY 1

2


EC74 S C 1 0 0 P 5 0 V 2 J N- 3 GP

DY

EC74 S C 1 0 0 P 5 0 V 2 J N- 3 GP

DY 1

2




EC26 S C D1 U1 0 V 2 K X -4 GP

DYEC26 S C D1 U1 0 V 2 K X -4 GP

DY

1

2

R150 0R0402-PADR150 0R0402-PAD1 2









5 4 3 2 1

3D3V_S02D5V_S0

34



5 4 3 2 1

D D

C C

B B

A A

2D5V_S0_PG

RUNPWROK_D

3D3V_S5

1D8V_S3

SB_PWRGD 12

1D8V_S3_PWRGD48

PM_SLP_S3#12,34,35,36,44,49,60,61

RUNPWROK35

1D1V_PWRGD47

VCORE_EN 45,47

3V/5V_POK46

PM_SLP_S3#12,34,35,36,44,49,60,61

1D1V_PWRGD 47VRM_PWRGD45

NB_PWRGD 9,12

RUNPWROK_D 3

Title


Date: Sheet of


JV50-TR SB

POWER ON LOGIC

A3


<Core Design>

Title


Date: Sheet of


JV50-TR SB

POWER ON LOGIC

A3


<Core Design>

Title


Date: Sheet of


JV50-TR SB

POWER ON LOGIC

A3


<Core Design>

P/H @ 1D8V_S3 PAGE

PH in page 3

SB

RN99

SRN100KJ-6-GP

RN99

SRN100KJ-6-GP

1 2

3 4

D27

BAW56-5-GP 83.00056.Q11

3RD = 83.00056.K112ND = 83.00056.G11

D27

BAW56-5-GP 83.00056.Q11

3RD = 83.00056.K112ND = 83.00056.G11

1

2

3

D3

BAW56-5-GP

83.00056.Q11

2ND = 83.00056.G113RD = 83.00056.K11

D3

BAW56-5-GP

83.00056.Q11

2ND = 83.00056.G113RD = 83.00056.K11

1

2

3

R457

0R2J-2-GP

DYR457

0R2J-2-GP

DY1 2

R456

0R2J-2-GP

DYR456

0R2J-2-GP

DY1 2

. ..

.

.

Q9

2N7002E-1-GP

84.2N702.D312ND = 84.2N702.E31

. ..

.

.

Q9

2N7002E-1-GP

84.2N702.D312ND = 84.2N702.E31

G

S

D

R120

0R2J-2-GP

DYR120

0R2J-2-GP

DY1 2

C825

SC1U10V3ZY-6GP

C825

SC1U10V3ZY-6GP

12

U16C

TSLVC08APW-1-GP

73.07408.L162ND = 73.07408.L153RD = 73.07408.02B U16C

TSLVC08APW-1-GP

73.07408.L162ND = 73.07408.L153RD = 73.07408.02B

9

108

1 4

7


5 4 3 2 1

(I)AD_OFF

Adapter

Input Signal

(O)

Output SignalAD_IN#

EN0

DCDC 5V/3D3V(RT8205A)

Input Signal Output Signal

DCDC 1D2V(TPS51124)


1D2V PWRGD



5 4 3 2 1

D D

C C

B B

A A

Title


Date: Sheet of


JV50-TR SB

Power Block Diagram


<Core Design>

Title


Date: Sheet of


JV50-TR SB

Power Block Diagram


<Core Design>

Title


Date: Sheet of


JV50-TR SB

Power Block Diagram


<Core Design>

Input Power Output Power

3D3V_S0

2D5V LDO


2D5V_S0

R9161

3D3V_S5

5V_S5

V(O)+VCHGR

ACOK

DCIN AD+

V(I)

V(I)DCBATOUT

VCC_VORE0

VCC_CORE1

VCC_CORE(O)

VCC_CORE(O)

ENABLE

SVC

SVDCPU_SVD

CPU_SVC

VCORE_EN

CPU_PWRGD_SVID_REG

VCLK+15V_ALW

ACIN

Input Power

MAX8731A ACIN

Output Power

CHARGER MAX8731


SDA

SCL

PBAT_SMBDAT

PBAT_SMBCLK

VDDSMB3D3V_AUX_S5

MAX8731A ACOK

VTT1D2V_S0

CPU_COREISL6265HRTZ

VCC

PGOOD

+5V_RUN

PWROK

VRM_PWRGD

DCBATOUT VIN

VDDNB VCC_CORE(O)

Output Power


Input Power

VCC(I)


AD_JK VCC(O)

AD+


1D5V LDO


1D5V_S0

VIN

Input Power

S5_ENABLE

Output Power

DCBATOUT

PGOOD

VREG33D3V_AUX_S5

3V/5V OK

VREG5 5V_AUX_S5

Input Power

PM_SLP_S5#

Output Power

DCDC 1D8V(RT8209B)Input Signal

PGOOD

Output Signal

VTT1D8V_S3

1D8V_S3_PWRGD

V5IN

5V_S5

V5FILT

EN_PSV

Input Power

VCORE_EN

Output Power

PGOOD

_

V5DRV

5V_S5

V5FILT

EN_PSV


DCDC 1D1V(TPS51124)

Input Signal

PGOOD

Output Signal

VTT V5DRV

+5V_SUS

ENTRIP1

ENTRIP2

VOUT

VOUT

1D2V_PWRGD

DCBATOUT

1D1V_PWRGD

1D2V_S0

LDO_OUT

LDO_SHDN#


1D8V_S3

0D9V LDO

Input Signal

LDO_POK

Output Signal

LDO_OUT0D9V_S3

RT9026

EN_PSV

V(I)DCBATOUT

VIN

VLDOIN

PM_SLP_S5#

5V_S5


3D3V_S5

1D2V LDO


OUT1D2V_S5

G9161

IN

IN OUT

G9571

3D3V_S0

IN OUT












5 4 3 2 1



5 4 3 2 1

D D

C C

B B

A A

9025_FB

9025_POK

9025_EN

3D3V_S0

1D5V_S01D5V_S0_LDO

2D5V_S0

3D3V_S0

1D2V_S53D3V_S5

2D5V_LDO

5V_S5

1D1V_M92

1D8V_S3

1D1V_M92_PWR

3D3V_S0

PM_SLP_S3#12,34,35,36,42,44,60,61

PE_GPIO111,44,60,61

Title


Date: Sheet of


JV50-TR SB

LDO 2D5V/1D5V/1D2V_S5 A3


<Core Design>

Title


Date: Sheet of


JV50-TR SB



<Core Design>

Title


Date: Sheet of


JV50-TR SB



<Core Design>

Place near to SB700

1D5V_S0Iomax=1A

G957

2D5VIomax=0.2A

1D2V_S5Iomax=400mA

Place near to CPU

For MINI Card.NEW Card power SW

DY

Iomax=0.8A

Vo=0.8*(1+(R1/R2))

for TR

-1

-1

C775

S C 1 0 0 P 5 0 V 2 J N- 3 GP

DIS_MUXC775

S C 1 0 0 P 5 0 V 2 J N- 3 GP

DIS_MUX 1

2

U66

G957T65UF-GP

74.95765.03CDY

U66

G957T65UF-GP

74.95765.03CDY

VIN 1GND

2VOUT 3

C412 S C 1 0 U 6 D 3 V 5 K X -1 GP

C412 S C 1 0 U 6 D 3 V 5 K X -1 GP

1

2

R42020KR2F-L-GPDIS_MUXR42020KR2F-L-GPDIS_MUX

1

2

C776 S C 1 0 U1 0 V 5 Z Y -1 GP

DIS_MUX

C776 S C 1 0 U1 0 V 5 Z Y -1 GP

DIS_ MUX

1

2

C803SC1U10V3ZY-6GP

DIS_MUX

C803SC1U10V3ZY-6GP

DIS_MUX

1

2

C771

S C 1 0 U1 0 V 5 Z Y -1 GP

DYC771

S C 1 0 U1 0 V 5 Z Y -1 GP

DY 1

2

G86

GAP-CLOSE-PWR

G86

GAP-CLOSE-PWR

1 2

R447

0R2J-2-GP

DISR447

0R2J-2-GP

DIS

1 2

G74

GAP-CLOSE-PWR-3-GP

G74

GAP-CLOSE-PWR-3-GP

1 2

C820SC10U10V5ZY-1GP

DY

C820SC10U10V5ZY-1GP

DY 1

2

U18

G9161-120U65U-GP

74.09161.E3C

U18

G9161-120U65U-GP

74.09161.E3C

I N

1

G N D

2

O U T

3

R579

0R2J-2-GP

TR-MUX

R579

0R2J-2-GP

TR-MUX

1 2

C819

SC10U10V5ZY-1GP

DIS_MUX

C819

SC10U10V5ZY-1GP

DIS_MUX

1

2

C918

SC10U6D3V5KX-1GP

DYC918

SC10U6D3V5KX-1GP

DY 1

2

C413 S C 1 0 U 6 D 3 V 5 K X -1 GP

C413 S C 1 0 U 6 D 3 V 5 K X -1 GP

1

2

C913SC1U10V3KX-3GPDYC913SC1U10V3KX-3GPDY

1

2

G111

GAP-CLOSE-PWR-3-GP

G111

GAP-CLOSE-PWR-3-GP

1 2

C410 S C 1 U1 0 V 3 K X - 3 GP

DY

C410 S C 1 U1 0 V 3 K X - 3 GP

DY

1

2

C761

S C 2 2 U 6 D 3 V 5 MX -2 GP

C761

S C 2 2 U 6 D 3 V 5 MX -2 GP

1

2

R4218K25R2F-1-GP

DIS_MUX

R4218K25R2F-1-GP

DIS_MUX 1

2

U48

RT9025-25PSP-GP

DIS_MUX

74.09025.03D

U48

RT9025-25PSP-GP

DIS_MUX

74.09025.03D

PGOOD1

EN2 VIN3 VDD4 NC#5 5

VOUT 6

ADJ 7

GND 8

G N D

9

C782 S C 1 U1 0 V 3 Z Y - 6 GP

C782 S C 1 U1 0 V 3 Z Y - 6 GP

1

2

C411 S C 1 0 U 6 D 3 V 5 K X -1 GP

DY

C411 S C 1 0 U 6 D 3 V 5 K X -1 GP

DY

1

2

C866

SCD1U25V3ZY-1GP

DYC866

SCD1U25V3ZY-1GP

DY 1

2

G85

GAP-CLOSE-PWR

G85

GAP-CLOSE-PWR

1 2

R4462K2R2J-2-GPDIS_MUXR4462K2R2J-2-GPDIS_MUX

1

2

U47

RT9161-A-25PG-GP

74.09161.F3C

U47

RT9161-A-25PG-GP

74.09161.F3C

GND 1VIN 2

VOUT 3

G110

GAP-CLOSE-PWR-3-GP

G110

GAP-CLOSE-PWR-3-GP

1 2
























5 4 3 2 1

D D1D8V_S3

5V S5

1D5V_S0Iomax=3.16AOCP>6A



5 4 3 2 1

C C

B B

A A

5912_EN

5912_POK1D5V_PWRGD

5912_FB

1D5V_M92

5V_S5

PE_GPIO111,44,49,60

PM_SLP_S3#12,34,35,36,42,44,49,60

Title


Date: Sheet of


JV50-TR SB

APL5912_1D5V_VRAM POWER

A3


<Core Design>

Title


Date: Sheet of


JV50-TR SB


A3


<Core Design>

Title


Date: Sheet of


JV50-TR SB


A3


<Core Design>

for TR SO-8-P

Vo(cal.)=1.5096V

Vo=0.8*(1+(R1/R2))

-1

-1

-1

-1 -1

C878

S C 1 0 U 6 D

3 V 5 K X - 1 G P

DIS_MUX

C878

S C 1 0 U 6 D

3 V 5 K X - 1 G P

DIS_MUX 1

2

TP260

TPAD14-GP

TP260

TPAD14-GP1

R6220R2J-2-GP

DISR622

0R2J-2-GP

DIS1 2

R6260R2J-2-GP

TR-MUXR626

0R2J-2-GP

TR-MUX1 2

C870

S C 1 0 U 6 D

3 V 5 K X - 1 G P

DIS_MUX

C870

S C 1 0 U 6 D

3 V 5 K X - 1 G P

DIS_MUX 1

2

R6240R2J-2-GP

DYR624

0R2J-2-GP

DY12

C882

S C 4 7 P 5 0 V 2 J N - 3 G P

DIS_MUX

C882

S C 4 7 P 5 0 V 2 J N - 3 G P

DIS_MUX 1

2

C879

S C 1 0 U 6 D 3 V 5 K X - 1 G P

DIS_MUX

C879

S C 1 0 U 6 D 3 V 5 K X - 1 G P

DIS_MUX 1

2

R62526K7R3F-GP

DIS_MUX

R62526K7R3F-GP

DIS_MUX 1

2

R62330K1R3F-GP

DIS_MUX

R62330K1R3F-GP

DIS_MUX 1

2

C869

S C D1 U2 5 V 3 Z Y -1 GP

DYC869

S C D1 U2 5 V 3 Z Y -1 GP

DY

1

2

C883

S C 1 0 U 6 D 3 V 5 K X - 1 G P

DIS_MUX

C883

S C 1 0 U 6 D 3 V 5 K X - 1 G P

DIS_MUX 1

2

C877

SC1U10V3KX-3GP

DIS_MUXC877

SC1U10V3KX-3GP

DIS_MUX

1

2

U62

APL5912-KAC-GP

DIS_MUX

74.05912.A71

U62

APL5912-KAC-GP

DIS_MUX

74.05912.A71

G N D

1

FB 2

VOUT 3

VOUT 4

VIN 5

V C N T L

6

POK7

EN8

VIN 9


Date post:	09-Feb-2018
Category:	Documents
Upload:	pepegotera454
View:	214 times
Download:	0 times

5542g_129716449-Aspire-5542-5542G-schematic

Documents