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Amplifier DesignGuide

August 2005

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Acknowledgments

Mentor Gra phics is a t ra dema rk of Mentor Gra phics Corporat ion in th e U.S. and

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Contents1 Amplifier QuickStart Guide

Using DesignGuides................................................................................................. 1-1

Accessing the Documentation............................................................................ 1-3

Basic Procedures ..................................................................................................... 1-3

Selecting the Appropriate Simulation Type............................................................... 1-7

DC and Bias Point Simulations........................................................................... 1-7

S-Parameter Simulations.................................................................................... 1-8

Nonlinear Simulations......................................................................................... 1-8

Tools ......................................................................................................................... 1-15

2 Introduction

List of Available Data Displays.................................................................................. 2-2

References for Power Amplifier Examples ............................................................... 2-10

3 DC and Bias Point Simulations

DC and Bias Point Simulations > BJT I-V Curves, Class A Power, Eff., Load, Gm vs. Bias

3-2

DC and Bias Point Simulations > BJT Output Power, Distortion vs. Load R ............ 3-4

DC and Bias Point Simulations > BJT Fmax vs. Bias............................................... 3-5

DC and Bias Point Simulations > BJT Ft vs. Bias..................................................... 3-6

DC and Bias Point Simulations > BJT Noise Fig., S-Params, Gain, Stability, and Circles vs.

Bias ........................................................................................................................ 3-7

DC and Bias Point Simulations > BJT Stability vs. Bias ........................................... 3-10

DC and Bias Point Simulations > FET I-V Curves, Class A Power, Eff., Load, Gm vs. Bias3-11

DC and Bias Point Simulations > FET Output Power, Distortion vs. Load R............ 3-13

DC and Bias Point Simulations > FET Fmax vs. Bias .............................................. 3-14

DC and Bias Point Simulations > FET Ft vs. Bias .................................................... 3-15

DC and Bias Point Simulations > FET Noise Fig., S-Params, Gain, Stability, and Circles vs.

Bias ........................................................................................................................ 3-16

DC and Bias Point Simulations > FET Stability vs. Bias........................................... 3-19

4 S-Parameter Simulations

S-Parameter Simulations > S-Params., Noise Fig., Gain, Stability, Circles, and Group Delay4-2

S-Parameter Simulations > Feedback Network Optimization to Attain Stability ....... 4-5

S-Parameter Simulations > S-Params, Gain, NF, Stability, Group Delay vs. Swept

Parameters............................................................................................................. 4-6

S-Parameter Simulations > S-Params., Stability, and Group Delay vs. Frequency and Input

Power ..................................................................................................................... 4-9
http://-/?-

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5 1-Tone Nonlinear Simulations

1-Tone Nonlinear Simulations > Spectrum, Gain, Harmonic Distortion.................... 5-2

1-Tone Nonlinear Simulations > Spectrum, Gain, Harmonic Distortion (w/PAE)...... 5-3

1-Tone Nonlinear Simulations > Spectrum, Gain, Harmonic Distortion vs. Power ... 5-5

1-Tone Nonlinear Simulations > Spectrum, Gain, Harmonic Distortion vs. Power (w/PAE)5-7

1-Tone Nonlinear Simulations > Spectrum, Gain, Harmonic Distortion vs. Frequency5-91-Tone Nonlinear Simulations > Spectrum, Gain, Harmonic Distortion vs. Frequency

(w/PAE) .................................................................................................................. 5-10

1-Tone Nonlinear Simulations > Spectrum, Gain, Harmonic Distortion vs. Frequency &

Power ..................................................................................................................... 5-12

1-Tone Nonlinear Simulations > Spectrum, Gain, Harmonic Distortion vs. Frequency &

Power (w/PAE) ....................................................................................................... 5-14

1-Tone Nonlinear Simulations > Spectrum, Gain, Harmonic Distortion at X dB Gain

Compression.......................................................................................................... 5-16


Compression vs. Freq. ........................................................................................... 5-18


Compression (w/PAE) vs. 1 Param. ....................................................................... 5-20


Compression (w/PAE) vs. 2 Params. ..................................................................... 5-22

1-Tone Nonlinear Simulations > Noise Figure, Spectrum, Gain, Harmonic Distortion 5-24

1-Tone Nonlinear Simulations > Large-Signal Load Impedance Mapping................ 5-25

1-Tone Nonlinear Simulations > Load-Pull - PAE, Output Power Contours.............. 5-26

1-Tone Nonlinear Simulations > Load-Pull - PAE, Output Power Contours at X dB Gain

Compression.......................................................................................................... 5-281-Tone Nonlinear Simulations > Source-Pull - PAE, Output Power Contours........... 5-30

1-Tone Nonlinear Simulations > Harmonic Impedance Opt. - PAE, Output Power, Gain5-32

1-Tone Nonlinear Simulations > Harmonic Gamma Opt. - PAE, Output Power, Gain 5-35

6 Statistical Design and Optimization for Amplifiers

Overview of Techniques ........................................................................................... 6-1

Yield Analysis ..................................................................................................... 6-2

Yield Optimization............................................................................................... 6-4

Yield Analysis Displays: YSH, MH, SRP ............................................................ 6-4

Statistical Design Methodology .......................................................................... 6-11Performing Yield Analysis................................................................................... 6-12

Using the Statistical Simulations .............................................................................. 6-14

Using the DesignGuide Schematics................................................................... 6-16

Selecting the Appropriate Simulation Schematic ............................................... 6-16

Selecting the Appropriate Data Display.............................................................. 6-17

Choosing Parameter Statistics ........................................................................... 6-17

Yield Analysis Schematics.................................................................................. 6-19

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Linear Analysis Using S-Parameters as Measurements .......................................... 6-20

Linear Analysis Using Group Delay and Noise Figure as Measurements................ 6-23

Linear Analysis Using S-Parameters, Group Delay and Noise Figure as Measurements6-25

Nonlinear Analysis Using 1-Tone Harmonic Balance with Harmonic Distortion and Spectrum

as Measurements .................................................................................................. 6-27

Nonlinear Analysis Using 2-Tone Harmonic Balance with Third and Fifth Order Intercepts asthe Measurements ................................................................................................. 6-29

Yield Optimization Schematics................................................................................. 6-31

Linear Optimization Using S-Parameters as Measurements.................................... 6-32

Linear Optimization Using Group Delay and Noise Figure as Measurements ......... 6-33

Linear Optimization Using S-Parameters, Group Delay and Noise Figure as Measurements

6-34

Nonlinear Optimization Using 1-Tone Harmonic Balance with Harmonic Distortion and

Spectrum as Measurements .................................................................................. 6-35

Nonlinear Optimization Using 2-Tone Harmonic Balance with Third and Fifth Order

Intercepts as Measurements.................................................................................. 6-36

7 2-Tone Nonlinear Simulations

2-Tone Nonlinear Simulations > Spectrum, Gain, TOI and 5thOI Points .................. 7-2

2-Tone Nonlinear Simulations > Spectrum, Gain, TOI and 5thOI Points (w/PAE) .... 7-3

2-Tone Nonlinear Simulations > Spectrum, Gain, TOI and 5thOI Points vs. Power.. 7-5

2-Tone Nonlinear Simulations > Spectrum, Gain, TOI and 5thOI Points vs. Power (w/PAE)

7-7

2-Tone Nonlinear Simulations > Spectrum, Gain, TOI and 5thOI Points vs. Frequency7-9

2-Tone Nonlinear Simulations > Spectrum, Gain, TOI and 5thOI Points vs. Frequency

(w/PAE) .................................................................................................................. 7-112-Tone Nonlinear Simulations > Spectrum, Gain, TOI and 5thOI Points vs. 1 Param. (w/PAE

7-13

2-Tone Nonlinear Simulations > Spectrum, Gain, TOI and 5thOI Points vs. 2 Param. (w/PAE

7-15

2-Tone Nonlinear Simulations > Load-Pull - PAE, Output Power, IMD Contours...... 7-17

2-Tone Nonlinear Simulations > Source-Pull - PAE, Output Power, IMD Contours .. 7-19

2-Tone Nonlinear Simulations > Harmonic Impedance Opt. - PAE, Output Power, Gain, IMD

7-21

2-Tone Nonlinear Simulations > Harmonic Gamma Opt. - PAE, Output Power, Gain, IMD7-24

8 Lumped 2-Element Z-Y Matching Networks

Lumped 2-Element Z-Y Matching Networks > Rload, Shunt C/L, Series C/L for Desired Z

8-2

Lumped 2-Element Z-Y Matching Networks > Rload, Series C/L, Shunt C/L for Desired Z

8-4

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Lumped 2-Element Z-Y Matching Networks > Rload, Shunt C/L, Series C/L for Desired Y

8-6

Lumped 2-Element Z-Y Matching Networks > Rload, Series C/L, Shunt C/L for Desired Y

8-8

Lumped 2-Element Z-Y Matching Networks > Rload, Shunt C/L, Series C/L to Match Series

R-C or R-L Device.................................................................................................. 8-10Lumped 2-Element Z-Y Matching Networks > Rload, Series C/L, Shunt C/L to Match Series

R-C or R-L Device.................................................................................................. 8-12

Lumped 2-Element Z-Y Matching Networks > Rload, Shunt C/L, Series C/L to Match Shunt

R-C or R-L Device.................................................................................................. 8-14

Lumped 2-Element Z-Y Matching Networks > Rload, Series C/L, Shunt C/L to Match Shunt

R-C or R-L Device.................................................................................................. 8-16

9 Lumped Multi-Element Z-Y Matching Networks

Lumped Multi-Element Z-Y Matching Networks > Rload, Series C/L, Shunt C/L, Series L/C

for Desired Z .......................................................................................................... 9-2Lumped Multi-Element Z-Y Matching Networks > Rload, Shunt C, Series L, Series C for

Desired Z ............................................................................................................... 9-3

Lumped Multi-Element Z-Y Matching Networks > Rload, Series L, Shunt C, Series L/C for

Desired Z ............................................................................................................... 9-5

Lumped Multi-Element Z-Y Matching Networks > Rload, Shunt C, Series L, Shunt C for

Desired Y ............................................................................................................... 9-6

Lumped Multi-Element Z-Y Matching Networks > Rload, Shunt C, Series L, Series C, Shun

L/C for Desired Y.................................................................................................... 9-7

Lumped Multi-Element Z-Y Matching Networks > Rload, Series C/L, Shunt C/L, Series L/C

to Match Series R-C or R-L Device........................................................................ 9-9Lumped Multi-Element Z-Y Matching Networks > Rload, Shunt C, Series L/C, Series C to

Match Series R-C or R-L Device............................................................................ 9-10

Lumped Multi-Element Z-Y Matching Networks > Rload, Series L, Shunt C, Series L/C to

Match Series R-C or R-L Device............................................................................ 9-12

Lumped Multi-Element Z-Y Matching Networks > Rload, Shunt C, Series L, Shunt C Shunt

R-C or R-L Device.................................................................................................. 9-13

Lumped Multi-Element Z-Y Matching Networks > Rload, Shunt C, Series L, Series C, Shun

L/C to Match Shunt R-C or R-L Device.................................................................. 9-14

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Chapter 1: Amplifier QuickStart GuideThe Am plifi er Qu ickS tart Gu id e is int ended to help you get sta rt ed using the

Amplifier DesignGuide effectively. For detailed r eferen ce inform ation, r efer to

subsequent cha pters of th is man ua l.

The Am plifi er DesignGu id e includes man y useful simulation setups a nd da ta

displays for am plifier design. The simu lation setu ps a re cat egorized by the t ype of

s imula t ion des ir ed and the type of model ava ilable. Mos t of the s imula t ion setups a re

for a na lysis, but th ere ar e some for synth esizing impeda nce mat ching n etwork s. The

DesignGuide is not a complete solut ion for a mplifier des igners, but provides some

useful t ools. Following ar e some feat ur e highlight s.

Simulat ions of eight high-efficiency power am plifier examples

A detailed section on st at istical design For m os t da t a d ispla ys, t h e equ a tion s a r e vis ible on a n Equ a t ion s scr een wit h in

each dat a display file, to mak e it mu ch ea sier to see wha t is being calculat ed

and how to modify it if necessa ry.

Note This ma nu al is written describing and sh owing access th rough th e cascading

men u preferen ce. If you ar e ru nn ing th e progra m th rough t he selection dia log box

met hod, the a ppear an ce a nd inter face will be slight ly different .

Using DesignGuides

All DesignGuides can be accessed in the Schemat ic window through either cascading

men us or dialog boxes. You can configu re your preferr ed meth od in t he Advan ced

Design System Main window. Select t he DesignGuid e menu.

The comm an ds in t his men u a re a s follows:

DesignGuide Studio Documentation > Developer Studio Documentation is only available

on th is men u if you ha ve inst alled th e DesignGu ide Developer St udio. It br ings up

th e DesignGu ide Developer St ud io docum ent at ion. Anoth er way to access th e

Developer S tu dio docum ent a tion is by selectin gHelp > Topics and In dex >

DesignGuid es >Design Gu id e Developer S tudio (from an y ADS pr ogra m window).

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Amplifier QuickStart Guide

DesignGuide Developer Studio > Start DesignGuide Studio is only ava ilable on t his

menu if you have insta lled the DesignGuide Developer Studio. I t launches the in it ia

Developer St udio dialog box.

Add DesignGuide brings up a directory browser in wh ich you can add a DesignGuide

to your insta llat ion. This is primar ily int ended for u se with DesignGuides th at ar e

cust om-built th rough th e Developer Stu dio.

List/Remove DesignGuide brings u p a list of your inst alled DesignGuides. Select an y

th at you would like to uninst all an d choose th e R em ove button.

Preferences brings up a dialog box th at allows you t o:

Disable the DesignGuide menu comma nds (all except Pr eferences) in th e Main

window by un checking t his box. In t he Schema tic and Layout windows, th e

complete DesignGuide menu and all of it s commands will be removed if th is box

is unchecked.

Select your preferr ed inter face meth od (cascading men us vs. dialog boxes).

Close an d rest ar t th e progra m for your preference cha nges to ta ke effect.

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Note On P C system s, Windows r esour ce issues m ight limit th e use of cascading

men us. When m ult iple windows ar e open , your system could become dest abilized.

Thu s th e dialog box menu style might be best for t hese situ at ions.

Accessing the Documentation

To access t he docum ent at ion for th e DesignGuide, select eith er of the following:

DesignGuide > Amplifier > Amplifier DesignGuide Documentation (from ADS

Schem atic window)

Help > Topics and Index > DesignGuides > Amplifier (from a ny ADS progra m

window)

Basic Procedures

The feat ur es an d cont ent of th e Am plifier DesignGu ide ar e accessible from t he

DesignGuid e men u foun d in any Advanced Design Syst em Schemat ic window, as

shown h ere

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The eight m enu selections from DC and Bias Poin t S im ulations through Lum ped

Multi-Elem ent Z-Y Matchin g N etwork s ar e for selecting var ious simula tion setu ps

an d am plifier examples. These ar e fur th er categorized, as explained in subsequen t

sections of th is docum ent .

Ea ch of th e eight men u selections from DC and Bias Poin t S im ula tion s toLum ped

Multi-Elem ent Z-Y Matchin g N etwork s ha ve additiona l selections. The men u for

schem at ics for DC an d bias point simula tions appea rs as follows.

Select ing one of these menu it ems, such as BJ T I-V Cu rves... , cop ies a schemat ic in to

your cur ren t project th at is set u p for gener at ing a bipolar jun ction tr an sistorscurrent-versus-voltage curves.

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The BJ T I-V cur ve schem at ic appears as follows.

Ea ch sch em a tic h a s a sa m ple device t h at h a s a lr ea dy been sim u la t ed. Th e sim u la t ed

results a re displayed in a dat a display file that opens au tomatically after th e

schema tic is copied int o your project. Modify th e BJ T by editing its m odel, or deleteth e device an d repla ce it with a differen t one. The red boxes enclose pa ra met ers you

should set, such a s t he r an ge of base curr ent s a nd th e ra nge of collector voltages.

After m ak ing modificat ions, run a simu lation a nd t he da ta display will upda te.

Note All schema tics have a sample device an d/or m odel, or a sa mple amp lifier. The

da ta d isplay tha t opens a ft er you make a menu select ion has pre-s imula ted da ta from

the device or amplifier. You must replace the device or amplifier on the schemat ic and

ru n a new simulation. The data display will be updat ed with th e new data .

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Following ar e th e resu lts of th e simu lation.

Mos t of t h e in for m at ion on t h is da t a disp la y a n d on ot h er s in t h e Des ign Gu id e is in aforma t t ha t engineers can easily understa nd.

Tips

We ha ve minimized th e visibility of equations t ha t you should not need to

modify. They ar e included in a separ at e Equa tions page.

Informa tion a bout items on a data display th at you would wan t t o modify is

enclosed in red boxes.

Many of th e data displays have multiple pages. Those tha t do have a note

indicat ing what inform at ion is on oth er pa ges.

If, after selecting a DesignGu ide men u comm an d th at ha s insert ed a schem at ic an d

opened a dat a display, you r e-na me th e schem at ic an d th en ru n a simu lation, the

most efficient way to display th e resu lts is to open t he da ta display file th at

corr esponded t o th e origina l schem at ic, and u pdat e th e defau lt dat aset na me (which

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is usu ally th e sam e as t he n ew na me of your schem at ic), to display your latest

simulation results.

Selecting the Appropriate Simulation Type

The Amplifier DesignGu ide is divided int o eight cat egories for d ifferen t simu lat ion

types. Your design object ive and the type of models you have available will determine

which men u selections you select fir st .

DC and Bias Point Simulations

If you h a ve a N on lin ea r F ET or BJT m odel a va ila ble, you ca n s ta r t wit h DC and Bias

Point S im ulations, as shown h ere.

These selections can be used t o deter mine da ta such a s t he following:

I-V cur ves of a device

Approxima te class A out put power a nd optimal bias point

Gm, fmax, and ft versus bias

Noise figure and S-param eters versus bias

Optimal sour ce and load impedances for ma ximum gain or minimum noise

figur e, versus bias

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Note While th is DesignGuide is ta rgeted t o power a mplifier designer s, man y of the

schema tics and da ta displays ar e quite useful for sm all-signa l or low-noise amplifier

designer s a s well.

S-Parameter Simulations

If you h ave only S-para met ers (possibly with n oise dat a) available, or wan t t o

simula te a n am plifiers sm all-signa l perform an ce, sta rt with S-Parameter

Simulations, as shown here.

These can be used t o determ ine dat a such as th e following:

Noise figure a nd NFm in, maximum available gain, and S-param eters

Optimal sour ce and load impedances to at ta in the minimum n oise figur e or

ma ximu m gain

Feedback network element values to att ain stabili ty

Noise an d available gain circles

Sta bility circles an d stability factors

Sta bility and S-para meters versus power (actually th ese require a nonlinear

model.)

Gr ou p Dela y

Nonlinear Simulations

If you h a ve a n on lin ea r d evice m odel a va ila ble a n d wa n t t h e opt im a l sou r ce a n d loa d

impedan ces at th e fun dam ent al frequen cy (to maximize out put power an d/or

power-added efficiency), use Load-Pull or Sour ce-Pull schema tics in 1-Tone N onlinea

Simulations, as sh own here.

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If you h a ve a n on lin ea r d evice m odel a va ila ble a n d wa n t t h e opt im a l sou r ce a n d loa dimpedan ces at th e fun dam ent al frequen cy (to maximize out put power an d/or

power-added efficiency, or min imize th ird- or fifth -order int erm odulat ion distort ion),

use Load-Pu ll or Sour ce-Pu ll schem at ics in 2-Tone Nonlinear Simulations, as shown

here.

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If you h a ve a n on lin ea r d evice m odel a va ila ble a n d wa n t t h e opt im a l sou r ce a n d loa d

impedan ces at the fun dament al and harmonic frequencies (to maximize output

power and/or power-added efficiency), use the Harmonic Impedance Opt or Harmonic

Gam ma Opt schema tics in 1-Tone N onlinear S im ulations, as shown here.

The differen ce between t he t wo opt imizat ions is th at in one case, you specify the

ra nges of allowed rea l an d ima gina ry impeda nces, an d in th e oth er, you specify th e

allowed reflection coefficient s as circula r r egions on th e Smith Ch ar t.

If you h a ve a n on lin ea r device m odel a va ila ble a n d wa n t t h e opt im a l sou r ce a n d loa d

impedan ces at the fun dament al and harmonic frequencies (to maximize output

power a nd /or power-added efficiency, an d m inimize int erm odulat ion d istort ion), use

th e Ha rm onic Impeda nce Optimization or Ha rm onic Gam ma Optimization

schematics in 2-Tone N onlinear S im ulation, as sh own here.

Again , the differen ce between th e two opt imizat ions is th at in one case, you specify

th e ra nges of allowed real a nd ima gina ry impedan ces, an d in t he other case you

specify the allowed reflection coefficient s a s circular regions on t he Sm ith Cha rt .

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If you a lready ha ve an a mplifier design, and you wan t t o cha ra cter ize th e nonlinea r

per form an ce over frequ ency, power, and oth er swept pa ra met ers, select t he

appr opriat e schemat ic from 1-Tone N onlinear S im ulations, as shown here.

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The selections for 2-Tone N onlinear S im ulation follow.

There are several high-efficiency power amplifier examples. Simulat ions of these can

be accessed u nder Power Am plifier Exam ples - By Class of Operation. Included ar e

Class AB thr ough Class F, with Doher ty a nd Class S examples a s well.

Amplifier sta tist ical design is a lso available. These schem at ics a nd dat a displays,

which descr ibe s teps you may take to minimize per formance var ia t ion and maximize

yield, can be accessed u nder Am plifi er S tatis tica l Design .

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If you wa n t t o gen er a te a n a r bit r ar y im peda n ce or a dm it t an ce, or m a tch t o a devices

equivalent input or out put circuit, u sing ideal, lum ped elements only, use one of th e

schematics under Lum ped 2-Elem ent Z and Y Matchin g N etwork , as sh own her e.

Lum ped, multi-elemen t m at ching net work s can also be used, as shown here.

Note The Pass ive Circuit DesignGuide includes impedan ce m at ching capa bilities.

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21/200Tools 1-15

Tools

These ut ilities pr ovide added fun ctiona lity to th is DesignGu ide. They can be seen in

the following figu re. A brief descript ion is pr ovided for each below. For more

inform at ion select th e help but ton in t he individua l ut ility.

Transistor Bias UtilityThe Transistor Bias Utility provides SmartComponents and automated-assistants for

th e design a nd simu lation of comm on r esistive an d active tr an sistor bias n etwork s.

The au tomated capabilities can determine th e tr an sistor DC para meters, design an

appr opriat e network to achieve a given bias point , and simu late a nd display the

achieved per form an ce. All SmartComponents can be modified wh en selected. You

simply select a SmartComponentan d with lit tle effort redes ign or verify th eir

performance.

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22/2001-16 Tools


Smith Chart Utility

This DesignGuide Utility provides full smith char t capabilit ies, synthesis of matching

net work s, allowing impeda nce ma tching an d plott ing of const an t

Gain/Q/VSWR/N oise circles. This guide assu mes you ha ve inst alled th e a ssociated

DesignGuide with a ppr opr iat e licens ing codewords.

Impedance Matching Utility

The Impeda nce Mat ching Ut ility perform s th e synth esis of lumped a nd distr ibuted

impedan ce m at ching n etwork s ba sed on pr ovided specificat ions. The Ut ility feat ur es

au tomat ic simula tion, sensitivity an alysis, and display setup t o ena ble simple and

efficient componen t verifica tion.

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23/2002-1

Chapter 2: IntroductionThe Am plifi er DesignGu id e has m any simulation setups a nd data displays that are

useful for am plifier design. The simu lation setu ps a re cat egorized by the t ype of

s imula t ion des ir ed and the type of model ava ilable. Mos t of the s imula t ion setups a re

for a na lysis, but th ere a re a lso some for synth esizing impedan ce ma tching networks

Note Th is m a nu a l a ssum es t h a t you a r e fa m ilia r wit h a ll of t h e ba sic ADS pr ogr a m

opera t ions. For a dditiona l inform ation, refer t o th e ADS S chem atic Capture and

Layoutmanual .

This m anu al is orga nized as follows:

Reference ta bles in t his cha pter, listing all simulat ion setu ps, with links to theappr opriat e ma nu al pages for det ailed inform at ion

Chapt ers for each type of simulation setu p, as identified on t he DesignGuide

menu (which is accessed from ADS Schematic window). Detai led information on

each simulat ion s etu p is included.

Note The Power Amplifier exam ples ar e not docum ent ed in det ail, but for th e list of

data displays, refer to Table 2-5. For a lis t of r eferences for these, r efer to References

for Power Amplifier E xam ples on pa ge 2-10.

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24/2002-2 List of Available Data Displays

Introduction

List of Available Data Displays

The ta bles th at follow list all dat a displays th at ar e included with ea ch simu lation.

Table 2-1 shows all data displays included for DC a nd Bias Point Simulat ions.

Table 2-2 shows all dat a displays used for S-Para met er Simu lations.

Table 2-1. DC and Bias Point Simu lations

Simulation Data Displays

BJT I-V Curves, Class A Power, Eff., Load,Gm vs. Bias

BJT_IV_Gm_PowerCalcs.dds, (ClassA_calcs;IV and Gm vs. Bias pages)

BJT Output Power, Distortion vs. Load R BJT_dynamic_LL.dds

BJT Fmax vs. Bias BJT_fmax_vs_bias.dds

BJT Ft vs. Bias BJT_ft_vs_bias.dds

BJT Noise Fig., S-Params, Gain, Stability, andCircles vs. Bias

BJT_SP_NF_Match_Circ.dds, (NF, SP, Gains, at allBias Pts.; Matching at 1 Bias Point; andCircles_Ga_Gp_NF_Stability pages)

BJT Stability vs. Bias BJT_Stab_vs_bias.dds

FET I-V Curves, Class A Power, Eff., Load,Gm vs. Bias

FET_IV_Gm_PowerCalcs.dds, (ClassA_calcs;IV and Gm vs. Bias pages)

FET Output Power, Distortion vs. Load R FET_dynamic_LL.dds

FET Fmax vs. Bias FET_fmax_vs_bias.dds

FET Ft vs. Bias FET_ft_vs_bias.ddsFET Noise Fig., S-Params, Gain, Stability, andCircles vs. Bias

FET_SP_NF_Match_Circ.dds, (NF, SP, Gains, at allBias Pts.; Matching at 1 Bias Point; andCircles_Ga_Gp_NF_Stability pages)

FET Stability vs. Bias FET_Stab_vs_bias

Table 2-2. S-Para meter Simu lations


S-Params., Noise Fig., Gain, Stability, Circles,and Group Delay

SP_NF_GainMatchK.dds, (NF, Gain, Stab. Fact.,Matching; Gain, Noise, and Stability Circles; SParameters, Group Delay pages)

Feedback Network Optimization to AttainStability

Gain_and_Stab_opt.dds

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25/200List of Available Data Displays 2-3

Table 2-3 shows all dat a displays u sed for 1-Tone Nonlinea r Simulat ions.

S-Params, Gain, NF, Stability, Group Delay vs.Swept Parameters

SP_NF_GainMatchKsweep.dds (Matching for Gainor NF; Stability Factors and Minimum NF, S Paramsand MAG at 1 Freq.; Group Delay pages)

S-Params., Stability, and Group Delay vs.Frequency and Input Power

Stab_vs_freq_pwr.dds (Stability and S-ParameterPlots; Group Delay pages)

Table 2-3. 1-Tone Nonlinear Simulat ions


Spectrum, Gain, Harmonic Distortion HB1Tone.dds

Spectrum, Gain, Harmonic Distortion (w/PAE) HB1TonePAE.dds

Spectrum, Gain, Harmonic Distortion vs.Power

HB1TonePswp.dds, (Spectrum, Gain Comp.,Harmonics; AM-to-AM, AM-to-PM Plots pages

Spectrum, Gain, Harmonic Distortion vs.Power (w/PAE)

HB1TonePAE_Pswp.dds, (Spectrum, Gain Comp.,PAE, Harmonics; AM-to-AM, AM-to-PM Plots pages

Spectrum, Gain, Harmonic Distortion vs.Frequency

HB1ToneFswp.dds

Spectrum, Gain, Harmonic Distortion vs.

Frequency (w/PAE)

HB1TonePAE_Fswp.dds

Spectrum, Gain, Harmonic Distortion vs.Frequency & Power

HB1ToneFPswp.dds, (Spectrum, Gain, Harmonics;AM-to-AM, AM-to-PM Plots pages)

Spectrum, Gain, Harmonic Distortion vs.Frequency & Power (w/PAE)

HB1TonePAE_FPswp.dds, (Spectrum, Gain, PAE,Harmonics; AM-to-AM, AM-to-PM Plots pages

Spectrum, Gain, Harmonic Distortion atX dB Gain Compression

HB1ToneGComp.dds

Spectrum, Gain, Harmonic Distortion at X dBGain Compression vs. Freq.

HB1ToneGCompFswp.dds

Spectrum, Gain, Harmonic Distortion at X dBGain Compression (w/PAE) vs. 1 Param.

HB1ToneGComp1swp.dds

Spectrum, Gain, Harmonic Distortion at X dBGain Compression (w/PAE) vs. 2 Params.

HB1ToneGComp2swp.dds

Noise Figure, Spectrum, Gain, HarmonicDistortion

HB1ToneNoise.dds

Large-Signal Load Impedance Mapping LoadMapper.dds

Table 2-2. S-Para meter Simu lations (cont inued)


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Introduction

Table 2-4 shows all dat a displays u sed for 2-Tone Nonlinea r Simulat ions.

Load-Pull - PAE, Output Power Contours HB1Tone_LoadPull.dds

Load-Pull - PAE, Output Power Contours at X

dB Gain Compression

HB1Tone_LoadPull_GComp.dds

Source-Pull - PAE, Output Power Contours HB1Tone_SourcePull.dds

Harmonic Impedance Opt. - PAE, OutputPower, Gain

HarmZopt1tone.dds, (Power, Gain, Spectrum; OptSource and Load Zs; and Waveforms pages)

Harmonic Gamma Opt. - PAE, Output Power,Gain

HarmGammaOpt1tone.dds, (Power, Gain,Spectrum; Opt Source and Load Zs; and Waveformspages

Table 2-4. 2-Tone Nonlinear Simulat ions


Spectrum, Gain, TOI and 5thOI Points HB2Tone.dds

Spectrum, Gain, TOI and 5thOI Points(w/PAE)

HB2TonePAE.dds

Spectrum, Gain, TOI and 5thOI Points vs.Power

HB2TonePswp.dds

Spectrum, Gain, TOI and 5thOI Points vs.Power (w/PAE)

HB2TonePAE_Pswp.dds

Spectrum, Gain, TOI and 5thOI Points vs.Frequency

HB2ToneFswp.dds

Spectrum, Gain, TOI and 5thOI Points vs.Frequency (w/PAE)

HB2TonePAE_Fswp.dds

Spectrum, Gain, TOI and 5thOI Points vs. 1Param. (w/PAE)

HB2TonePAE_1swp.dds

Spectrum, Gain, TOI and 5thOI Points vs. 2

Param. (w/PAE)

HB2TonePAE_2swp.dds

Load-Pull - PAE, Output Power, IMD Contours HB2Tone_LoadPull.dds

Source-Pull - PAE, Output Power, IMDContours

HB2Tone_SourcePull.dds

Harmonic Impedance Opt. - PAE, OutputPower, Gain, IMD

HarmZopt2tone.dds, (Power, Gain, Spectra; OptSource and Load Zs; and Waveforms pages)

Table 2-3. 1-Tone Nonlinea r Simu lations (cont inued)

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Ta ble 2-5 shows a ll da t a displa ys u sed in t h e Power Amplifier Examples - By Class of

Operation category. For reference information on these examples, refer to References

for Power Amplifier E xam ples on pa ge 2-10.

Harmonic Gamma Opt. - PAE, Output Power,Gain, IMD

HarmGammaOpt2tone.dds, (Power, Gain, Spectrum;Opt Source and Load Zs; and Waveforms pages)

Table 2-5. Power Amplifier Exam ples - By Clas s of Opera tion


Class AB > Load-Pull - PAE, Output PowerContours

HB1Tone_LoadPull_ClassAB.dds

Class AB > Spectrum, Gain, HarmonicDistortion, and PAE vs. Power

HB1TonePAE_Pswp_ClassAB.dds

Class AB > Spectrum, Gain, HarmonicDistortion, and PAE vs. 1 Swept Parameter

HB1TonePAE1swp_ClassAB.dds

Class AB > Spectrum, Gain, TOI and 5thOIPoints, and PAE vs. Power

HB2TonePAE_Pswp_ClassAB.dds

Class B > Load-Pull - PAE, Output PowerContours

HB1Tone_LoadPull_ClassB.dds

Class B > Spectrum, Gain, HarmonicDistortion, and PAE vs. Power HB1TonePAE_Pswp_ClassB.dds

Class B > Spectrum, Gain, HarmonicDistortion, and PAE vs. 1 Swept Parameter

HB1TonePAE1swp_ClassB.dds

Class B > Spectrum, Gain, TOI and 5thOIPoints, and PAE vs. Power

HB2TonePAE_Pswp_ClassB.dds

Class C > Load-Pull - PAE, Output PowerContours

HB1Tone_LoadPull_ClassC.dds

Class C > Spectrum, Gain, Harmonic

Distortion, and PAE vs. Power

HB1TonePAE_Pswp_ClassC.dds

Class C > Spectrum, Gain, HarmonicDistortion, and PAE vs. 1 Swept Parameter

HB1TonePAE1swp_ClassC.dds

Class D > Load-Pull - PAE, Output PowerContours

HB1Tone_LoadPull_ClassD.dds

Class D > Spectrum, Gain, HarmonicDistortion, and PAE vs. Power

HB1TonePAE_Pswp_ClassD.dds

Table 2-4. 2-Tone Nonlinea r Simu lations (cont inued)

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Introduction

Table 2-6 shows all dat a d isplays used in the Amplifier Sta t istical Design category.

Class D > Spectrum, Gain, HarmonicDistortion, and PAE vs. 1 Swept Parameter

HB1TonePAE1swp_ClassD.dds

Class E > Load-Pull - PAE, Output PowerContours HB1Tone_LoadPull_ClassE.dds

Class E > Spectrum, Gain, HarmonicDistortion, and PAE vs. Power

HB1TonePAE_Pswp_ClassE.dds

Class E > Spectrum, Gain, HarmonicDistortion, and PAE vs. 1 Swept Parameter

HB1TonePAE1swp_ClassE.dds

Class F > Load-Pull - PAE, Output PowerContours

HB1Tone_LoadPull_ClassF.dds

Class F > Spectrum, Gain, Harmonic

Distortion, and PAE vs. Power

HB1TonePAE_Pswp_ClassF.dds

Class F > Spectrum, Gain, HarmonicDistortion, and PAE vs. 1 Swept Parameter

HB1TonePAE1swp_ClassF.dds

Doherty> Load-Pull - PAE, Output PowerContours

HB1Tone_LoadPull_Doherty.dds

Doherty > Spectrum, Gain, HarmonicDistortion, and PAE vs. Power

HB1TonePAE_Pswp_Doherty.dds

Doherty > Spectrum, Gain, HarmonicDistortion, and PAE vs. 1 Swept Parameter

HB1TonePAE1swp_Doherty.dds

Doherty > Spectrum, Gain, TOI and 5thOIPoints, and PAE vs. Power

HB2TonePAE_Pswp_Doherty.dds

Class S > Spectrum, Output Power, Distortion,PAE

ClassS_PA_1.dds

Table 2-5. Power Amplifier E xamples - By Class of Operat ion (cont inued)


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Table 2-6. Amplifier Sta tist ical Design


S-Parameter Simulation Yield Sensitivity Histogram - One(YSH_SParams_One.dds)

Yield Sensitivity Histograms - Four(YSH_SParams_Four.dds)

Measurement Histogram - One(MH_SParams_One.dds)

Measurement Histograms - Four(MH_SParams_Four.dds)

Statistical Response Plots (SRP_SParams.dds)

Group Delay, Noise Figure Simulation Yield Sensitivity Histogram - One

(YSH_GrpDly_NF_One.dds)Yield Sensitivity Histograms - Four(YSH_GrpDly_NF_Four.dds)

Measurement Histogram - One(MH_GrpDly_NF_One.dds)

Measurement Histograms - Four(MH_GrpDly_NF_Four.dds)

Statistical Response Plots (SRP_GrpDly_NF.dds)

S-Parameters, Group Delay, Noise Figure

Simulation

Yield Sensitivity Histogram - One

(YSH_Sparams_GrpDly_One.dds)

Yield Sensitivity Histograms - Four(YSH_Sparams_GrpDly_Two.dds)

Gain, Spectrum, Harmonic Dist. Simulation Yield Sensitivity Histogram(YSH_1Tone_HD_Spect.dds)

Measurement Histogram(MH_1Tone_HD_Spect.dds)

Statistical Response Plots(SRP_1Tone_HD_Spect.dds)

Third- and Fifth-Order Intercept Simulation Yield Sensitivity Histogram(YSH_2Tone_TOI_5OI.dds)

Measurement Histogram (MH_2Tone_TOI_5OI.dds)

Statistical Response Plot(SRP_2Tone_TOI_5OI.dds)
http://-/?-http://-/?-http://-/?-http://-/?-

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Introduction

Table 2-7 shows all dat a d isplays used for Lu mped 2-Elemen t Z-Y Mat chin g

Networks.

Table 2-8 shows all dat a d isplays used for Lu mped Mu lti-E lement Z-Y Mat chin g

Networks.

Table 2-7. Lumped 2-Elemen t Z-Y Mat ching N etworks

Simulation Data DisplaysRload, Shunt C/L, Series C/L for Desired Z Zdesired1.dds

Rload, Series C/L, Shunt C/L for Desired Z Zdesired2.dds

Rload, Shunt C/L, Series C/L for Desired Y Ydesired1.dds

Rload, Series C/L, Shunt C/L for Desired Y Ydesired2.dds

Rload, Shunt C/L, Series C/L to Match Series R-Cor R-L Device

Zmatch1.dds

Rload, Series C/L, Shunt C/L to Match Series R-C

or R-L Device

Zmatch2.dds

Rload, Shunt C/L, Series C/L to Match Shunt R-Cor R-L Device

Ymatch1.dds

Rload, Series C/L, Shunt C/L to Match Shunt R-Cor R-L Device

Ymatch2.dds

Table 2-8. Lumped Mu lti-Elemen t Z-Y Mat ching Net works

Simulation Data Display

Rload, Series C/L, Shunt C/L, Series L/C forDesired Z

Zdesired1M.dds

Rload, Shunt C, Series L, Series C for Desired Z Zdesired2M.dds

Rload, Series L, Shunt C, Series L/C for DesiredZ

Zdesired3M.dds

Rload, Shunt C, Series L, Shunt C for Desired Y Ydesired1M.dds

Rload, Shunt C, Series L, Series C, Shunt L/C forDesired Y

Ydesired2M.dds

Rload, Series C/L, Shunt C/L, Series L/C toMatch Series R-C or R-L Device

Zmatch1M.dds

Rload, Shunt C, Series L/C, Series C to MatchSeries R-C or R-L Device

Zmatch2M.dds

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Rload, Series L, Shunt C, Series L/C to MatchSeries R-C or R-L Device

Zmatch3M.dds

Rload, Shunt C, Series L, Shunt C Shunt R-C orR-L Device

Ymatch1M.dds

Rload, Shunt C, Series L, Series C, Shunt L/C toMatch Shunt R-C or R-L Device

Ymatch2M.dds

Table 2-8. Lum ped Multi-Element Z-Y Mat ching Networks (cont inued)

Simulation Data Display

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32/2002-10 References for Power Amplifier Examples

Introduction

References for Power Amplifier Examples

Class AB

[1]Cripps S.C., RF Power Amplifiers for Wireless Communications, 1999 Artech

House, ISBN # 0-89006-989-1.(pa ges 120-125)

[2] Kenin gton P.B., High-Linear ity RF Amplfier Design, 2000 Art ech House,

ISBN # 1-58053-143-1. (pa ges 101-102)

Class B


House, ISBN # 0-89006-989-1. (pa ges 93-112)


ISBN # 1-58053-143-1. (pa ges 97-101)

Class C


House, ISBN # 0-89006-989-1.(pa ge 124)


ISBN # 1-58053-143-1. (pa ges 102-112)

Class D

[1]Cripps S.C., RF Power Amplifiers for Wireless Communications, 1999 ArtechHouse, ISBN # 0-89006-989-1.(pa ges 130-132)


ISBN # 1-58053-143-1. (pa ges 113-121)

Class E


House, ISBN # 0-89006-989-1.(pa ges 170-177)

[2] Kenin gton P.B., High-Linear ity RF Amplfier Design, 2000 Art ech House,ISBN # 1-58053-143-1. (pa ges 121-122)

Class F


House, ISBN # 0-89006-989-1.(pa ges 132-140)

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33/200References for Power Amplifier Examples 2-11


ISBN # 1-58053-143-1. (pa ges 122-123)

Class S


House, ISBN # 0-89006-989-1.(pa ges 246-248)


ISBN # 1-58053-143-1. (pa ges 124-126)

[3] 3. Kahn L.R., Single Sideband Tra nsm ission by En velope E limina tion an d

Rest ora t ion, Pr oc. IRE, Vol. 40, Ju ly 1952, pp. 803-806.

Doh ert y

[1]1. Cripps S.C., RF Power Amplifiers for Wireless Communications, 1999

Artech House, ISBN # 0-89006-989-1.(pa ges 225-239)

[2] 2. Kenin gton P.B., High-Linear ity RF Amplfier Design, 2000 Artech House,

ISBN # 1-58053-143-1. (pa ges 493-499)

General

[1]1. Sokal N.O. RF Power Amplifiers, Classes A through S, Proc. Wireless and

Microwave Technology 1997 Chanatilly, VA.

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Introduction

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Chapter 3: DC and Bias Point SimulationsThe tem plates in t he DC and Bias Point Simulat ions m enu ar e concerned with

choosing a bias point , an d its effects on out pu t power, gain, noise figur e,

tr an scondu cta nce, etc.

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DC and Bias Point Simulations > BJT I-V Curves, Class A Power, Eff.,Load, Gm vs. Bias

Description

This simu lation setu p genera tes t he I-V cur ves of a BJ T. Var ious dat a dependent on

th e I-V cur ves, such a s t ra nsconducta nce, class A out pu t power, and efficiency a realso shown. Both th e base cur ren t an d t he collector-to-emitt er voltage a re swept.

Needed to Use Schematic

Nonlinea r BJ T model

Main Schematic Settings

Sweep ra nges for ba se cur ren t a nd collector volta ge

Data Display Outputs

BJ T_IV_Gm_PowerCalcs.dds, Clas sA_calcs pa ge:

Device I-V curves

Load line set by placing a m ar ker on th e I-V curves at t he knee, an d by a

user-specifiable m aximum VCE.

Maximum allowed DC power dissipation curve, with ma ximu m dissipat ion set

by user.

Given t he load line specified by th e knee of th e I-V cur ves an d th e maximumVCE:

Optimu m collector voltage a nd collector curr ent , for ma ximu m power

delivered t o the load while in Class A operat ion

Corr esponding load resistance

Corr esponding ma ximu m out put power

Corr esponding DC power consu mpt ion

Corr esponding DC-to-RF efficiency

Given a different bias point, specified by a different ma rker:

Load line between tha t ma rker a nd th e mark er at t he knee of th e I-V cur ve

Resista nce of th is load line

DC power consu mption a t t his bias point

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Outpu t power, assuming the device remains in Class A opera t ion (AC voltage

does not exceed user-specified VCE, an d does not en ter th e knee region)

DC-to-RF efficiency at th is bias point

Device beta versus ba se cur rent at th e VCE specified by one of th e mar kers

Note The est ima te of DC-to-RF efficiency an d out pu t power a re only

ap proximat e, since no high-frequ ency effects ar e modeled in this sim ula t ion.

BJ T_IV_Gm_PowerCalcs.dds, IV and Gm vs. Bias pa ge:

Device I-V cur ves

DC tra nsconductan ce (Gm) versu s VCE

DC tra nsconductan ce (Gm) versu s IBB and VCE

DC tra nscondu cta nce (Gm) versus collector cur ren t

Collector current versu s base cur rent at one VCE

Table of tr an sconductan ce values

Schematic Name

BJT_IV_Gm_PowerCalcs

Data display name

BJT_IV_Gm_PowerCalcs.dds

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DC and Bias Point Simulations > BJT Output Power, Distortion vs. LoadR

Description

This simulat ion set up genera tes t he I-V cur ves of a BJ T an d simula tes t he power

delivered to a load resistor a s a fun ction of the r esistan ce value, at one bias point.




Sweep ra nges for ba se cur ren t, collector volta ge and load resist ance; bias point an d

frequen cy for out put power versu s load resista nce simulat ion


Device I-V curves

Load lines for each of th e load r esista nces

Power delivered to the load a s a fun ction of load r esista nce

Output power a nd ha rmonic distortion at each load r esistan ce

Schematic Name

BJT_dynamic_LL

Data Display Name

BJT_dynamic_LL.dds

Note

The load power simu lations will show less th an optima l results a s th e simulat ion

frequ ency is increa sed, because only a res istive load is presen ted to th e device. Also,

no impeda nce ma tching is included at th e inpu t.

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DC and Bias Point Simulations > BJT Fmax vs. Bias

Description

This simu lates th e ma ximu m frequen cy of oscillation (th e frequen cy at which th e

maximum ava ilable ga in drops to 0 dB), ver sus bias cur ren t , for a part icu la r va lue o

VCE. It should help you det erm ine how high in frequen cy a device can be used.




VCE, base curr ent sweep limits, and frequency ra nge for S-para met er simu lation


The maximum available gain versus base current and frequency

dB(S21) versus base current and frequency

The ma ximu m frequency of oscillation, which is dependent on a ma rker th at

you move to select th e valu e of collector cur ren t

Schematic Name

BJ T_fma x_vs_bias

Data Display Name

BJ T_fma x_vs_bias.dds

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DC and Bias Point Simulations > BJT Ft vs. Bias

Description

This simu lates a devices ft, th e frequen cy at which th e sh ort -circuit cur ren t gain

drops to un ity, versus bias cur ren t, for a pa rt icula r va lue of VCE. It should help you

determ ine how high in frequency a device can be used.






Short circuit current gain versus base current and frequency

F r equ en cy a t wh ich t h e sh or t -cir cu it cu r ren t ga in dr ops t o 0 dB, a t t h e collect or

bias cur ren t specified by a movable ma rk er

Schematic Name

BJ T_ft

Data Display Name

BJT_ft.dds

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DC and Bias Point Simulations > BJT Noise Fig., S-Params, Gain,Stability, and Circles vs. Bias

Description

This simulat es th e S-par am eters a nd n oise par am eters of a device, versus bias

voltage and current, at a single frequency. You specify the collector voltage sweepra nge an d th e base cur ren t sweep ra nge, an d th e single frequen cy for S-para met er

an d n oise ana lysis. The optimal source and load impedan ces for m inimum noise

figur e an d for ma ximu m gain a re compu ted, as well as t he a vailable gain circles,

power gain circles, noise circles, and sour ce a nd load st ability circles.



Main Schematic SettingsSweep ra nges for base cur ren t an d collector voltage a nd frequen cy for S-par am eter

analysis.


BJ T_SP_NF _Mat ch_Circ.dds, NF, SP, Gains a t all Bias Pt s. page:

Minimum noise figure versus VCE and base current

dB(S21), dB(S12), dB(S11), and dB(S22) versu s collector volta ge and base

current

Maximum available gain versus base curr ent a nd collector voltage

Associated power gain (with input m at ched for m inimum noise figur e and

out put conjugat ely mat ched) versu s collector voltage a nd base cur ren t

BJ T_SP_NF _Mat ch_Circ.dds, Mat chin g at 1 Bias Point page:

Minimum n oise figure an d dB(S21) versus collector cur ren t a t a collector

volta ge selected by moving a ma rk er on t he I -V cur ves.

DC I-V curves

Smith cha rt with t ra ces of th e optima l sour ce reflection coefficients for

minimum noise figure, and the following reflect ion coefficients (gammas) a t the

selected bia s point :

Gamma source for minimum noise figure

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Gamma load for ma ximum power gain when input is terminat ed for

minimu m noise figur e

Gamm a sour ce for simultan eous conjugate mat ch (with out regard to noise)

Gamm a load for simultan eous conjugate mat ch (with out r egar d to noise)

Listing column s of dat a corr esponding to the bias point selected by moving a

ma rk er on th e I-V cur ves:

VCE

IC

Approximat e DC power consumption

S-pa r am et er s, dB

Maximum available power gain, dB Minimum noise figure, dB

Sopt for minimum n oise figur e in polar coordinat es and in magnitude and

phase

Zopt for minimum n oise figure

Associated power gain in dB, if th e input is ma tched for m inimu m n oise

figur e an d th en t he output is mat ched for ma ximum power gain

Corr esponding load impedance for a ssociated power gain

Sour ce an d load impedances for simulta neous conjugate ma tching (with out

regar d t o noise)

Input an d output impedances when source and load are terminated in 50

ohms

Stability factor, K

Frequency of the S-param eter simulations

BJ T_SP_NF_Match_Circ.dds, Circles_Ga_Gp_NF _St ability pa ge:

All at one bias p oint selected by moving a ma rk er on th e devices I-V cur ves:

Sta bility factor, K, and sour ce stability circles. Note t ha t t he Smith Char t

size is fixed, so if th e sta bility circles ar e far out side th e Smith Cha rt , th ey

will not be displayed. If you cha nge the Sm ith Cha rt scaling to Aut o Scale,

the circles will be visible.

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Available gain a nd n oise circles on one Smith Cha rt , an d power gain circles

on a different Smith Char t.

Minimum noise figure, source impedance (Zopt) required to achieve th is noise

figur e, an d th e optima l load impeda nce for power t ra nsfer when th e sour ce

impeda nce is Zopt

Maximum available gain, and t he sour ce and load impedances required for

simu lta neous conjugat e ma tching (only valid if K>1)

Noise figure with t he simultaneous conjugate mat ch condition

Noise figure, tran sducer power gain, and optimal load impedance if th e

sour ce impedan ce is chosen a rbitr ar ily by moving a m ar ker (Gam ma S) on a

Smith Cha rt . This is useful if you mu st ma ke some compr omise between

noise and gain, or if you n eed to avoid an un st able region.

Tran sducer power gain, an d optimal sour ce impedance an d corr esponding

noise figure, if th e load impedan ce is chosen a rbitr ar ily by moving a ma rk er

(Gam ma L) on a Smith Cha rt . This is useful if you n eed to avoid an un sta ble

region.

Schematic Name

BJT_SP_NF_Match_Circ

Data Display Name

BJT_SP_NF_Match_Circ.dds

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DC and Bias Point Simulations > BJT Stability vs. Bias

Description

Th is sim u la t es t h e S-pa r am et er s of a t r an sis tor, wit h t h e ba se cu r ren t swept a n d t h e

emitt er bias voltage const an t, t o determ ine th e sta bility factors as a fun ction of base

cur ren t. It should help you det erm ine th e dependence of th e sta bility factor on th ebias point .






Stability measure, B1, versus base current and frequency

Sta bility factor, K, versus base cur rent an d frequency

Geomet rically-derived load st ability factor, mu , versus base cur ren t a nd

frequency

Geomet rically-derived sour ce sta bility factor, mu_prime, versus ba se cur ren t

an d frequen cy

Schematic NameBJT_Stab_vs_bias

Data Display Name

BJT_Stab_vs_bias.dds

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DC and Bias Point Simulations > FET I-V Curves, Class A Power, Eff.,Load, Gm vs. Bias

Description

This simu lation setu p genera tes t he I-V cur ves of a FE T. Var ious dat a dependent on

th e I-V cur ves, such a s t ra nsconducta nce, class A out pu t power, and efficiency a realso shown. Both th e gat e an d dra in voltages ar e swept.


Nonlinea r F ET model


Sweep ran ges for gat e an d dra in voltages


FET_IV_Gm_PowerCalcs.dds, ClassA_calcs pa ge:

Device I-V curves

Load line set by placing a m ar ker on th e I-V curves at t he knee, an d by a

user-specifiable maximum VDS

Maximum allowed DC power dissipation curve, with ma ximu m dissipat ion set

by user.

Given t he load line specified by th e knee of th e I-V cur ves an d th e maximumVDS:

Optimum drain voltage and dra in curr ent, for m aximum power delivered to

th e load while in Class A opera tion

Corresponding load resistance

Corresponding maximum output power

Corresponding DC power consumption

Corr esponding DC-to-RF efficiency

Given a different bias point, specified by a different ma rker:

Load line between th at m arker an d the marker at the knee of the I-V curve

Resistance of this load line

DC power consumption at t his bias point

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Outpu t power, assuming the device remains in Class A opera t ion (AC voltage

does not exceed user-specified VDS, an d does not ent er t he k nee r egion)

DC-to-RF efficiency at th is bias point

Note The est ima tes of DC-to-RF efficiency and out pu t power a re onlyap proximat e, since no high-frequ ency effects ar e modeled in this sim ula t ion.

FET_IV_Gm_PowerCalcs.dds, IV, Gm vs. Bias page:

Device I-V curves

DC transconductan ce (Gm) versus VDS

DC tr an sconductan ce (Gm) versu s VGS and VDS

DC tra nsconductan ce (Gm) versus drain curr ent

Drain curr ent versus gate voltage at one VDS

Table of transconductan ce values

Schematic Name

FET_IV_Gm_PowerCalcs

Data Display Name

FET_IV_Gm_PowerCalcs.dds

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DC and Bias Point Simulations > FET Output Power, Distortion vs. LoadR

Description

This simulat ion set up genera tes t he I-V cur ves of a F ET a nd simu lates t he power

delivered to a load resistor a s a fun ction of the r esistan ce value, at one bias point.




Sweep ra nges for gate voltage, drain voltage a nd load resista nce; bias point an d

frequen cy for out put power versu s load resista nce simulat ion


Device I-V curves

Load lines for each of th e load r esista nces

Power delivered to the load a s a fun ction of load r esista nce

Output power a nd ha rmonic distortion at each load r esistan ce

Schematic Name

FET_dynamic_LL

Data Display Name

FET_dynamic_LL.dds

Note

The load power simu lations a re going to show less th an optima l results a s th e

simula tion frequen cy is increa sed, becau se only a resistive load is present ed t o the

device. Also, no impeda nce matchin g is included at the input .

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DC and Bias Point Simulations > FET Fmax vs. Bias

Description

This simu lates th e ma ximu m frequen cy of oscillation (th e frequen cy at which th e

maximum ava ilable ga in drops to 0 dB), ver sus bias volt age, for a par t icu la r va lue o

VDS. It should help you det erm ine how high in frequ ency a device can be used.




VDS, gate voltage sweep limits, an d frequency ran ge for S-par am eter simula tion


The maximu m available gain versus gat e voltage an d frequency

dB(S21) versus gat e voltage and frequency

The ma ximu m frequency of oscillation, which is dependent on a ma rker th at

you m ove to select t he va lue of drain cur ren t

Schematic Name

FET_fmax_vs_bias

Data Display Name

FET_fmax_vs_bias.dds

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DC and Bias Point Simulations > FET Ft vs. Bias

Description

This simu lates a devices ft, th e frequen cy at which th e sh ort -circuit cur ren t gain

drops t o un ity, versus gat e volta ge, for a pa rt icula r value of VDS. It sh ould h elp you

determ ine how high in frequency a device can be used.


Nonlinea r F ET m odel.




Short circuit cur rent gain versu s gat e voltage an d frequency

Frequency at which th e short -circuit cur rent gain drops to 0 dB, at th e drain

bias cur ren t specified by a movable ma rk er

Schematic Name

FET_ft_vs_bias

Data Display Name

FET_ft_vs_bias.dds

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DC and Bias Point Simulations > FET Noise Fig., S-Params, Gain,Stability, and Circles vs. Bias

Description

This simulat es th e S-par am eters a nd n oise par am eters of a device, versus bias

volta ges, a t a single frequ ency. You specify th e gat e and dra in volta ge sweep ra nges,and the s ingle fr equency for S-parameter and noise ana lys is. The op timal source and

load imp edan ces for m inimum noise figur e an d for m aximum gain a re compu ted, as

well as the avai lable gain circles, power gain circles, noise circles, and source and load

stability circles.



Main Schematic SettingsSweep ran ges for gat e an d dra in voltages an d frequen cy for S-para met er a na lysis


FE T_SP_NF _Mat ch_Circ.dds, NF, SP, Gains a t a ll Bias Pt s. pa ge:

Minimum noise figure versus VGS and VDS

dB(S21), dB(S12), dB(S11), and dB(S22) versu s VGS an d VDS

Maximum available gain versus VGS and VDS

Associated power gain (with input m at ched for m inimum noise figur e and

out put conjugat ely ma tched) versus VGS an d VDS

FE T_SP_NF _Mat ch_Circ.dds, Mat chin g at 1 Bias Point pa ge:

Minimum n oise figure an d dB(S21) versu s drain cur rent a t a dra in voltage

selected by moving a m ar ker on t he I-V cur ves.

DC I-V curves

Smith cha rt with t ra ces of th e optima l sour ce reflection coefficients forminimum noise figure, and the following reflect ion coefficients (gammas) a t the

selected bia s point :




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Listing column s of dat a corr esponding to the bias point selected by moving a

ma rk er on th e I-V cur ve:

VDS

IDS

Approximat e DC power consumption


Maximum available power gain, dB

Minimum noise figure, dB

Sopt for minimum n oise figur e in polar coordinat es and in magnitude andphase






regar d t o noise)

Input an d output impedances when source and load are terminated in 50

ohms

Stability factor, K

Frequency of the S-param eter simulations

FET_SP_NF_Match_Circ.dds, Circles_Ga_Gp_NF_Stability page:

All at one bias p oint selected by moving a ma rk er on th e devices I-V cur ves:

Sta bility factor, K, and sour ce stability circles. Note t ha t t he Smith Char t

size is fixed, so if th e sta bility circles ar e far out side th e Smith Cha rt , th ey

will not be displayed. If you cha nge the Sm ith Cha rt scaling to Aut o Scale,

the circles will be visible.

Available gain a nd n oise circles on one Smith Cha rt , an d power gain circles

on a different Smith Char t.

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Minimum noise figure, source impedance (Zopt) required to achieve th is noise

figur e, an d th e optima l load impeda nce for power t ra nsfer when th e sour ce

impeda nce is Zopt


simu lta neous conjugat e ma tching (only valid if K>1)

Noise figure with t he simultaneous conjugate mat ch condition

Noise figure, tran sducer power gain, and optimal load impedance if th e

sour ce impedan ce is chosen a rbitr ar ily by moving a m ar ker (Gam ma S) on a

Smith Cha rt . This is useful if you mu st ma ke some compr omise between

noise and gain, or if you n eed to avoid an un st able region.

Tran sducer power gain, an d optimal sour ce impedance an d corr esponding

noise figure, if th e load impedan ce is chosen a rbitr ar ily by moving a ma rk er

(Gam ma L) on a Smith Cha rt . This is useful if you n eed to avoid an un sta bleregion.

Schematic Name

FET_SP_NF_Match_Circ

Data Display Name

FET_SP_NF_Match_Circ.dds

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DC and Bias Point Simulations > FET Stability vs. Bias

Description

This simulat es th e S-para meters of a tr an sistor, with th e gate voltage swept a nd t he

dra in bias voltage const an t, to determ ine th e sta bility factors as a fun ction of gate

voltage. It sh ould h elp you determ ine th e dependen ce of the st ability factor on t hebias point .






Sta bility measur e, B1, versu s gate voltage and frequency

Sta bility factor, K, versus gate voltage and frequency

Geomet rically-derived load st ability factor, mu, versu s gate voltage an d

frequency

Geomet rically-derived source stability factor, mu_prime, versu s gat e voltage

an d frequen cy

Schematic NameFET_Stab_vs_bias

Data Display Name

FET_Stab_vs_bias.dds

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Chapter 4: S-Parameter SimulationsThe templat es in t he S-Par am eter Simulat ions ar e for simulating th e sma ll-signa l

cha ra cter istics, such as noise figure, available ga in, st ability, group delay, etc., of a

device or a n a mplifier. Except for t he las t one, th ese simu lat ions do not requ ire a

nonlinea r m odel, but an am plifier with nonlinea r m odels can be used.

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S-Parameter Simulations > S-Params., Noise Fig., Gain, Stability, Circlesand Group Delay

Description

This simu lates th e S-par am eters, noise figure, sta bility, an d group delay of an y

two-por t network , ver sus fr equency. You may use it with an S-parameter data file, orwith a nonlinea r a mplifier m odel.


Any linea r or n onlinear model, including mea sur ed S-par am eters


Fr equency sweep ran ge


SP_NF _Gain Mat chK.dds, NF, Gain , Sta b. Fact., Mat chin g pa ge:

Minimum n oise figure an d noise figur e with 50 ohm t erminat ions versus

frequency

dB(S21), maximu m available gain, and a ssociated gain (when t he input is

ma tched for NF min a nd t he out put is then conjugat ely ma tched), versu s

frequency

Sta bility factor, K, and geomet ric sta bility factors, mu _sour ce an d mu _load

versus frequen cy


min imu m n oise figure, sour ce an d load st ability circles, and the following

reflection coefficient s (gam ma s) a t a frequ ency selected by moving a m ar ker :






Listing column s of dat a corr esponding to the frequen cy point selected by

moving a m ar ker:


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phase






regar d t o noise)

Stability factor, K

SP_NF _Gain Mat chK.dds, Gain , Noise, an d St ability Circles page:

All at one frequen cy selected by moving a m ar ker :

Sta bility factor, K, an d sour ce and load st ability circles. Note t ha t t he Smith

char t s ize is fixed , so if the s tability cir cles a re fa r ou t side the Smith char t , they

will not be displayed. If you cha nge th e Smit h cha rt scaling to Aut o Scale, th e

circles will be visible.

Available gain a nd n oise circles

Minimum noise figur e, sour ce impedan ce (Zopt) required to achieve th is noise

figur e, an d th e optima l load impeda nce for power t ra nsfer when t he source

impedan ce is Zopt, as well as t he t ra nsdu cer power gain with t hese source an d

load impedances


simu lta neous conjuga te m at chin g (only valid if K>1), and th e corr esponding

noise figure

Noise figure, tr an sducer power gain, an d optimal load impedance if th e sour ceimpedan ce is chosen ar bitra rily by moving a ma rk er (Gam ma S) on a Smith

cha rt . This is useful if you mu st ma ke some compr omise between n oise an d

gain, or if you n eed to avoid an un st able r egion.

Power gain circles, on a different Sm ith cha rt

Tran sducer power gain, optimal source impedance, and corresponding noise

figur e, if the load impedan ce is chosen a rbitr ar ily by moving a ma rk er

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(Gam ma L) on a Smith cha rt . This is useful if you n eed to avoid an un sta ble

region.

SP_NF_GainMatchK.dds, S Parameters, Group Delay page:

S11 and S22 on Sm ith cha rt s, also with a circle of const an t VSWR

S21 an d S12 (linear u nits) on polar plots

dB(S21) an d dB(S12) on a recta ngular plot

Group Delay in seconds, versus frequen cy.

Note This plot m ay be jagged if mea sur ed S-par am eter da ta is simu lated, an d

th e num ber of mea sur ed points is sma ll.

Schematic Name

SP_NF_GainMatchK

Data Display Name

SP_NF_GainMatchK.dds

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S-Parameter Simulations > Feedback Network Optimization to AttainStability

Description

This schema tic optimizes component values in input , out put , an d feedback

sta bilizat ion net work s, to sta bilize a 2-port net work, m inimize th e minimu m n oisefigure, an d m aximize gain (dB(S21).) You ma y delete componen ts or modify th e

str uctur e of th e sta bilizat ion n etwork s.




Type of optimization algorithm (gradient, ran dom, genetic, etc.), goal weighting, goa

values, an d frequ ency ran ges over which noise figur e an d gain goa ls will beevaluated.


Geomet rically-derived sour ce and load st ability factors

Gain , dB(S21)

Minimum noise figure

Values of optimized component s

Schematic Name

Gain_and_Stab_opt

Data display name

Gain_and_Stab_opt.dds

Note

The optimizat ion resu lts m ay vary su bsta nt ially, depending on t he t ype of

opt imizat ion algor ithm used (set on the Nominal Opt imizat ion cont roller ) and on thegoals. Noise figure and gain have been included as opt imizat ion goals. Otherwise, the

optimizer might fin d a sta ble net work, but with poor per form an ce as a n a mplifier.

The feedback network topology might be modified, but the data display will a lso have

to be adjust ed. For example, if you use a tr an smission line (inst ead of lum ped

elemen ts) to att ain sta bility an d optimize the length an d/or width of th e line, these

par am eters can be displayed on t he da ta display by insert ing new listing column s.

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S-Parameter Simulations > S-Params, Gain, NF, Stability, Group Delay vsSwept Parameters

Description

This schem at ic sweeps two par am eters in a circuit to determ ine how gain, noise

figur e, ma tching impeda nces, sta bility an d group delay depend on th e twoparameters. Often th is sor t of a s imula t ion provides designers with more ins ight than

an optimization. You mu st decide which two par am eters to sweep, an d you ma y

modify th e net work to be simu lated.




Network topology, two parameters to sweep and their sweep ranges, frequency rangefor S-para met er simu lation


SP_NF _Gain Mat chKsweep.dds, Mat chin g for Ga in or NF pa ge:

Minimum noise figure versus frequency


ma tched for NF min a nd t he out put is then conjugat ely ma tched), versu s

frequency


ma tched for NF min a nd t he out put is then conjugat ely ma tched), versu s each

swept para meter, with th e oth er pa ra meter held const an t, at one frequency

selected by a ma rk er

Stability factor versus frequency


min imu m n oise figure, an d the following reflection coefficient s (gam ma s) a t a

frequen cy selected by moving a ma rk er:





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Listing column s of dat a corr esponding to the frequen cy point selected by

moving a m ar ker:





phase






regar d t o noise)

Stability factor, K

SP_NF_GainMatchKsweep.dds, Stability Factors and Minimum NF page:

Sta bility factor, K, versus both swept pa ra meters a nd frequency

Sta bility factor, K, versus both swept par am eters, at one frequen cy selected bymoving a ma rker

Minimum n oise figure versus both swept par ameters an d frequency

Min imum noise figure ver sus both swept parameter s, a t one frequency selected

by moving a ma rk er

SP_NF_GainMa tchKsweep.dds, S Pa ra ms an d MAG a t 1 Fr eq. page:

S-parameters versus both parameters

Minimum noise figure versus both swept para meters

Maximum available gain versus both swept para meters

SP_NF _Gain Mat chKsweep.dds, Group Delay pa ge:

Group delay versus both swept parameters an d frequency

Group delay at one combination of th e swept pa ra meters, versus frequency

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S-Parameter Simulations > S-Params., Stability, and Group Delay vs.Frequency and Input Power

Description

This schematic simulates the large-signal S-parameters of a device, versus frequency

and input power. The stability factor, K, is computed from these S-parameters , us ingth e sta nda rd form ula foun d in t extbooks. This simu lation s etu p differs from t he

LSSP con t roller in tha t small-s igna l mixer mode is used to in ject a small s igna l a t the

out pu t of th e device, while th e inpu t is being driven by a lar ge signa l sour ce. This

gives a m uch m ore r ealistic simula tion of S12 an d S22.


Nonlinea r model, or an am plifier with nonlinea r device m odels

Main Schematic SettingsRan ges over which to sweep th e input signa l frequen cy an d power


Stab_vs_freq_pwr.dds, Stability an d S-Par amet er P lots pa ge:

S-Param eters versus input frequency and input power

Sta bility factor, K, versus input frequency and input power

St ab_vs_freq_pwr.dds, Group Dela y pa ge:

Group delay versu s frequen cy, with t he inpu t power selected by moving a

marker

Schematic Name

Stab_vs_freq_pwr

Data Display Name

Stab_vs_freq_pwr.dds

Note

The st ability factor is only compu ted at th e frequen cy of the inpu t signa l. The

sta bility factors at higher a nd lower frequencies ar e not compu ted.

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Chapter 5: 1-Tone Nonlinear Simulations

The templates in t he 1-Tone Nonlinear Simulat ions ar e for simu lating the

large-signa l cha ra cter istics of an am plifier or device, such as gain, ha rm onic

distortion, power-added efficiency, gain compression, etc. Setups for simulating these

versus frequen cy, power, and ar bitra ry swept p ar am eters ar e included. Load- an d

Source-pull simulat ions and impedance optimizat ion setups are also included. These

simulations do require nonlinear model(s).

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1-Tone Nonlinear Simulations

1-Tone Nonlinear Simulations > Spectrum, Gain, Harmonic Distortion

Description

This is the mos t bas ic s imula t ion setup, and it s imula tes the spect rum, ou tpu t power

power ga in, an d h ar monic dist ort ion of a device or a mplifier. A sa mple power

am plifier is provided. You m us t r eplace th is am plifier with your own device oram plifier, and m odify the biases, as n eeded.


A device or a n a mplifier u sing nonlinea r m odel(s)


Inpu t frequen cy an d a vailable source power


Output spectrum and voltage waveform

Ou t pu t p ower

Transducer power gain (power delivered to the load minus power available from

th e sour ce)

Har monic distortion up t o the 5th, in dBc

Schematic Name

HB1Tone

Data Display Name

HB1Tone.dds

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1-Tone Nonlinear Simulations > Spectrum, Gain, Harmonic Distortion(w/PAE)

Description

This simu lation setu p is identical t o th e HB1Tone schema tic, except t ha t it includes

two current probes and named voltage nodes for calculat ing power-added efficiency. Ialso simu lates t he spectru m, out put power, power gain, an d h ar monic distort ion of a

device or a mplifier. A sa mple power a mplifier is pr ovided. You mu st rep lace th is

am plifier with your own device or a mplifier, and you can modify th e biases, as

described in the notes, below.


A device or a n a mplifier u sing nonlinea r m odel(s)

Main schematic settingsInpu t frequency, available sour ce power, and bias set tin gs


Output spectrum and input an d output voltage waveforms

Ou t pu t p ower

Transducer power gain (power delivered to the load minus power available from

th e sour ce)

Har monic distortion up t o the 5th, in dBc

Power-added efficiency (Pout at fun dam ent al minu s Available sour ce

power)/(DC power consumption)

High supply cur rent

DC power consumption

Therma l power dissipat ion in th e device or a mplifier

Schematic NameHB1TonePAE

Data Display Name

HB1TonePAE.dds

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1-Tone Nonlinear Simulations

Note

Only bias su pplies on t he h ighes t level schem atic will be included in t he PAE

calculat ion. So, for exa mple, if you r eplace th e sample amplifier with one with t he

bias su pplies included in t he subcircuit, th ose su pplies will not be included in t he

PAE calculat ion. On t he h ighest level schem at ic, you can delete one of th e two

supplies an d/or r eplace th e voltage sour ces with cur ren t sour ces, an d t he PAE

calculat ion will still be valid. You can modify th e componen ts in t he bia s n etwork,

rea lizing th at th e DC power consu mpt ion is compu ted a s (th e DC voltage at th e

Vs_high n ode) * (th e DC cur ren t in th e Is_h igh cur ren t pr obe) + (th e

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