Switching Units

Types of switching elementsTelephone switchesswitch samplesDatagram routersswitch datagramsATM switchesswitch ATM cellsINPUTSOUTPUTS

*Look Inside a RouterTwo key router functions: run routing algorithms/protocol (RIP, OSPF, BGP)switching datagrams from incoming to outgoing ports

Repeaters, bridges, routers, and gatewaysRepeaters/Hubs: at physical level (L1)Bridges: at datalink level (L2)based on MAC addressesdiscover attached stations by listeningRouters: at network level (L3)participate in routing protocolsApplication level gateways: at application level (L7)treat entire network as a single hopGain functionality at the expense of forwarding speedfor best performance, push functionality as low as possible

Types of servicesPacket vs. circuit switchespackets have headers and samples dont Connectionless vs. connection orientedconnection oriented switches need a call setupsetup is handled in control plane by switch controllerconnectionless switches deal with self-contained datagrams

Connectionless (router)

Connection-oriented (switching system)

Packet switch

Internet router

ATM switching system

Circuit switch

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Telephone switching system

Other switching unit functionsParticipate in routing algorithmsto build routing tablesNext Lecture!Resolve contention for output trunksbuffer schedulingPrevious Lecture!Admission controlto guarantee resources to certain streams

RequirementsCapacity of switch is the maximum rate at which it can move information, assuming all data paths are simultaneously activePrimary goal: maximize capacitysubject to cost and reliability constraintsCircuit switch must reject call if cant find a path for samples from input to outputgoal: minimize call blockingPacket switch must reject a packet if it cant find a buffer to store it awaiting access to output trunkgoal: minimize packet lossSubgoal: Dont reorder packets

Internal switchingIn a circuit switch, path of a sample is determined at time of connection establishmentNo need for a sample header--position in frame is enoughIn a packet switch, packets carry a destination fieldNeed to look up destination port on-the-flyDatagramlookup based on entire destination addressCelllookup based on VCI used as an index to a table Other than that, switching units are very similar

Blocking in packet switchesCan have both internal and output blockingInternalno path to outputExample: head of line blocking.Outputoutput link busyIf packet is blocked, must either buffer or drop it

Dealing with blockingOverprovisioninginternal links much faster than inputsBuffersat input or outputBackpressureif switch fabric doesnt have buffers, prevent packet from entering until path is availableParallel switch fabricsincreases effective switching capacity

Three generations of packet switchesDifferent trade-offs between cost and performanceRepresent evolution in switching capacity, rather than in technologyWith same technology, a later generation switch achieves greater capacity, but at greater costAll three generations are represented in current products

First generation switchMost Ethernet switches and cheap packet routersBottleneck can be CPU, host-adaptor or I/O bus, dependingcomputerqueues in memoryCPUlinecard

Second generation switchPort mapping intelligence in line cardsBottleneck is the bus (or ring)

buscomputerfront end processorsor line cards

Third generation switchesThird generation switch provides parallel paths (fabric)

NxNpacketswitchfabricOLCOLCOLCINILCILCILCOUTcontrol

Third generation (contd.)Featuresself-routing fabricoutput buffer is a point of contentionunless we arbitrate access to fabricpotential for unlimited scaling, as long as we can resolve contention for output buffer

Switching - Fabric

Switching: abstract model Number of connections: from few (4 or 8) to huge (100K)

Multiplexors and demultiplexorsMultiplexor: aggregates sessions N input linesOutput runs N times as fast as inputDemultiplexor: distributes sessionsone input line and N outputs that run N times slowerCan cascade multiplexors

Time division switchingKey idea: when demultiplexing, position in frame determines output linkTime division switching interchanges sample position within a frame: Time slot interchange (TSI)

Time Slot Interchange (TSI) : examplesessions: (1,3) (2,1) (3,4) (4,2)3 1 4 21234Read and write to shared memory in different order12342413

TSI Simple to build.Multicast: easy (why?)Limit is the time taken to read and write to memoryFor 120,000 telephone circuitsEach circuit reads and writes memory once every 125 ms.Number of operations per second : 120,000 x 8000 x2 each operation takes around 0.5 ns => impossible with current technologyNeed to look to other techniques

Space division switchingEach sample takes a different path through the switch, depending on its destinationCrossbar: Simplest possible space-division switchCrosspoints can be turned on or off

Crossbar - examplesessions: (1,2) (2,4) (3,1) (4,3)inputsoutput

CrossbarAdvantages:simple to implementsimple controlstrict sense non-blockingMulticastSingle source multiple destination portsDrawbacksnumber of crosspoints, N2large VLSI spacevulnerable to single faults

Time-space switchingPrecede each input trunk in a crossbar with a TSIDelay samples so that they arrive at the right time for the space division switchs scheduleCrosspoint: 4 (not 16)memory speed : x2 (not x4)

Finding the scheduleBuild a routing graphnodes - input linkssession connects an input and output nodes.Feasible scheduleComputing a schedulecompute perfect matching.

Time-Space: ExampleInternal speed = double link speedTSI

Time-space-time (TST) switchingAllowed to TSI both on input and outputGives more flexibility => lowers call blocking probability

Internal Non-Blocking TypesRe-arrangeableCan route any permutation from inputs to outputs.Strict sense non-blockingGiven any current connections through the switch.Any unused input can be routed to any unused output.Wide sense non-blocking.There exists a specific routing algorithm, s.t.,for any sequence of connections and releases, Any unused input can be routed to any unused output,assuming all the sequence was served by the routing algorithm.

Circuit switching - Space divisiongraph representationtransmitter nodesreceiver nodesinternal nodesFeasible scheduleedge disjoint paths.cost functionnumber of crosspoints (complexity of AxB is AB)internal nodes

Crossbar - example12341234

Another Exampleinputsoutputs

Another Examplesessions: (1,3) (2,6) (3,1) (4,4) (5,2) (6,5)inputsoutputs

Clos NetworkClos(N, n , k) : N - inputs/outputs; cross-points: 2 (N/n)nk + k(N/n)2nxk(N/n)x(N/n)kxnN=6n=2k=23x33x32x22x22x2NkN/nN/n

Clos Network - strict sense non-blockingHolds for k 2n-1Proof Methodology:Recall: IF [A,B S and |A|+|B| > |S|] then A BS= The k middle switchesA = middle switches reachable from the inputsB = middle switches reachable from the outputsOur case:|S|=k|A| k-(n-1)|B| k-(n-1)

Clos Network - strict sense non-blockingHolds for k 2n-1Proof:Consider an idle input and outputInput box connected to at most n-1 middle layer switchesoutput box connected to at most n-1 middle layer switchesThere exists an unused" middle switch good for both.

ExampleClos(8,2,3)Need to route a new call

Clos NetworkWhy is k=n internally blocking?

Clos Network - re-arrangableHolds for k nProof:Consider the routing graph.find a perfect matching.route the perfect matching through asingle middle switch!remaining network is Clos(N-N/n,n-1,k-1)summary:smaller circuitweaker guaranteeMulticast ?

Recursive Construction: basisThe basic element:The two states:The dimension: r=0

Recursive Construction: Benes Networkr-1 dimension N/2 size

r-1 dimension N/2 size

Example 16x16

Benes NetworksSymmetrySize:F(N) = 2(N/2)*4 + 2F(N/2) = O(N log N)RearrangableClos network with k=2 n=2Proof I:Build routing graph.Find 2 matchingsroute one in the upper Benes and the other in the lower.

Greedy permutation routing Start with an arbitrary node i1 set i1 to upper.At the output, o1 , a new constraint,set o2 to lower.Continue until no new constraint.Completing a cycle.Continue until done.Solve for the upper and lower Benes recursively.

Example: Benes Network for r=2level 0 switcheslevel 2r switchesI1I212

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CRS-1 Switch Fabric Overview1 of 82 of 88 of 8128121640 GbpsLine CardLine Card50 Gbps 136 Bytes cellsFabric Chassis100 Gbps/LC(2) (2.5X Speedup)1296 x 1296 buffered non-blocking switch Multi-stage Interconnect3 Stage Benes topologyS1S2S3S1S2S3S1S2S32 LEVELS OF PRIORITYHP Low latency trafficLP Best effort trafficMULTICAST SUPPORT1M multicast groups

Basic Router Architecture3 Main components: Line cards,Switching mechanism, Route Processor(s), Routing ApplicationsControl ComponentsForwarding ComponentInterconnect

Strict Sense non-BlockingN/2 x N/2N/2 x N/2......N/2 x N/2

PropertiesSize:F(N) = 2N*6 + 3F(N/2) = O( N1.58 )strict sense non-blockingClos network with k=3 n=2Better parameters:n=sqrt{N}, k=2sqrt{N}-1recursive size sqrt{N} x sqrt{N}Circuit size O(N log2.58 N)

Cantor Networksm copies of Benes network.For m = log N its strict sense non-blockingNetwork size N log2 NExample

Cantor Networkm=4

Proof Sketch:Benes network: 2 log N -1 layers, N/2 nodes in layer.Middle layer= layer log N -1Consider the middle layer of the Benes Networks.There are Nm/2 nodes in in all of them combined.Bound (from below) the number of nodes reachable from an input and output.If the sum is more than Nm/2:There is an intersection there has to be a route.

Proof Sketch:Let A(k) = number of nodes reachable at level k.A(0)=m A(1)= 2A(0)-1A(2)=2A(1)-2A(k)=2A(k-1) - 2k-1 = 2k A(0) - k 2k-1A(log N -1) = Nm/2 - (log N -1) N/4Need that: 2A(log N -1) > Nm/2.2[Nm/2 - (log N -1) N/4] > Nm/2.Hold for m> log N-1.

Advanced constructionsThere are networks of size O(N log N).the constants are huge!Basic paradigm also applies to large packet switches.

Proof Sketch:Let A(k) = number of nodes reachable at level k.A(0)=m A(1)= 2A(0)-1A(2)=2A(1)-2A(k)=2A(k-1) - 2k-2 = 2k-1 A(1) - (k-1) 2k-2A(log N) = Nm/2 - (log N -1) N/4Need that: 2A(log N) > Nm/2.Hold for m> log N-1.

*87Inexpensive PAROLI optics - up to 100m between LC chassis and Switch FabricLine Card count has increased because now at 16 vs 14 LCs/rack