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Amplifier Design Tutorial Introduction This tutorial will set out the design stages required to design a theoretical microwave amplifier with the following specification shown in Table 1: Table 1 Required Specification Parameter Frequency Gain Noise Figure Output VSWR Gain ripple Units GHz dB dB dB

1.45 1.55 12.5 0.2 2.0 1:1.5 (>13dB) < 1.5

The first stage in the design process is to pick a suitable device. For X-Band and above GaAs MESFETS are used while at lower frequencies Bipolar devices are used if noise is not so critical. Try to pick a device design for the range of frequencies you require. Dont for example use an X-band device for an LNA at UHF you are bound to run into stability problems. Also pick a device that will give you plenty of gain margin to allow for noise mismatching etc. For this design an Agilent AT41435 Bipolar transistor has been used. This device has > 14dB of gain at 2GHz with an associated noise figure of 1. The ADS simulation shown in Figure 1 has been setup to calculate K factor and plot minimum noise figure.

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S-PARAMETERSS_Param SP1 Start=1.0 GHz Stop=2.0 GHz Step= CalcNoise=yes sp_hp_AT-41435_1_19921201 SNP1 Bias="Bjt: Vce=8V Ic=10mA" Frequency="{0.10 - 6.00} GHz" Noise Frequency="{0.10 - 4.00} GHz"

Term Term1 Num=1 Z=50 Ohm

Term Term2 Num=2 Z=50 Ohm

StabFact

StabFact StabFact1 StabFact1=stab_fact(S)

Figure 1 ADS simulation to calculate K and minimum noise figure. The resistorcapacitor combination connected between the gate and source are to ensure that the device is unconditionally stable at 1.5GHz.2.0

1.8

nf(2)

m1 freq=1.526GHz nf(2)=1.589

m1

1.6

1.4

1.2 1.0 1.2 1.4 1.6 1.8 2.0

freq, GHz freq 1.000GHz 1.053GHz 1.105GHz 1.158GHz 1.211GHz 1.263GHz 1.316GHz 1.368GHz 1.421GHz 1.474GHz 1.526GHz 1.579GHz 1.632GHz 1.684GHz 1.737GHz 1.789GHz 1.842GHz 1.895GHz 1.947GHz StabFact1 0.944 0.950 0.958 0.968 0.980 0.995 1.012 1.032 1.056 1.083 1.097 1.097 1.098 1.100 1.104 1.110 1.116 1.124 1.134

Figure 2 Results from the simulation shown in Figure 1, showing a K factor >= 1 at 1.4GHz and a minimum noise figure of 1.65dB at our highest frequency of 1.6GHz.

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General Amplifier Design Procedure Now that we have picked our device, stabilised it and checked its maximum available gain we can begin the process of designing the LNA. This process consists of the following steps:(1) Evaluate the Rolletts stability factor to identify the possibility of instabilities depending on source and load matching. (2) Determine Bias conditions and circuit. (3) If a specified gain is required at a single frequency then the gain circles can be plotted on a Smith chart and the associated source match can be read off and the corresponding load match calculated. Careful consideration must be taken to the position of the source match in relation to the stability circles. (4) If a specified noise figure and gain at a frequency is required then the noise circles need to be added to the gain circles from (ii). The source match required will be the intersection of the required gain & noise circles. Again careful consideration must be given to the position of the source match in relation to the stability circles. (5) Once the required source impedance has been chosen the corresponding output match required for best return loss can be calculated. Gain & Noise Parameters Using the S-parameters of the device it is possible to calculate the overall transducer gain which consists of three parts, the gain factor of the input (source) matching network, the active device and the output (load) matching network:Gs = 1 s2 2

1 in .s2

G o = S 21

GL =

1 s

2 2

1 S 22 .L

Overall Transducer gain = 10LOG10 (G s .G o .GL ) For the unilateral case where S12 = 0 (and a stable device) the above equations can be simplified to the following : Gs = 1 1 S112 2

G o = S 21 GL =

1 1 S 222

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For rough estimate of the maximum gain available we can assume that S12 = 0 therefore at 1.5GHz (Assuming a bias of 8V @ 10mA) the estimated gain is:Gs = 1 1 S 112 2

=

1 1 - 0.382 2

= 1.17 = 0.68dB

G o = S 21 = 4.63 = 21.43 = 13.31dB GL = 1 1 S 222

=

1 1 - 0.482

= 1.29 = 1.14dB

Total available gain = 0.68 + 13.31 + 1.14 = 15.13dB Constant Gain circlesD 2 = S 222

2

C 2 = S 22 S 11 * Gain desired (absolute ie not in dB) S 212

Gain = G =

Location of gain circle ro =

G.C 2 * 1 + D 2 .G 1 - 2K S 12 .S 21 .G + S 12 .S 21 .G 2 1 + D 2 .G2

Radius of gain circle p o =

Note the 0dB gain circle will always pass through the centre of the Smith chart.

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Constant Noise circles Formula for calculation of noise circles:N= F - Fmin 1 + opt 4R N Zo2

Where F

= required noise figure (noise factor = 10

NFdB 10

) )

Fmin = Optimum noise figure (noise factor = 10 R N = Equivalent noise resistance of transistor

NFmin dB 10

opt = Reflection coefficien t to achieve optimum noise opt N+1 N N + 1 - opt N +1

Centre of noise figure circle =

and the radius of the noise figure circle is =

(

2

)

The values of Fmin, RN and opt are given in the manufacturers data sheet. However remember that that the parallel feedback resistor will now have modified the device noise parameters. Calculating these circles by hand is luckily not required these days, as this can be performed using the CAD simulator but before we progress to gain & noise we need to check on the stability of the device. Refer to the stability tutorial for a discussion of stability circles etc.

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Specifically we need to find the no-go matching zones that may cause the circuit to oscillate if we place these matches to the device. Again this is best performed using the CAD the ADS simulation shown in Figure 3 has the basic FET device with stability circle simulation boxes.

S-PARAMETERSS_Param SP1 Start=1.0 GHz Stop=2.0 GHz Step= CalcNoise=yes sp_hp_AT-41435_1_19921201 SNP1 Bias="Bjt: Vce=8V Ic=10mA" Frequency="{0.10 - 6.00} GHz" Noise Frequency="{0.10 - 4.00} GHz"

SStabCircle

Term Term1 Num=1 Z=50 Ohm

Term Term2 Num=2 Z=50 Ohm

S_StabCircle S_StabCircle1 S_StabCircle1=s_stab_circle(S,51)

Figure 3 ADS setup to simulate the Agilent AT41435 using a S-parameter simulator and output the input stability circles. The results from the ADS simulation (Figure 3) shows that the device is conditionally stable as the stability circles clip the edge of the smith chart so that there is a possibility of instability, if a match is placed on the device source with an impedance within the area of the smith chart covered by the stability circle (as shown by the shaded area).S_StabCircle1=1.009 / 179.579 freq=1.315789GHz impedance = Z0 * (-0.004 + j0.004)

S_ St ab m1 Cir cle 1

indep(S_StabCircle1) (0.000 to 51.000)

Figure 4 Result of the circuit simulation showing the input stability circles. The stability circles are outside the smith chart so that for any match applied to the device, the device will be unconditionally stable.

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We can now plot the gain circles and noise circles. The idea is to choose a matching point on the 10dB source and load constant gain circles and ensure the input matching point is either on the 2dB noise circle or within it. To perform the simulation we need to add the gain mismatch and noise mismatch simulator boxes, note too that the noise feature has been switched on in the S-parameter simulator box. The simulation is shown in Figure 5.

S-PARAMETERSS_Param SP1 Start=0.5 GHz Stop=3.5 GHz CalcNoise=yes

Term Term1 Num=1 Z=50 Ohm

Term Term2 Num=2 Z=50 Ohm

Meas SmGamma1 Eqn smg1 match_input=sm_gamma1(S) Meas SmGamma2 Eqn smg2 match_output=sm_gamma2(S) Meas SmZ1 Eqn smz1 smz_in=sm_z1(S,PortZ1) smz_out=sm_z2(S,PortZ2)

sp_hp_AT-41435_1_19921201 SNP1 Bias="Bjt: Vce=8V Ic=10mA" Frequency="{0.10 - 6.00} GHz" Noise Frequency="{0.10 - 4.00} GHz"

Figure 5 ADS simulation showing the modified S-parameter simulation box set to include noise. The other measurement boxes are: SmGamma1 which, returns the simultaneous-match input-reflection coefficient. SmGamma2 which, returns the simultaneous-match output-reflection coefficient. Sm_z1 which, returns the simultaneous-match input impedance.

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m1 indep(m1)=4 GAcircles=0.337 / 48.137 gain=12.759112 impedance = Z0 * (1.335 + j0.75

m3 indep(m3)=3 Noise_circles=0.399 / 42.894 ns figure=1.900000 impedance = Z0 * (1.463 + j0.94

Eqn num_NFcircles=4 m3 m1Noise_circles Noise_circleMin GAcircles GAcircleM ax

Eqn NFstep_size=.1

Set step sizes and number of circles, here.

Eqn Noise_circles=ns_circle(NFmin[m2]+NFstep_size*[0::num_NFcircles],NFmin[m2],Sopt[m2],Rn[m2]/50,51) Eqn Noise_circleMin=ns_circle(NFmin[m2],NFmin[m2],Sopt[m2],Rn[m2]/50,51) Eqn num_GAcircles=6 Eqn GAstep_size=1 Eqn GAcircles=ga_circle(S[m2],max_gain(S[m2])-GAstep_size*[0::num_GAcircles]) Eqn GAcircleMax=ga_circle(S[m2],max_gain(S[m2]))

indep(GAcircleMax) (0.000 to 51.000) cir_pts (0.000 to 51.000) indep(Noise_circleMin) (0.000 to 51.000)

RF Frequency Selector100 [0::sweep_size(freq)-1] 80 60 40 20 0

m2

m2 indep(m2)=1500000000.000 vs([0::sweep_size(freq)-1],freq)=33.000

Figure 6 Data display setup to plot gain and noise circles. The slider m2 on the frequency selector can be moved to display the noise and gain circles at other frequencies.

400.M

600.M

1.00G 800.M

1.20G

1.40G

1.60G

1.80G

freq, Hz

2.00G

2.20G

2.40G

2.60G

3.00G 2.80G

3.20G

3.40G

3.60G

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m1 indep(m1)=4 GAcircles=0.337 / 48.137 gain=12.759112 impedance = Z0 * (1.335 + j0.755)Noise_circles Noise_circleMin

m3 indep(m3)=45 Noise_circles=0.252 / -30.384 ns figure=1.900000 impedance = Z0 * (1.490 - j0.406)

m1 m3

GAcircles

GAcircleMax

indep(GAcircleMax) (0.000 to 51.000) cir_pts (0.000 to 51.000) indep(Noise_circleMin) (0.000 to 51.000)Figure 7 The diagram shows a smith chart with constant gain and noise circles plotted. The brown circles show the constant noise circles with the blue dot showing the optimum noise point. The red circle shows the constant maximum available gain and the green circles are the constant gain circles. Marker 1 has been placed on the 12.5dB constant gain circle with the 2.0dB constant noise circle is indicated by marker 3. If we place a load at marker 1 ie an impedance of 1.335+j0.75 to the input of the Bipolar transistor then we should have an amplifier with 12.5dB of gain and a noise figure of 20dB at 1.45GHz.

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Final design To physically realise the design we need to add the RF bias circuits and DC blocks. The RF bias circuits consist of wave inductive lines connected to a wave capacitive open-circuit stub (See tutorial on Bias Circuits for more details). The final schematic layout of the amplifier together with the RF bias circuits is shown in Figure 13. As a final check it is a good idea to perform a wide-band analysis of the circuit to ensure that at all frequencies S11 and S22 < 0. The wide-band plots of the circuit are shown in Figure 14.

Collector Bias Base Bias

50-ohm chip resistor L = 22mm(100) L = 21.2mm (102)

L = 7.6mm (36) AT41435 L = 8.6mm (39)

Figure 13 Final Amplifier schematic layout with RF bias circuits added, together with blocking capacitors.

As can be seen although the pass-band amplifier response is compliant with a pass-band gain ripple of